1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 4 * License terms: GNU General Public License (GPL), version 2 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/of_address.h> 15 #include <linux/of_irq.h> 16 17 #define IRQS_PER_BANK 32 18 19 struct stm32_exti_bank { 20 u32 imr_ofst; 21 u32 emr_ofst; 22 u32 rtsr_ofst; 23 u32 ftsr_ofst; 24 u32 swier_ofst; 25 u32 pr_ofst; 26 }; 27 28 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 29 .imr_ofst = 0x00, 30 .emr_ofst = 0x04, 31 .rtsr_ofst = 0x08, 32 .ftsr_ofst = 0x0C, 33 .swier_ofst = 0x10, 34 .pr_ofst = 0x14, 35 }; 36 37 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 38 &stm32f4xx_exti_b1, 39 }; 40 41 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 42 { 43 const struct stm32_exti_bank *stm32_bank = gc->private; 44 45 return irq_reg_readl(gc, stm32_bank->pr_ofst); 46 } 47 48 static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask) 49 { 50 const struct stm32_exti_bank *stm32_bank = gc->private; 51 52 irq_reg_writel(gc, mask, stm32_bank->pr_ofst); 53 } 54 55 static void stm32_irq_handler(struct irq_desc *desc) 56 { 57 struct irq_domain *domain = irq_desc_get_handler_data(desc); 58 struct irq_chip *chip = irq_desc_get_chip(desc); 59 unsigned int virq, nbanks = domain->gc->num_chips; 60 struct irq_chip_generic *gc; 61 const struct stm32_exti_bank *stm32_bank; 62 unsigned long pending; 63 int n, i, irq_base = 0; 64 65 chained_irq_enter(chip, desc); 66 67 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 68 gc = irq_get_domain_generic_chip(domain, irq_base); 69 stm32_bank = gc->private; 70 71 while ((pending = stm32_exti_pending(gc))) { 72 for_each_set_bit(n, &pending, IRQS_PER_BANK) { 73 virq = irq_find_mapping(domain, irq_base + n); 74 generic_handle_irq(virq); 75 stm32_exti_irq_ack(gc, BIT(n)); 76 } 77 } 78 } 79 80 chained_irq_exit(chip, desc); 81 } 82 83 static int stm32_irq_set_type(struct irq_data *data, unsigned int type) 84 { 85 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 86 const struct stm32_exti_bank *stm32_bank = gc->private; 87 int pin = data->hwirq % IRQS_PER_BANK; 88 u32 rtsr, ftsr; 89 90 irq_gc_lock(gc); 91 92 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 93 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 94 95 switch (type) { 96 case IRQ_TYPE_EDGE_RISING: 97 rtsr |= BIT(pin); 98 ftsr &= ~BIT(pin); 99 break; 100 case IRQ_TYPE_EDGE_FALLING: 101 rtsr &= ~BIT(pin); 102 ftsr |= BIT(pin); 103 break; 104 case IRQ_TYPE_EDGE_BOTH: 105 rtsr |= BIT(pin); 106 ftsr |= BIT(pin); 107 break; 108 default: 109 irq_gc_unlock(gc); 110 return -EINVAL; 111 } 112 113 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 114 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 115 116 irq_gc_unlock(gc); 117 118 return 0; 119 } 120 121 static int stm32_irq_set_wake(struct irq_data *data, unsigned int on) 122 { 123 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 124 const struct stm32_exti_bank *stm32_bank = gc->private; 125 int pin = data->hwirq % IRQS_PER_BANK; 126 u32 emr; 127 128 irq_gc_lock(gc); 129 130 emr = irq_reg_readl(gc, stm32_bank->emr_ofst); 131 if (on) 132 emr |= BIT(pin); 133 else 134 emr &= ~BIT(pin); 135 irq_reg_writel(gc, emr, stm32_bank->emr_ofst); 136 137 irq_gc_unlock(gc); 138 139 return 0; 140 } 141 142 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 143 unsigned int nr_irqs, void *data) 144 { 145 struct irq_chip_generic *gc; 146 struct irq_fwspec *fwspec = data; 147 irq_hw_number_t hwirq; 148 149 hwirq = fwspec->param[0]; 150 gc = irq_get_domain_generic_chip(d, hwirq); 151 152 irq_map_generic_chip(d, virq, hwirq); 153 irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc, 154 handle_simple_irq, NULL, NULL); 155 156 return 0; 157 } 158 159 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 160 unsigned int nr_irqs) 161 { 162 struct irq_data *data = irq_domain_get_irq_data(d, virq); 163 164 irq_domain_reset_irq_data(data); 165 } 166 167 struct irq_domain_ops irq_exti_domain_ops = { 168 .map = irq_map_generic_chip, 169 .xlate = irq_domain_xlate_onetwocell, 170 .alloc = stm32_exti_alloc, 171 .free = stm32_exti_free, 172 }; 173 174 static int 175 __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks, 176 int bank_nr, struct device_node *node) 177 { 178 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 179 int nr_irqs, nr_exti, ret, i; 180 struct irq_chip_generic *gc; 181 struct irq_domain *domain; 182 void *base; 183 184 base = of_iomap(node, 0); 185 if (!base) { 186 pr_err("%pOF: Unable to map registers\n", node); 187 return -ENOMEM; 188 } 189 190 domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK, 191 &irq_exti_domain_ops, NULL); 192 if (!domain) { 193 pr_err("%s: Could not register interrupt domain.\n", 194 node->name); 195 ret = -ENOMEM; 196 goto out_unmap; 197 } 198 199 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 200 handle_edge_irq, clr, 0, 0); 201 if (ret) { 202 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 203 node); 204 goto out_free_domain; 205 } 206 207 for (i = 0; i < bank_nr; i++) { 208 const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i]; 209 u32 irqs_mask; 210 211 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 212 213 gc->reg_base = base; 214 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 215 gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit; 216 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 217 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 218 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 219 gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake; 220 gc->chip_types->regs.ack = stm32_bank->pr_ofst; 221 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 222 gc->private = (void *)stm32_bank; 223 224 /* Determine number of irqs supported */ 225 writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst); 226 irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst); 227 nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst)); 228 writel_relaxed(0, base + stm32_bank->rtsr_ofst); 229 230 pr_info("%s: bank%d, External IRQs available:%#x\n", 231 node->full_name, i, irqs_mask); 232 } 233 234 nr_irqs = of_irq_count(node); 235 for (i = 0; i < nr_irqs; i++) { 236 unsigned int irq = irq_of_parse_and_map(node, i); 237 238 irq_set_handler_data(irq, domain); 239 irq_set_chained_handler(irq, stm32_irq_handler); 240 } 241 242 return 0; 243 244 out_free_domain: 245 irq_domain_remove(domain); 246 out_unmap: 247 iounmap(base); 248 return ret; 249 } 250 251 static int __init stm32f4_exti_of_init(struct device_node *np, 252 struct device_node *parent) 253 { 254 return stm32_exti_init(stm32f4xx_exti_banks, 255 ARRAY_SIZE(stm32f4xx_exti_banks), np); 256 } 257 258 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 259