1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) Maxime Coquelin 2015 4 * Copyright (C) STMicroelectronics 2017 5 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/delay.h> 10 #include <linux/hwspinlock.h> 11 #include <linux/interrupt.h> 12 #include <linux/io.h> 13 #include <linux/irq.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqchip/chained_irq.h> 16 #include <linux/irqdomain.h> 17 #include <linux/module.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/of_platform.h> 21 #include <linux/syscore_ops.h> 22 23 #include <dt-bindings/interrupt-controller/arm-gic.h> 24 25 #define IRQS_PER_BANK 32 26 27 #define HWSPNLCK_TIMEOUT 1000 /* usec */ 28 29 struct stm32_exti_bank { 30 u32 imr_ofst; 31 u32 emr_ofst; 32 u32 rtsr_ofst; 33 u32 ftsr_ofst; 34 u32 swier_ofst; 35 u32 rpr_ofst; 36 u32 fpr_ofst; 37 }; 38 39 #define UNDEF_REG ~0 40 41 struct stm32_desc_irq { 42 u32 exti; 43 u32 irq_parent; 44 }; 45 46 struct stm32_exti_drv_data { 47 const struct stm32_exti_bank **exti_banks; 48 const struct stm32_desc_irq *desc_irqs; 49 u32 bank_nr; 50 u32 irq_nr; 51 }; 52 53 struct stm32_exti_chip_data { 54 struct stm32_exti_host_data *host_data; 55 const struct stm32_exti_bank *reg_bank; 56 struct raw_spinlock rlock; 57 u32 wake_active; 58 u32 mask_cache; 59 u32 rtsr_cache; 60 u32 ftsr_cache; 61 }; 62 63 struct stm32_exti_host_data { 64 void __iomem *base; 65 struct stm32_exti_chip_data *chips_data; 66 const struct stm32_exti_drv_data *drv_data; 67 struct hwspinlock *hwlock; 68 }; 69 70 static struct stm32_exti_host_data *stm32_host_data; 71 72 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 73 .imr_ofst = 0x00, 74 .emr_ofst = 0x04, 75 .rtsr_ofst = 0x08, 76 .ftsr_ofst = 0x0C, 77 .swier_ofst = 0x10, 78 .rpr_ofst = 0x14, 79 .fpr_ofst = UNDEF_REG, 80 }; 81 82 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 83 &stm32f4xx_exti_b1, 84 }; 85 86 static const struct stm32_exti_drv_data stm32f4xx_drv_data = { 87 .exti_banks = stm32f4xx_exti_banks, 88 .bank_nr = ARRAY_SIZE(stm32f4xx_exti_banks), 89 }; 90 91 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 92 .imr_ofst = 0x80, 93 .emr_ofst = 0x84, 94 .rtsr_ofst = 0x00, 95 .ftsr_ofst = 0x04, 96 .swier_ofst = 0x08, 97 .rpr_ofst = 0x88, 98 .fpr_ofst = UNDEF_REG, 99 }; 100 101 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 102 .imr_ofst = 0x90, 103 .emr_ofst = 0x94, 104 .rtsr_ofst = 0x20, 105 .ftsr_ofst = 0x24, 106 .swier_ofst = 0x28, 107 .rpr_ofst = 0x98, 108 .fpr_ofst = UNDEF_REG, 109 }; 110 111 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 112 .imr_ofst = 0xA0, 113 .emr_ofst = 0xA4, 114 .rtsr_ofst = 0x40, 115 .ftsr_ofst = 0x44, 116 .swier_ofst = 0x48, 117 .rpr_ofst = 0xA8, 118 .fpr_ofst = UNDEF_REG, 119 }; 120 121 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 122 &stm32h7xx_exti_b1, 123 &stm32h7xx_exti_b2, 124 &stm32h7xx_exti_b3, 125 }; 126 127 static const struct stm32_exti_drv_data stm32h7xx_drv_data = { 128 .exti_banks = stm32h7xx_exti_banks, 129 .bank_nr = ARRAY_SIZE(stm32h7xx_exti_banks), 130 }; 131 132 static const struct stm32_exti_bank stm32mp1_exti_b1 = { 133 .imr_ofst = 0x80, 134 .emr_ofst = 0x84, 135 .rtsr_ofst = 0x00, 136 .ftsr_ofst = 0x04, 137 .swier_ofst = 0x08, 138 .rpr_ofst = 0x0C, 139 .fpr_ofst = 0x10, 140 }; 141 142 static const struct stm32_exti_bank stm32mp1_exti_b2 = { 143 .imr_ofst = 0x90, 144 .emr_ofst = 0x94, 145 .rtsr_ofst = 0x20, 146 .ftsr_ofst = 0x24, 147 .swier_ofst = 0x28, 148 .rpr_ofst = 0x2C, 149 .fpr_ofst = 0x30, 150 }; 151 152 static const struct stm32_exti_bank stm32mp1_exti_b3 = { 153 .imr_ofst = 0xA0, 154 .emr_ofst = 0xA4, 155 .rtsr_ofst = 0x40, 156 .ftsr_ofst = 0x44, 157 .swier_ofst = 0x48, 158 .rpr_ofst = 0x4C, 159 .fpr_ofst = 0x50, 160 }; 161 162 static const struct stm32_exti_bank *stm32mp1_exti_banks[] = { 163 &stm32mp1_exti_b1, 164 &stm32mp1_exti_b2, 165 &stm32mp1_exti_b3, 166 }; 167 168 static const struct stm32_desc_irq stm32mp1_desc_irq[] = { 169 { .exti = 0, .irq_parent = 6 }, 170 { .exti = 1, .irq_parent = 7 }, 171 { .exti = 2, .irq_parent = 8 }, 172 { .exti = 3, .irq_parent = 9 }, 173 { .exti = 4, .irq_parent = 10 }, 174 { .exti = 5, .irq_parent = 23 }, 175 { .exti = 6, .irq_parent = 64 }, 176 { .exti = 7, .irq_parent = 65 }, 177 { .exti = 8, .irq_parent = 66 }, 178 { .exti = 9, .irq_parent = 67 }, 179 { .exti = 10, .irq_parent = 40 }, 180 { .exti = 11, .irq_parent = 42 }, 181 { .exti = 12, .irq_parent = 76 }, 182 { .exti = 13, .irq_parent = 77 }, 183 { .exti = 14, .irq_parent = 121 }, 184 { .exti = 15, .irq_parent = 127 }, 185 { .exti = 16, .irq_parent = 1 }, 186 { .exti = 65, .irq_parent = 144 }, 187 { .exti = 68, .irq_parent = 143 }, 188 { .exti = 73, .irq_parent = 129 }, 189 }; 190 191 static const struct stm32_exti_drv_data stm32mp1_drv_data = { 192 .exti_banks = stm32mp1_exti_banks, 193 .bank_nr = ARRAY_SIZE(stm32mp1_exti_banks), 194 .desc_irqs = stm32mp1_desc_irq, 195 .irq_nr = ARRAY_SIZE(stm32mp1_desc_irq), 196 }; 197 198 static int stm32_exti_to_irq(const struct stm32_exti_drv_data *drv_data, 199 irq_hw_number_t hwirq) 200 { 201 const struct stm32_desc_irq *desc_irq; 202 int i; 203 204 if (!drv_data->desc_irqs) 205 return -EINVAL; 206 207 for (i = 0; i < drv_data->irq_nr; i++) { 208 desc_irq = &drv_data->desc_irqs[i]; 209 if (desc_irq->exti == hwirq) 210 return desc_irq->irq_parent; 211 } 212 213 return -EINVAL; 214 } 215 216 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 217 { 218 struct stm32_exti_chip_data *chip_data = gc->private; 219 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 220 unsigned long pending; 221 222 pending = irq_reg_readl(gc, stm32_bank->rpr_ofst); 223 if (stm32_bank->fpr_ofst != UNDEF_REG) 224 pending |= irq_reg_readl(gc, stm32_bank->fpr_ofst); 225 226 return pending; 227 } 228 229 static void stm32_irq_handler(struct irq_desc *desc) 230 { 231 struct irq_domain *domain = irq_desc_get_handler_data(desc); 232 struct irq_chip *chip = irq_desc_get_chip(desc); 233 unsigned int virq, nbanks = domain->gc->num_chips; 234 struct irq_chip_generic *gc; 235 unsigned long pending; 236 int n, i, irq_base = 0; 237 238 chained_irq_enter(chip, desc); 239 240 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 241 gc = irq_get_domain_generic_chip(domain, irq_base); 242 243 while ((pending = stm32_exti_pending(gc))) { 244 for_each_set_bit(n, &pending, IRQS_PER_BANK) { 245 virq = irq_find_mapping(domain, irq_base + n); 246 generic_handle_irq(virq); 247 } 248 } 249 } 250 251 chained_irq_exit(chip, desc); 252 } 253 254 static int stm32_exti_set_type(struct irq_data *d, 255 unsigned int type, u32 *rtsr, u32 *ftsr) 256 { 257 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 258 259 switch (type) { 260 case IRQ_TYPE_EDGE_RISING: 261 *rtsr |= mask; 262 *ftsr &= ~mask; 263 break; 264 case IRQ_TYPE_EDGE_FALLING: 265 *rtsr &= ~mask; 266 *ftsr |= mask; 267 break; 268 case IRQ_TYPE_EDGE_BOTH: 269 *rtsr |= mask; 270 *ftsr |= mask; 271 break; 272 default: 273 return -EINVAL; 274 } 275 276 return 0; 277 } 278 279 static int stm32_irq_set_type(struct irq_data *d, unsigned int type) 280 { 281 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 282 struct stm32_exti_chip_data *chip_data = gc->private; 283 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 284 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 285 u32 rtsr, ftsr; 286 int err; 287 288 irq_gc_lock(gc); 289 290 if (hwlock) { 291 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 292 if (err) { 293 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 294 goto unlock; 295 } 296 } 297 298 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 299 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 300 301 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 302 if (err) 303 goto unspinlock; 304 305 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 306 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 307 308 unspinlock: 309 if (hwlock) 310 hwspin_unlock_in_atomic(hwlock); 311 unlock: 312 irq_gc_unlock(gc); 313 314 return err; 315 } 316 317 static void stm32_chip_suspend(struct stm32_exti_chip_data *chip_data, 318 u32 wake_active) 319 { 320 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 321 void __iomem *base = chip_data->host_data->base; 322 323 /* save rtsr, ftsr registers */ 324 chip_data->rtsr_cache = readl_relaxed(base + stm32_bank->rtsr_ofst); 325 chip_data->ftsr_cache = readl_relaxed(base + stm32_bank->ftsr_ofst); 326 327 writel_relaxed(wake_active, base + stm32_bank->imr_ofst); 328 } 329 330 static void stm32_chip_resume(struct stm32_exti_chip_data *chip_data, 331 u32 mask_cache) 332 { 333 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 334 void __iomem *base = chip_data->host_data->base; 335 336 /* restore rtsr, ftsr, registers */ 337 writel_relaxed(chip_data->rtsr_cache, base + stm32_bank->rtsr_ofst); 338 writel_relaxed(chip_data->ftsr_cache, base + stm32_bank->ftsr_ofst); 339 340 writel_relaxed(mask_cache, base + stm32_bank->imr_ofst); 341 } 342 343 static void stm32_irq_suspend(struct irq_chip_generic *gc) 344 { 345 struct stm32_exti_chip_data *chip_data = gc->private; 346 347 irq_gc_lock(gc); 348 stm32_chip_suspend(chip_data, gc->wake_active); 349 irq_gc_unlock(gc); 350 } 351 352 static void stm32_irq_resume(struct irq_chip_generic *gc) 353 { 354 struct stm32_exti_chip_data *chip_data = gc->private; 355 356 irq_gc_lock(gc); 357 stm32_chip_resume(chip_data, gc->mask_cache); 358 irq_gc_unlock(gc); 359 } 360 361 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 362 unsigned int nr_irqs, void *data) 363 { 364 struct irq_fwspec *fwspec = data; 365 irq_hw_number_t hwirq; 366 367 hwirq = fwspec->param[0]; 368 369 irq_map_generic_chip(d, virq, hwirq); 370 371 return 0; 372 } 373 374 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 375 unsigned int nr_irqs) 376 { 377 struct irq_data *data = irq_domain_get_irq_data(d, virq); 378 379 irq_domain_reset_irq_data(data); 380 } 381 382 static const struct irq_domain_ops irq_exti_domain_ops = { 383 .map = irq_map_generic_chip, 384 .alloc = stm32_exti_alloc, 385 .free = stm32_exti_free, 386 }; 387 388 static void stm32_irq_ack(struct irq_data *d) 389 { 390 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); 391 struct stm32_exti_chip_data *chip_data = gc->private; 392 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 393 394 irq_gc_lock(gc); 395 396 irq_reg_writel(gc, d->mask, stm32_bank->rpr_ofst); 397 if (stm32_bank->fpr_ofst != UNDEF_REG) 398 irq_reg_writel(gc, d->mask, stm32_bank->fpr_ofst); 399 400 irq_gc_unlock(gc); 401 } 402 403 static inline u32 stm32_exti_set_bit(struct irq_data *d, u32 reg) 404 { 405 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 406 void __iomem *base = chip_data->host_data->base; 407 u32 val; 408 409 val = readl_relaxed(base + reg); 410 val |= BIT(d->hwirq % IRQS_PER_BANK); 411 writel_relaxed(val, base + reg); 412 413 return val; 414 } 415 416 static inline u32 stm32_exti_clr_bit(struct irq_data *d, u32 reg) 417 { 418 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 419 void __iomem *base = chip_data->host_data->base; 420 u32 val; 421 422 val = readl_relaxed(base + reg); 423 val &= ~BIT(d->hwirq % IRQS_PER_BANK); 424 writel_relaxed(val, base + reg); 425 426 return val; 427 } 428 429 static void stm32_exti_h_eoi(struct irq_data *d) 430 { 431 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 432 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 433 434 raw_spin_lock(&chip_data->rlock); 435 436 stm32_exti_set_bit(d, stm32_bank->rpr_ofst); 437 if (stm32_bank->fpr_ofst != UNDEF_REG) 438 stm32_exti_set_bit(d, stm32_bank->fpr_ofst); 439 440 raw_spin_unlock(&chip_data->rlock); 441 442 if (d->parent_data->chip) 443 irq_chip_eoi_parent(d); 444 } 445 446 static void stm32_exti_h_mask(struct irq_data *d) 447 { 448 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 449 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 450 451 raw_spin_lock(&chip_data->rlock); 452 chip_data->mask_cache = stm32_exti_clr_bit(d, stm32_bank->imr_ofst); 453 raw_spin_unlock(&chip_data->rlock); 454 455 if (d->parent_data->chip) 456 irq_chip_mask_parent(d); 457 } 458 459 static void stm32_exti_h_unmask(struct irq_data *d) 460 { 461 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 462 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 463 464 raw_spin_lock(&chip_data->rlock); 465 chip_data->mask_cache = stm32_exti_set_bit(d, stm32_bank->imr_ofst); 466 raw_spin_unlock(&chip_data->rlock); 467 468 if (d->parent_data->chip) 469 irq_chip_unmask_parent(d); 470 } 471 472 static int stm32_exti_h_set_type(struct irq_data *d, unsigned int type) 473 { 474 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 475 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 476 struct hwspinlock *hwlock = chip_data->host_data->hwlock; 477 void __iomem *base = chip_data->host_data->base; 478 u32 rtsr, ftsr; 479 int err; 480 481 raw_spin_lock(&chip_data->rlock); 482 483 if (hwlock) { 484 err = hwspin_lock_timeout_in_atomic(hwlock, HWSPNLCK_TIMEOUT); 485 if (err) { 486 pr_err("%s can't get hwspinlock (%d)\n", __func__, err); 487 goto unlock; 488 } 489 } 490 491 rtsr = readl_relaxed(base + stm32_bank->rtsr_ofst); 492 ftsr = readl_relaxed(base + stm32_bank->ftsr_ofst); 493 494 err = stm32_exti_set_type(d, type, &rtsr, &ftsr); 495 if (err) 496 goto unspinlock; 497 498 writel_relaxed(rtsr, base + stm32_bank->rtsr_ofst); 499 writel_relaxed(ftsr, base + stm32_bank->ftsr_ofst); 500 501 unspinlock: 502 if (hwlock) 503 hwspin_unlock_in_atomic(hwlock); 504 unlock: 505 raw_spin_unlock(&chip_data->rlock); 506 507 return err; 508 } 509 510 static int stm32_exti_h_set_wake(struct irq_data *d, unsigned int on) 511 { 512 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 513 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 514 515 raw_spin_lock(&chip_data->rlock); 516 517 if (on) 518 chip_data->wake_active |= mask; 519 else 520 chip_data->wake_active &= ~mask; 521 522 raw_spin_unlock(&chip_data->rlock); 523 524 return 0; 525 } 526 527 static int stm32_exti_h_set_affinity(struct irq_data *d, 528 const struct cpumask *dest, bool force) 529 { 530 if (d->parent_data->chip) 531 return irq_chip_set_affinity_parent(d, dest, force); 532 533 return -EINVAL; 534 } 535 536 static int __maybe_unused stm32_exti_h_suspend(void) 537 { 538 struct stm32_exti_chip_data *chip_data; 539 int i; 540 541 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 542 chip_data = &stm32_host_data->chips_data[i]; 543 raw_spin_lock(&chip_data->rlock); 544 stm32_chip_suspend(chip_data, chip_data->wake_active); 545 raw_spin_unlock(&chip_data->rlock); 546 } 547 548 return 0; 549 } 550 551 static void __maybe_unused stm32_exti_h_resume(void) 552 { 553 struct stm32_exti_chip_data *chip_data; 554 int i; 555 556 for (i = 0; i < stm32_host_data->drv_data->bank_nr; i++) { 557 chip_data = &stm32_host_data->chips_data[i]; 558 raw_spin_lock(&chip_data->rlock); 559 stm32_chip_resume(chip_data, chip_data->mask_cache); 560 raw_spin_unlock(&chip_data->rlock); 561 } 562 } 563 564 static struct syscore_ops stm32_exti_h_syscore_ops = { 565 #ifdef CONFIG_PM_SLEEP 566 .suspend = stm32_exti_h_suspend, 567 .resume = stm32_exti_h_resume, 568 #endif 569 }; 570 571 static void stm32_exti_h_syscore_init(struct stm32_exti_host_data *host_data) 572 { 573 stm32_host_data = host_data; 574 register_syscore_ops(&stm32_exti_h_syscore_ops); 575 } 576 577 static void stm32_exti_h_syscore_deinit(void) 578 { 579 unregister_syscore_ops(&stm32_exti_h_syscore_ops); 580 } 581 582 static int stm32_exti_h_retrigger(struct irq_data *d) 583 { 584 struct stm32_exti_chip_data *chip_data = irq_data_get_irq_chip_data(d); 585 const struct stm32_exti_bank *stm32_bank = chip_data->reg_bank; 586 void __iomem *base = chip_data->host_data->base; 587 u32 mask = BIT(d->hwirq % IRQS_PER_BANK); 588 589 writel_relaxed(mask, base + stm32_bank->swier_ofst); 590 591 return 0; 592 } 593 594 static struct irq_chip stm32_exti_h_chip = { 595 .name = "stm32-exti-h", 596 .irq_eoi = stm32_exti_h_eoi, 597 .irq_mask = stm32_exti_h_mask, 598 .irq_unmask = stm32_exti_h_unmask, 599 .irq_retrigger = stm32_exti_h_retrigger, 600 .irq_set_type = stm32_exti_h_set_type, 601 .irq_set_wake = stm32_exti_h_set_wake, 602 .flags = IRQCHIP_MASK_ON_SUSPEND, 603 .irq_set_affinity = IS_ENABLED(CONFIG_SMP) ? stm32_exti_h_set_affinity : NULL, 604 }; 605 606 static int stm32_exti_h_domain_alloc(struct irq_domain *dm, 607 unsigned int virq, 608 unsigned int nr_irqs, void *data) 609 { 610 struct stm32_exti_host_data *host_data = dm->host_data; 611 struct stm32_exti_chip_data *chip_data; 612 struct irq_fwspec *fwspec = data; 613 struct irq_fwspec p_fwspec; 614 irq_hw_number_t hwirq; 615 int p_irq, bank; 616 617 hwirq = fwspec->param[0]; 618 bank = hwirq / IRQS_PER_BANK; 619 chip_data = &host_data->chips_data[bank]; 620 621 irq_domain_set_hwirq_and_chip(dm, virq, hwirq, 622 &stm32_exti_h_chip, chip_data); 623 624 p_irq = stm32_exti_to_irq(host_data->drv_data, hwirq); 625 if (p_irq >= 0) { 626 p_fwspec.fwnode = dm->parent->fwnode; 627 p_fwspec.param_count = 3; 628 p_fwspec.param[0] = GIC_SPI; 629 p_fwspec.param[1] = p_irq; 630 p_fwspec.param[2] = IRQ_TYPE_LEVEL_HIGH; 631 632 return irq_domain_alloc_irqs_parent(dm, virq, 1, &p_fwspec); 633 } 634 635 return 0; 636 } 637 638 static struct 639 stm32_exti_host_data *stm32_exti_host_init(const struct stm32_exti_drv_data *dd, 640 struct device_node *node) 641 { 642 struct stm32_exti_host_data *host_data; 643 644 host_data = kzalloc(sizeof(*host_data), GFP_KERNEL); 645 if (!host_data) 646 return NULL; 647 648 host_data->drv_data = dd; 649 host_data->chips_data = kcalloc(dd->bank_nr, 650 sizeof(struct stm32_exti_chip_data), 651 GFP_KERNEL); 652 if (!host_data->chips_data) 653 goto free_host_data; 654 655 host_data->base = of_iomap(node, 0); 656 if (!host_data->base) { 657 pr_err("%pOF: Unable to map registers\n", node); 658 goto free_chips_data; 659 } 660 661 stm32_host_data = host_data; 662 663 return host_data; 664 665 free_chips_data: 666 kfree(host_data->chips_data); 667 free_host_data: 668 kfree(host_data); 669 670 return NULL; 671 } 672 673 static struct 674 stm32_exti_chip_data *stm32_exti_chip_init(struct stm32_exti_host_data *h_data, 675 u32 bank_idx, 676 struct device_node *node) 677 { 678 const struct stm32_exti_bank *stm32_bank; 679 struct stm32_exti_chip_data *chip_data; 680 void __iomem *base = h_data->base; 681 682 stm32_bank = h_data->drv_data->exti_banks[bank_idx]; 683 chip_data = &h_data->chips_data[bank_idx]; 684 chip_data->host_data = h_data; 685 chip_data->reg_bank = stm32_bank; 686 687 raw_spin_lock_init(&chip_data->rlock); 688 689 /* 690 * This IP has no reset, so after hot reboot we should 691 * clear registers to avoid residue 692 */ 693 writel_relaxed(0, base + stm32_bank->imr_ofst); 694 writel_relaxed(0, base + stm32_bank->emr_ofst); 695 696 pr_info("%pOF: bank%d\n", node, bank_idx); 697 698 return chip_data; 699 } 700 701 static int __init stm32_exti_init(const struct stm32_exti_drv_data *drv_data, 702 struct device_node *node) 703 { 704 struct stm32_exti_host_data *host_data; 705 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 706 int nr_irqs, ret, i; 707 struct irq_chip_generic *gc; 708 struct irq_domain *domain; 709 710 host_data = stm32_exti_host_init(drv_data, node); 711 if (!host_data) 712 return -ENOMEM; 713 714 domain = irq_domain_add_linear(node, drv_data->bank_nr * IRQS_PER_BANK, 715 &irq_exti_domain_ops, NULL); 716 if (!domain) { 717 pr_err("%pOFn: Could not register interrupt domain.\n", 718 node); 719 ret = -ENOMEM; 720 goto out_unmap; 721 } 722 723 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 724 handle_edge_irq, clr, 0, 0); 725 if (ret) { 726 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 727 node); 728 goto out_free_domain; 729 } 730 731 for (i = 0; i < drv_data->bank_nr; i++) { 732 const struct stm32_exti_bank *stm32_bank; 733 struct stm32_exti_chip_data *chip_data; 734 735 stm32_bank = drv_data->exti_banks[i]; 736 chip_data = stm32_exti_chip_init(host_data, i, node); 737 738 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 739 740 gc->reg_base = host_data->base; 741 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 742 gc->chip_types->chip.irq_ack = stm32_irq_ack; 743 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 744 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 745 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 746 gc->chip_types->chip.irq_set_wake = irq_gc_set_wake; 747 gc->suspend = stm32_irq_suspend; 748 gc->resume = stm32_irq_resume; 749 gc->wake_enabled = IRQ_MSK(IRQS_PER_BANK); 750 751 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 752 gc->private = (void *)chip_data; 753 } 754 755 nr_irqs = of_irq_count(node); 756 for (i = 0; i < nr_irqs; i++) { 757 unsigned int irq = irq_of_parse_and_map(node, i); 758 759 irq_set_handler_data(irq, domain); 760 irq_set_chained_handler(irq, stm32_irq_handler); 761 } 762 763 return 0; 764 765 out_free_domain: 766 irq_domain_remove(domain); 767 out_unmap: 768 iounmap(host_data->base); 769 kfree(host_data->chips_data); 770 kfree(host_data); 771 return ret; 772 } 773 774 static const struct irq_domain_ops stm32_exti_h_domain_ops = { 775 .alloc = stm32_exti_h_domain_alloc, 776 .free = irq_domain_free_irqs_common, 777 .xlate = irq_domain_xlate_twocell, 778 }; 779 780 static void stm32_exti_remove_irq(void *data) 781 { 782 struct irq_domain *domain = data; 783 784 irq_domain_remove(domain); 785 } 786 787 static int stm32_exti_remove(struct platform_device *pdev) 788 { 789 stm32_exti_h_syscore_deinit(); 790 return 0; 791 } 792 793 static int stm32_exti_probe(struct platform_device *pdev) 794 { 795 int ret, i; 796 struct device *dev = &pdev->dev; 797 struct device_node *np = dev->of_node; 798 struct irq_domain *parent_domain, *domain; 799 struct stm32_exti_host_data *host_data; 800 const struct stm32_exti_drv_data *drv_data; 801 struct resource *res; 802 803 host_data = devm_kzalloc(dev, sizeof(*host_data), GFP_KERNEL); 804 if (!host_data) 805 return -ENOMEM; 806 807 /* check for optional hwspinlock which may be not available yet */ 808 ret = of_hwspin_lock_get_id(np, 0); 809 if (ret == -EPROBE_DEFER) 810 /* hwspinlock framework not yet ready */ 811 return ret; 812 813 if (ret >= 0) { 814 host_data->hwlock = devm_hwspin_lock_request_specific(dev, ret); 815 if (!host_data->hwlock) { 816 dev_err(dev, "Failed to request hwspinlock\n"); 817 return -EINVAL; 818 } 819 } else if (ret != -ENOENT) { 820 /* note: ENOENT is a valid case (means 'no hwspinlock') */ 821 dev_err(dev, "Failed to get hwspinlock\n"); 822 return ret; 823 } 824 825 /* initialize host_data */ 826 drv_data = of_device_get_match_data(dev); 827 if (!drv_data) { 828 dev_err(dev, "no of match data\n"); 829 return -ENODEV; 830 } 831 host_data->drv_data = drv_data; 832 833 host_data->chips_data = devm_kcalloc(dev, drv_data->bank_nr, 834 sizeof(*host_data->chips_data), 835 GFP_KERNEL); 836 if (!host_data->chips_data) 837 return -ENOMEM; 838 839 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 840 host_data->base = devm_ioremap_resource(dev, res); 841 if (IS_ERR(host_data->base)) { 842 dev_err(dev, "Unable to map registers\n"); 843 return PTR_ERR(host_data->base); 844 } 845 846 for (i = 0; i < drv_data->bank_nr; i++) 847 stm32_exti_chip_init(host_data, i, np); 848 849 parent_domain = irq_find_host(of_irq_find_parent(np)); 850 if (!parent_domain) { 851 dev_err(dev, "GIC interrupt-parent not found\n"); 852 return -EINVAL; 853 } 854 855 domain = irq_domain_add_hierarchy(parent_domain, 0, 856 drv_data->bank_nr * IRQS_PER_BANK, 857 np, &stm32_exti_h_domain_ops, 858 host_data); 859 860 if (!domain) { 861 dev_err(dev, "Could not register exti domain\n"); 862 return -ENOMEM; 863 } 864 865 ret = devm_add_action_or_reset(dev, stm32_exti_remove_irq, domain); 866 if (ret) 867 return ret; 868 869 stm32_exti_h_syscore_init(host_data); 870 871 return 0; 872 } 873 874 /* platform driver only for MP1 */ 875 static const struct of_device_id stm32_exti_ids[] = { 876 { .compatible = "st,stm32mp1-exti", .data = &stm32mp1_drv_data}, 877 {}, 878 }; 879 MODULE_DEVICE_TABLE(of, stm32_exti_ids); 880 881 static struct platform_driver stm32_exti_driver = { 882 .probe = stm32_exti_probe, 883 .remove = stm32_exti_remove, 884 .driver = { 885 .name = "stm32_exti", 886 .of_match_table = stm32_exti_ids, 887 }, 888 }; 889 890 static int __init stm32_exti_arch_init(void) 891 { 892 return platform_driver_register(&stm32_exti_driver); 893 } 894 895 static void __exit stm32_exti_arch_exit(void) 896 { 897 return platform_driver_unregister(&stm32_exti_driver); 898 } 899 900 arch_initcall(stm32_exti_arch_init); 901 module_exit(stm32_exti_arch_exit); 902 903 /* no platform driver for F4 and H7 */ 904 static int __init stm32f4_exti_of_init(struct device_node *np, 905 struct device_node *parent) 906 { 907 return stm32_exti_init(&stm32f4xx_drv_data, np); 908 } 909 910 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 911 912 static int __init stm32h7_exti_of_init(struct device_node *np, 913 struct device_node *parent) 914 { 915 return stm32_exti_init(&stm32h7xx_drv_data, np); 916 } 917 918 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 919