1 /* 2 * Copyright (C) Maxime Coquelin 2015 3 * Author: Maxime Coquelin <mcoquelin.stm32@gmail.com> 4 * License terms: GNU General Public License (GPL), version 2 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/of_address.h> 15 #include <linux/of_irq.h> 16 17 #define IRQS_PER_BANK 32 18 19 struct stm32_exti_bank { 20 u32 imr_ofst; 21 u32 emr_ofst; 22 u32 rtsr_ofst; 23 u32 ftsr_ofst; 24 u32 swier_ofst; 25 u32 pr_ofst; 26 }; 27 28 static const struct stm32_exti_bank stm32f4xx_exti_b1 = { 29 .imr_ofst = 0x00, 30 .emr_ofst = 0x04, 31 .rtsr_ofst = 0x08, 32 .ftsr_ofst = 0x0C, 33 .swier_ofst = 0x10, 34 .pr_ofst = 0x14, 35 }; 36 37 static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = { 38 &stm32f4xx_exti_b1, 39 }; 40 41 static const struct stm32_exti_bank stm32h7xx_exti_b1 = { 42 .imr_ofst = 0x80, 43 .emr_ofst = 0x84, 44 .rtsr_ofst = 0x00, 45 .ftsr_ofst = 0x04, 46 .swier_ofst = 0x08, 47 .pr_ofst = 0x88, 48 }; 49 50 static const struct stm32_exti_bank stm32h7xx_exti_b2 = { 51 .imr_ofst = 0x90, 52 .emr_ofst = 0x94, 53 .rtsr_ofst = 0x20, 54 .ftsr_ofst = 0x24, 55 .swier_ofst = 0x28, 56 .pr_ofst = 0x98, 57 }; 58 59 static const struct stm32_exti_bank stm32h7xx_exti_b3 = { 60 .imr_ofst = 0xA0, 61 .emr_ofst = 0xA4, 62 .rtsr_ofst = 0x40, 63 .ftsr_ofst = 0x44, 64 .swier_ofst = 0x48, 65 .pr_ofst = 0xA8, 66 }; 67 68 static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = { 69 &stm32h7xx_exti_b1, 70 &stm32h7xx_exti_b2, 71 &stm32h7xx_exti_b3, 72 }; 73 74 static unsigned long stm32_exti_pending(struct irq_chip_generic *gc) 75 { 76 const struct stm32_exti_bank *stm32_bank = gc->private; 77 78 return irq_reg_readl(gc, stm32_bank->pr_ofst); 79 } 80 81 static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask) 82 { 83 const struct stm32_exti_bank *stm32_bank = gc->private; 84 85 irq_reg_writel(gc, mask, stm32_bank->pr_ofst); 86 } 87 88 static void stm32_irq_handler(struct irq_desc *desc) 89 { 90 struct irq_domain *domain = irq_desc_get_handler_data(desc); 91 struct irq_chip *chip = irq_desc_get_chip(desc); 92 unsigned int virq, nbanks = domain->gc->num_chips; 93 struct irq_chip_generic *gc; 94 const struct stm32_exti_bank *stm32_bank; 95 unsigned long pending; 96 int n, i, irq_base = 0; 97 98 chained_irq_enter(chip, desc); 99 100 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) { 101 gc = irq_get_domain_generic_chip(domain, irq_base); 102 stm32_bank = gc->private; 103 104 while ((pending = stm32_exti_pending(gc))) { 105 for_each_set_bit(n, &pending, IRQS_PER_BANK) { 106 virq = irq_find_mapping(domain, irq_base + n); 107 generic_handle_irq(virq); 108 stm32_exti_irq_ack(gc, BIT(n)); 109 } 110 } 111 } 112 113 chained_irq_exit(chip, desc); 114 } 115 116 static int stm32_irq_set_type(struct irq_data *data, unsigned int type) 117 { 118 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 119 const struct stm32_exti_bank *stm32_bank = gc->private; 120 int pin = data->hwirq % IRQS_PER_BANK; 121 u32 rtsr, ftsr; 122 123 irq_gc_lock(gc); 124 125 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst); 126 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst); 127 128 switch (type) { 129 case IRQ_TYPE_EDGE_RISING: 130 rtsr |= BIT(pin); 131 ftsr &= ~BIT(pin); 132 break; 133 case IRQ_TYPE_EDGE_FALLING: 134 rtsr &= ~BIT(pin); 135 ftsr |= BIT(pin); 136 break; 137 case IRQ_TYPE_EDGE_BOTH: 138 rtsr |= BIT(pin); 139 ftsr |= BIT(pin); 140 break; 141 default: 142 irq_gc_unlock(gc); 143 return -EINVAL; 144 } 145 146 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst); 147 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst); 148 149 irq_gc_unlock(gc); 150 151 return 0; 152 } 153 154 static int stm32_irq_set_wake(struct irq_data *data, unsigned int on) 155 { 156 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 157 const struct stm32_exti_bank *stm32_bank = gc->private; 158 int pin = data->hwirq % IRQS_PER_BANK; 159 u32 imr; 160 161 irq_gc_lock(gc); 162 163 imr = irq_reg_readl(gc, stm32_bank->imr_ofst); 164 if (on) 165 imr |= BIT(pin); 166 else 167 imr &= ~BIT(pin); 168 irq_reg_writel(gc, imr, stm32_bank->imr_ofst); 169 170 irq_gc_unlock(gc); 171 172 return 0; 173 } 174 175 static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq, 176 unsigned int nr_irqs, void *data) 177 { 178 struct irq_chip_generic *gc; 179 struct irq_fwspec *fwspec = data; 180 irq_hw_number_t hwirq; 181 182 hwirq = fwspec->param[0]; 183 gc = irq_get_domain_generic_chip(d, hwirq); 184 185 irq_map_generic_chip(d, virq, hwirq); 186 irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc, 187 handle_simple_irq, NULL, NULL); 188 189 return 0; 190 } 191 192 static void stm32_exti_free(struct irq_domain *d, unsigned int virq, 193 unsigned int nr_irqs) 194 { 195 struct irq_data *data = irq_domain_get_irq_data(d, virq); 196 197 irq_domain_reset_irq_data(data); 198 } 199 200 struct irq_domain_ops irq_exti_domain_ops = { 201 .map = irq_map_generic_chip, 202 .xlate = irq_domain_xlate_onetwocell, 203 .alloc = stm32_exti_alloc, 204 .free = stm32_exti_free, 205 }; 206 207 static int 208 __init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks, 209 int bank_nr, struct device_node *node) 210 { 211 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 212 int nr_irqs, nr_exti, ret, i; 213 struct irq_chip_generic *gc; 214 struct irq_domain *domain; 215 void *base; 216 217 base = of_iomap(node, 0); 218 if (!base) { 219 pr_err("%pOF: Unable to map registers\n", node); 220 return -ENOMEM; 221 } 222 223 domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK, 224 &irq_exti_domain_ops, NULL); 225 if (!domain) { 226 pr_err("%s: Could not register interrupt domain.\n", 227 node->name); 228 ret = -ENOMEM; 229 goto out_unmap; 230 } 231 232 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti", 233 handle_edge_irq, clr, 0, 0); 234 if (ret) { 235 pr_err("%pOF: Could not allocate generic interrupt chip.\n", 236 node); 237 goto out_free_domain; 238 } 239 240 for (i = 0; i < bank_nr; i++) { 241 const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i]; 242 u32 irqs_mask; 243 244 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK); 245 246 gc->reg_base = base; 247 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH; 248 gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit; 249 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit; 250 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit; 251 gc->chip_types->chip.irq_set_type = stm32_irq_set_type; 252 gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake; 253 gc->chip_types->regs.ack = stm32_bank->pr_ofst; 254 gc->chip_types->regs.mask = stm32_bank->imr_ofst; 255 gc->private = (void *)stm32_bank; 256 257 /* Determine number of irqs supported */ 258 writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst); 259 irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst); 260 nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst)); 261 262 /* 263 * This IP has no reset, so after hot reboot we should 264 * clear registers to avoid residue 265 */ 266 writel_relaxed(0, base + stm32_bank->imr_ofst); 267 writel_relaxed(0, base + stm32_bank->emr_ofst); 268 writel_relaxed(0, base + stm32_bank->rtsr_ofst); 269 writel_relaxed(0, base + stm32_bank->ftsr_ofst); 270 writel_relaxed(~0UL, base + stm32_bank->pr_ofst); 271 272 pr_info("%s: bank%d, External IRQs available:%#x\n", 273 node->full_name, i, irqs_mask); 274 } 275 276 nr_irqs = of_irq_count(node); 277 for (i = 0; i < nr_irqs; i++) { 278 unsigned int irq = irq_of_parse_and_map(node, i); 279 280 irq_set_handler_data(irq, domain); 281 irq_set_chained_handler(irq, stm32_irq_handler); 282 } 283 284 return 0; 285 286 out_free_domain: 287 irq_domain_remove(domain); 288 out_unmap: 289 iounmap(base); 290 return ret; 291 } 292 293 static int __init stm32f4_exti_of_init(struct device_node *np, 294 struct device_node *parent) 295 { 296 return stm32_exti_init(stm32f4xx_exti_banks, 297 ARRAY_SIZE(stm32f4xx_exti_banks), np); 298 } 299 300 IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init); 301 302 static int __init stm32h7_exti_of_init(struct device_node *np, 303 struct device_node *parent) 304 { 305 return stm32_exti_init(stm32h7xx_exti_banks, 306 ARRAY_SIZE(stm32h7xx_exti_banks), np); 307 } 308 309 IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init); 310