1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017 SiFive 4 * Copyright (C) 2018 Christoph Hellwig 5 */ 6 #define pr_fmt(fmt) "plic: " fmt 7 #include <linux/cpu.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/spinlock.h> 20 #include <asm/smp.h> 21 22 /* 23 * This driver implements a version of the RISC-V PLIC with the actual layout 24 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual: 25 * 26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf 27 * 28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is 29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged 30 * Spec. 31 */ 32 33 #define MAX_DEVICES 1024 34 #define MAX_CONTEXTS 15872 35 36 /* 37 * Each interrupt source has a priority register associated with it. 38 * We always hardwire it to one in Linux. 39 */ 40 #define PRIORITY_BASE 0 41 #define PRIORITY_PER_ID 4 42 43 /* 44 * Each hart context has a vector of interrupt enable bits associated with it. 45 * There's one bit for each interrupt source. 46 */ 47 #define CONTEXT_ENABLE_BASE 0x2000 48 #define CONTEXT_ENABLE_SIZE 0x80 49 50 /* 51 * Each hart context has a set of control registers associated with it. Right 52 * now there's only two: a source priority threshold over which the hart will 53 * take an interrupt, and a register to claim interrupts. 54 */ 55 #define CONTEXT_BASE 0x200000 56 #define CONTEXT_SIZE 0x1000 57 #define CONTEXT_THRESHOLD 0x00 58 #define CONTEXT_CLAIM 0x04 59 60 #define PLIC_DISABLE_THRESHOLD 0x7 61 #define PLIC_ENABLE_THRESHOLD 0 62 63 #define PLIC_QUIRK_EDGE_INTERRUPT 0 64 65 struct plic_priv { 66 struct cpumask lmask; 67 struct irq_domain *irqdomain; 68 void __iomem *regs; 69 unsigned long plic_quirks; 70 }; 71 72 struct plic_handler { 73 bool present; 74 void __iomem *hart_base; 75 /* 76 * Protect mask operations on the registers given that we can't 77 * assume atomic memory operations work on them. 78 */ 79 raw_spinlock_t enable_lock; 80 void __iomem *enable_base; 81 struct plic_priv *priv; 82 }; 83 static int plic_parent_irq __ro_after_init; 84 static bool plic_cpuhp_setup_done __ro_after_init; 85 static DEFINE_PER_CPU(struct plic_handler, plic_handlers); 86 87 static int plic_irq_set_type(struct irq_data *d, unsigned int type); 88 89 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) 90 { 91 u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32); 92 u32 hwirq_mask = 1 << (hwirq % 32); 93 94 if (enable) 95 writel(readl(reg) | hwirq_mask, reg); 96 else 97 writel(readl(reg) & ~hwirq_mask, reg); 98 } 99 100 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) 101 { 102 raw_spin_lock(&handler->enable_lock); 103 __plic_toggle(handler->enable_base, hwirq, enable); 104 raw_spin_unlock(&handler->enable_lock); 105 } 106 107 static inline void plic_irq_toggle(const struct cpumask *mask, 108 struct irq_data *d, int enable) 109 { 110 int cpu; 111 112 for_each_cpu(cpu, mask) { 113 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 114 115 plic_toggle(handler, d->hwirq, enable); 116 } 117 } 118 119 static void plic_irq_enable(struct irq_data *d) 120 { 121 plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1); 122 } 123 124 static void plic_irq_disable(struct irq_data *d) 125 { 126 plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0); 127 } 128 129 static void plic_irq_unmask(struct irq_data *d) 130 { 131 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 132 133 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 134 } 135 136 static void plic_irq_mask(struct irq_data *d) 137 { 138 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 139 140 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 141 } 142 143 static void plic_irq_eoi(struct irq_data *d) 144 { 145 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 146 147 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); 148 } 149 150 #ifdef CONFIG_SMP 151 static int plic_set_affinity(struct irq_data *d, 152 const struct cpumask *mask_val, bool force) 153 { 154 unsigned int cpu; 155 struct cpumask amask; 156 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 157 158 cpumask_and(&amask, &priv->lmask, mask_val); 159 160 if (force) 161 cpu = cpumask_first(&amask); 162 else 163 cpu = cpumask_any_and(&amask, cpu_online_mask); 164 165 if (cpu >= nr_cpu_ids) 166 return -EINVAL; 167 168 plic_irq_disable(d); 169 170 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 171 172 if (!irqd_irq_disabled(d)) 173 plic_irq_enable(d); 174 175 return IRQ_SET_MASK_OK_DONE; 176 } 177 #endif 178 179 static struct irq_chip plic_edge_chip = { 180 .name = "SiFive PLIC", 181 .irq_enable = plic_irq_enable, 182 .irq_disable = plic_irq_disable, 183 .irq_ack = plic_irq_eoi, 184 .irq_mask = plic_irq_mask, 185 .irq_unmask = plic_irq_unmask, 186 #ifdef CONFIG_SMP 187 .irq_set_affinity = plic_set_affinity, 188 #endif 189 .irq_set_type = plic_irq_set_type, 190 .flags = IRQCHIP_SKIP_SET_WAKE | 191 IRQCHIP_AFFINITY_PRE_STARTUP, 192 }; 193 194 static struct irq_chip plic_chip = { 195 .name = "SiFive PLIC", 196 .irq_enable = plic_irq_enable, 197 .irq_disable = plic_irq_disable, 198 .irq_mask = plic_irq_mask, 199 .irq_unmask = plic_irq_unmask, 200 .irq_eoi = plic_irq_eoi, 201 #ifdef CONFIG_SMP 202 .irq_set_affinity = plic_set_affinity, 203 #endif 204 .irq_set_type = plic_irq_set_type, 205 .flags = IRQCHIP_SKIP_SET_WAKE | 206 IRQCHIP_AFFINITY_PRE_STARTUP, 207 }; 208 209 static int plic_irq_set_type(struct irq_data *d, unsigned int type) 210 { 211 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 212 213 if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) 214 return IRQ_SET_MASK_OK_NOCOPY; 215 216 switch (type) { 217 case IRQ_TYPE_EDGE_RISING: 218 irq_set_chip_handler_name_locked(d, &plic_edge_chip, 219 handle_edge_irq, NULL); 220 break; 221 case IRQ_TYPE_LEVEL_HIGH: 222 irq_set_chip_handler_name_locked(d, &plic_chip, 223 handle_fasteoi_irq, NULL); 224 break; 225 default: 226 return -EINVAL; 227 } 228 229 return IRQ_SET_MASK_OK; 230 } 231 232 static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, 233 irq_hw_number_t hwirq) 234 { 235 struct plic_priv *priv = d->host_data; 236 237 irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, 238 handle_fasteoi_irq, NULL, NULL); 239 irq_set_noprobe(irq); 240 irq_set_affinity(irq, &priv->lmask); 241 return 0; 242 } 243 244 static int plic_irq_domain_translate(struct irq_domain *d, 245 struct irq_fwspec *fwspec, 246 unsigned long *hwirq, 247 unsigned int *type) 248 { 249 struct plic_priv *priv = d->host_data; 250 251 if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) 252 return irq_domain_translate_twocell(d, fwspec, hwirq, type); 253 254 return irq_domain_translate_onecell(d, fwspec, hwirq, type); 255 } 256 257 static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 258 unsigned int nr_irqs, void *arg) 259 { 260 int i, ret; 261 irq_hw_number_t hwirq; 262 unsigned int type; 263 struct irq_fwspec *fwspec = arg; 264 265 ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type); 266 if (ret) 267 return ret; 268 269 for (i = 0; i < nr_irqs; i++) { 270 ret = plic_irqdomain_map(domain, virq + i, hwirq + i); 271 if (ret) 272 return ret; 273 } 274 275 return 0; 276 } 277 278 static const struct irq_domain_ops plic_irqdomain_ops = { 279 .translate = plic_irq_domain_translate, 280 .alloc = plic_irq_domain_alloc, 281 .free = irq_domain_free_irqs_top, 282 }; 283 284 /* 285 * Handling an interrupt is a two-step process: first you claim the interrupt 286 * by reading the claim register, then you complete the interrupt by writing 287 * that source ID back to the same claim register. This automatically enables 288 * and disables the interrupt, so there's nothing else to do. 289 */ 290 static void plic_handle_irq(struct irq_desc *desc) 291 { 292 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 293 struct irq_chip *chip = irq_desc_get_chip(desc); 294 void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; 295 irq_hw_number_t hwirq; 296 297 WARN_ON_ONCE(!handler->present); 298 299 chained_irq_enter(chip, desc); 300 301 while ((hwirq = readl(claim))) { 302 int err = generic_handle_domain_irq(handler->priv->irqdomain, 303 hwirq); 304 if (unlikely(err)) 305 pr_warn_ratelimited("can't find mapping for hwirq %lu\n", 306 hwirq); 307 } 308 309 chained_irq_exit(chip, desc); 310 } 311 312 static void plic_set_threshold(struct plic_handler *handler, u32 threshold) 313 { 314 /* priority must be > threshold to trigger an interrupt */ 315 writel(threshold, handler->hart_base + CONTEXT_THRESHOLD); 316 } 317 318 static int plic_dying_cpu(unsigned int cpu) 319 { 320 if (plic_parent_irq) 321 disable_percpu_irq(plic_parent_irq); 322 323 return 0; 324 } 325 326 static int plic_starting_cpu(unsigned int cpu) 327 { 328 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 329 330 if (plic_parent_irq) 331 enable_percpu_irq(plic_parent_irq, 332 irq_get_trigger_type(plic_parent_irq)); 333 else 334 pr_warn("cpu%d: parent irq not available\n", cpu); 335 plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD); 336 337 return 0; 338 } 339 340 static int __init __plic_init(struct device_node *node, 341 struct device_node *parent, 342 unsigned long plic_quirks) 343 { 344 int error = 0, nr_contexts, nr_handlers = 0, i; 345 u32 nr_irqs; 346 struct plic_priv *priv; 347 struct plic_handler *handler; 348 349 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 350 if (!priv) 351 return -ENOMEM; 352 353 priv->plic_quirks = plic_quirks; 354 355 priv->regs = of_iomap(node, 0); 356 if (WARN_ON(!priv->regs)) { 357 error = -EIO; 358 goto out_free_priv; 359 } 360 361 error = -EINVAL; 362 of_property_read_u32(node, "riscv,ndev", &nr_irqs); 363 if (WARN_ON(!nr_irqs)) 364 goto out_iounmap; 365 366 nr_contexts = of_irq_count(node); 367 if (WARN_ON(!nr_contexts)) 368 goto out_iounmap; 369 370 error = -ENOMEM; 371 priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1, 372 &plic_irqdomain_ops, priv); 373 if (WARN_ON(!priv->irqdomain)) 374 goto out_iounmap; 375 376 for (i = 0; i < nr_contexts; i++) { 377 struct of_phandle_args parent; 378 irq_hw_number_t hwirq; 379 int cpu; 380 unsigned long hartid; 381 382 if (of_irq_parse_one(node, i, &parent)) { 383 pr_err("failed to parse parent for context %d.\n", i); 384 continue; 385 } 386 387 /* 388 * Skip contexts other than external interrupts for our 389 * privilege level. 390 */ 391 if (parent.args[0] != RV_IRQ_EXT) { 392 /* Disable S-mode enable bits if running in M-mode. */ 393 if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { 394 void __iomem *enable_base = priv->regs + 395 CONTEXT_ENABLE_BASE + 396 i * CONTEXT_ENABLE_SIZE; 397 398 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) 399 __plic_toggle(enable_base, hwirq, 0); 400 } 401 continue; 402 } 403 404 error = riscv_of_parent_hartid(parent.np, &hartid); 405 if (error < 0) { 406 pr_warn("failed to parse hart ID for context %d.\n", i); 407 continue; 408 } 409 410 cpu = riscv_hartid_to_cpuid(hartid); 411 if (cpu < 0) { 412 pr_warn("Invalid cpuid for context %d\n", i); 413 continue; 414 } 415 416 /* Find parent domain and register chained handler */ 417 if (!plic_parent_irq && irq_find_host(parent.np)) { 418 plic_parent_irq = irq_of_parse_and_map(node, i); 419 if (plic_parent_irq) 420 irq_set_chained_handler(plic_parent_irq, 421 plic_handle_irq); 422 } 423 424 /* 425 * When running in M-mode we need to ignore the S-mode handler. 426 * Here we assume it always comes later, but that might be a 427 * little fragile. 428 */ 429 handler = per_cpu_ptr(&plic_handlers, cpu); 430 if (handler->present) { 431 pr_warn("handler already present for context %d.\n", i); 432 plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); 433 goto done; 434 } 435 436 cpumask_set_cpu(cpu, &priv->lmask); 437 handler->present = true; 438 handler->hart_base = priv->regs + CONTEXT_BASE + 439 i * CONTEXT_SIZE; 440 raw_spin_lock_init(&handler->enable_lock); 441 handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE + 442 i * CONTEXT_ENABLE_SIZE; 443 handler->priv = priv; 444 done: 445 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { 446 plic_toggle(handler, hwirq, 0); 447 writel(1, priv->regs + PRIORITY_BASE + 448 hwirq * PRIORITY_PER_ID); 449 } 450 nr_handlers++; 451 } 452 453 /* 454 * We can have multiple PLIC instances so setup cpuhp state only 455 * when context handler for current/boot CPU is present. 456 */ 457 handler = this_cpu_ptr(&plic_handlers); 458 if (handler->present && !plic_cpuhp_setup_done) { 459 cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, 460 "irqchip/sifive/plic:starting", 461 plic_starting_cpu, plic_dying_cpu); 462 plic_cpuhp_setup_done = true; 463 } 464 465 pr_info("%pOFP: mapped %d interrupts with %d handlers for" 466 " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); 467 return 0; 468 469 out_iounmap: 470 iounmap(priv->regs); 471 out_free_priv: 472 kfree(priv); 473 return error; 474 } 475 476 static int __init plic_init(struct device_node *node, 477 struct device_node *parent) 478 { 479 return __plic_init(node, parent, 0); 480 } 481 482 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); 483 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ 484 485 static int __init plic_edge_init(struct device_node *node, 486 struct device_node *parent) 487 { 488 return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); 489 } 490 491 IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init); 492 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); 493