1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017 SiFive 4 * Copyright (C) 2018 Christoph Hellwig 5 */ 6 #define pr_fmt(fmt) "plic: " fmt 7 #include <linux/cpu.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/spinlock.h> 20 #include <linux/syscore_ops.h> 21 #include <asm/smp.h> 22 23 /* 24 * This driver implements a version of the RISC-V PLIC with the actual layout 25 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual: 26 * 27 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf 28 * 29 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is 30 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged 31 * Spec. 32 */ 33 34 #define MAX_DEVICES 1024 35 #define MAX_CONTEXTS 15872 36 37 /* 38 * Each interrupt source has a priority register associated with it. 39 * We always hardwire it to one in Linux. 40 */ 41 #define PRIORITY_BASE 0 42 #define PRIORITY_PER_ID 4 43 44 /* 45 * Each hart context has a vector of interrupt enable bits associated with it. 46 * There's one bit for each interrupt source. 47 */ 48 #define CONTEXT_ENABLE_BASE 0x2000 49 #define CONTEXT_ENABLE_SIZE 0x80 50 51 /* 52 * Each hart context has a set of control registers associated with it. Right 53 * now there's only two: a source priority threshold over which the hart will 54 * take an interrupt, and a register to claim interrupts. 55 */ 56 #define CONTEXT_BASE 0x200000 57 #define CONTEXT_SIZE 0x1000 58 #define CONTEXT_THRESHOLD 0x00 59 #define CONTEXT_CLAIM 0x04 60 61 #define PLIC_DISABLE_THRESHOLD 0x7 62 #define PLIC_ENABLE_THRESHOLD 0 63 64 #define PLIC_QUIRK_EDGE_INTERRUPT 0 65 66 struct plic_priv { 67 struct cpumask lmask; 68 struct irq_domain *irqdomain; 69 void __iomem *regs; 70 unsigned long plic_quirks; 71 unsigned int nr_irqs; 72 unsigned long *prio_save; 73 }; 74 75 struct plic_handler { 76 bool present; 77 void __iomem *hart_base; 78 /* 79 * Protect mask operations on the registers given that we can't 80 * assume atomic memory operations work on them. 81 */ 82 raw_spinlock_t enable_lock; 83 void __iomem *enable_base; 84 u32 *enable_save; 85 struct plic_priv *priv; 86 }; 87 static int plic_parent_irq __ro_after_init; 88 static bool plic_cpuhp_setup_done __ro_after_init; 89 static DEFINE_PER_CPU(struct plic_handler, plic_handlers); 90 91 static int plic_irq_set_type(struct irq_data *d, unsigned int type); 92 93 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) 94 { 95 u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32); 96 u32 hwirq_mask = 1 << (hwirq % 32); 97 98 if (enable) 99 writel(readl(reg) | hwirq_mask, reg); 100 else 101 writel(readl(reg) & ~hwirq_mask, reg); 102 } 103 104 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) 105 { 106 raw_spin_lock(&handler->enable_lock); 107 __plic_toggle(handler->enable_base, hwirq, enable); 108 raw_spin_unlock(&handler->enable_lock); 109 } 110 111 static inline void plic_irq_toggle(const struct cpumask *mask, 112 struct irq_data *d, int enable) 113 { 114 int cpu; 115 116 for_each_cpu(cpu, mask) { 117 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 118 119 plic_toggle(handler, d->hwirq, enable); 120 } 121 } 122 123 static void plic_irq_unmask(struct irq_data *d) 124 { 125 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 126 127 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 128 } 129 130 static void plic_irq_mask(struct irq_data *d) 131 { 132 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 133 134 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 135 } 136 137 static void plic_irq_enable(struct irq_data *d) 138 { 139 plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1); 140 plic_irq_unmask(d); 141 } 142 143 static void plic_irq_disable(struct irq_data *d) 144 { 145 plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0); 146 } 147 148 static void plic_irq_eoi(struct irq_data *d) 149 { 150 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 151 152 if (unlikely(irqd_irq_disabled(d))) { 153 plic_toggle(handler, d->hwirq, 1); 154 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); 155 plic_toggle(handler, d->hwirq, 0); 156 } else { 157 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); 158 } 159 } 160 161 #ifdef CONFIG_SMP 162 static int plic_set_affinity(struct irq_data *d, 163 const struct cpumask *mask_val, bool force) 164 { 165 unsigned int cpu; 166 struct cpumask amask; 167 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 168 169 cpumask_and(&amask, &priv->lmask, mask_val); 170 171 if (force) 172 cpu = cpumask_first(&amask); 173 else 174 cpu = cpumask_any_and(&amask, cpu_online_mask); 175 176 if (cpu >= nr_cpu_ids) 177 return -EINVAL; 178 179 plic_irq_disable(d); 180 181 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 182 183 if (!irqd_irq_disabled(d)) 184 plic_irq_enable(d); 185 186 return IRQ_SET_MASK_OK_DONE; 187 } 188 #endif 189 190 static struct irq_chip plic_edge_chip = { 191 .name = "SiFive PLIC", 192 .irq_enable = plic_irq_enable, 193 .irq_disable = plic_irq_disable, 194 .irq_ack = plic_irq_eoi, 195 .irq_mask = plic_irq_mask, 196 .irq_unmask = plic_irq_unmask, 197 #ifdef CONFIG_SMP 198 .irq_set_affinity = plic_set_affinity, 199 #endif 200 .irq_set_type = plic_irq_set_type, 201 .flags = IRQCHIP_SKIP_SET_WAKE | 202 IRQCHIP_AFFINITY_PRE_STARTUP, 203 }; 204 205 static struct irq_chip plic_chip = { 206 .name = "SiFive PLIC", 207 .irq_enable = plic_irq_enable, 208 .irq_disable = plic_irq_disable, 209 .irq_mask = plic_irq_mask, 210 .irq_unmask = plic_irq_unmask, 211 .irq_eoi = plic_irq_eoi, 212 #ifdef CONFIG_SMP 213 .irq_set_affinity = plic_set_affinity, 214 #endif 215 .irq_set_type = plic_irq_set_type, 216 .flags = IRQCHIP_SKIP_SET_WAKE | 217 IRQCHIP_AFFINITY_PRE_STARTUP, 218 }; 219 220 static int plic_irq_set_type(struct irq_data *d, unsigned int type) 221 { 222 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 223 224 if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) 225 return IRQ_SET_MASK_OK_NOCOPY; 226 227 switch (type) { 228 case IRQ_TYPE_EDGE_RISING: 229 irq_set_chip_handler_name_locked(d, &plic_edge_chip, 230 handle_edge_irq, NULL); 231 break; 232 case IRQ_TYPE_LEVEL_HIGH: 233 irq_set_chip_handler_name_locked(d, &plic_chip, 234 handle_fasteoi_irq, NULL); 235 break; 236 default: 237 return -EINVAL; 238 } 239 240 return IRQ_SET_MASK_OK; 241 } 242 243 static int plic_irq_suspend(void) 244 { 245 unsigned int i, cpu; 246 u32 __iomem *reg; 247 struct plic_priv *priv; 248 249 priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; 250 251 for (i = 0; i < priv->nr_irqs; i++) 252 if (readl(priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID)) 253 __set_bit(i, priv->prio_save); 254 else 255 __clear_bit(i, priv->prio_save); 256 257 for_each_cpu(cpu, cpu_present_mask) { 258 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 259 260 if (!handler->present) 261 continue; 262 263 raw_spin_lock(&handler->enable_lock); 264 for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { 265 reg = handler->enable_base + i * sizeof(u32); 266 handler->enable_save[i] = readl(reg); 267 } 268 raw_spin_unlock(&handler->enable_lock); 269 } 270 271 return 0; 272 } 273 274 static void plic_irq_resume(void) 275 { 276 unsigned int i, index, cpu; 277 u32 __iomem *reg; 278 struct plic_priv *priv; 279 280 priv = per_cpu_ptr(&plic_handlers, smp_processor_id())->priv; 281 282 for (i = 0; i < priv->nr_irqs; i++) { 283 index = BIT_WORD(i); 284 writel((priv->prio_save[index] & BIT_MASK(i)) ? 1 : 0, 285 priv->regs + PRIORITY_BASE + i * PRIORITY_PER_ID); 286 } 287 288 for_each_cpu(cpu, cpu_present_mask) { 289 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 290 291 if (!handler->present) 292 continue; 293 294 raw_spin_lock(&handler->enable_lock); 295 for (i = 0; i < DIV_ROUND_UP(priv->nr_irqs, 32); i++) { 296 reg = handler->enable_base + i * sizeof(u32); 297 writel(handler->enable_save[i], reg); 298 } 299 raw_spin_unlock(&handler->enable_lock); 300 } 301 } 302 303 static struct syscore_ops plic_irq_syscore_ops = { 304 .suspend = plic_irq_suspend, 305 .resume = plic_irq_resume, 306 }; 307 308 static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, 309 irq_hw_number_t hwirq) 310 { 311 struct plic_priv *priv = d->host_data; 312 313 irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, 314 handle_fasteoi_irq, NULL, NULL); 315 irq_set_noprobe(irq); 316 irq_set_affinity(irq, &priv->lmask); 317 return 0; 318 } 319 320 static int plic_irq_domain_translate(struct irq_domain *d, 321 struct irq_fwspec *fwspec, 322 unsigned long *hwirq, 323 unsigned int *type) 324 { 325 struct plic_priv *priv = d->host_data; 326 327 if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) 328 return irq_domain_translate_twocell(d, fwspec, hwirq, type); 329 330 return irq_domain_translate_onecell(d, fwspec, hwirq, type); 331 } 332 333 static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 334 unsigned int nr_irqs, void *arg) 335 { 336 int i, ret; 337 irq_hw_number_t hwirq; 338 unsigned int type; 339 struct irq_fwspec *fwspec = arg; 340 341 ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type); 342 if (ret) 343 return ret; 344 345 for (i = 0; i < nr_irqs; i++) { 346 ret = plic_irqdomain_map(domain, virq + i, hwirq + i); 347 if (ret) 348 return ret; 349 } 350 351 return 0; 352 } 353 354 static const struct irq_domain_ops plic_irqdomain_ops = { 355 .translate = plic_irq_domain_translate, 356 .alloc = plic_irq_domain_alloc, 357 .free = irq_domain_free_irqs_top, 358 }; 359 360 /* 361 * Handling an interrupt is a two-step process: first you claim the interrupt 362 * by reading the claim register, then you complete the interrupt by writing 363 * that source ID back to the same claim register. This automatically enables 364 * and disables the interrupt, so there's nothing else to do. 365 */ 366 static void plic_handle_irq(struct irq_desc *desc) 367 { 368 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 369 struct irq_chip *chip = irq_desc_get_chip(desc); 370 void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; 371 irq_hw_number_t hwirq; 372 373 WARN_ON_ONCE(!handler->present); 374 375 chained_irq_enter(chip, desc); 376 377 while ((hwirq = readl(claim))) { 378 int err = generic_handle_domain_irq(handler->priv->irqdomain, 379 hwirq); 380 if (unlikely(err)) 381 pr_warn_ratelimited("can't find mapping for hwirq %lu\n", 382 hwirq); 383 } 384 385 chained_irq_exit(chip, desc); 386 } 387 388 static void plic_set_threshold(struct plic_handler *handler, u32 threshold) 389 { 390 /* priority must be > threshold to trigger an interrupt */ 391 writel(threshold, handler->hart_base + CONTEXT_THRESHOLD); 392 } 393 394 static int plic_dying_cpu(unsigned int cpu) 395 { 396 if (plic_parent_irq) 397 disable_percpu_irq(plic_parent_irq); 398 399 return 0; 400 } 401 402 static int plic_starting_cpu(unsigned int cpu) 403 { 404 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 405 406 if (plic_parent_irq) 407 enable_percpu_irq(plic_parent_irq, 408 irq_get_trigger_type(plic_parent_irq)); 409 else 410 pr_warn("cpu%d: parent irq not available\n", cpu); 411 plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD); 412 413 return 0; 414 } 415 416 static int __init __plic_init(struct device_node *node, 417 struct device_node *parent, 418 unsigned long plic_quirks) 419 { 420 int error = 0, nr_contexts, nr_handlers = 0, i; 421 u32 nr_irqs; 422 struct plic_priv *priv; 423 struct plic_handler *handler; 424 unsigned int cpu; 425 426 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 427 if (!priv) 428 return -ENOMEM; 429 430 priv->plic_quirks = plic_quirks; 431 432 priv->regs = of_iomap(node, 0); 433 if (WARN_ON(!priv->regs)) { 434 error = -EIO; 435 goto out_free_priv; 436 } 437 438 error = -EINVAL; 439 of_property_read_u32(node, "riscv,ndev", &nr_irqs); 440 if (WARN_ON(!nr_irqs)) 441 goto out_iounmap; 442 443 priv->nr_irqs = nr_irqs; 444 445 priv->prio_save = bitmap_alloc(nr_irqs, GFP_KERNEL); 446 if (!priv->prio_save) 447 goto out_free_priority_reg; 448 449 nr_contexts = of_irq_count(node); 450 if (WARN_ON(!nr_contexts)) 451 goto out_free_priority_reg; 452 453 error = -ENOMEM; 454 priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1, 455 &plic_irqdomain_ops, priv); 456 if (WARN_ON(!priv->irqdomain)) 457 goto out_free_priority_reg; 458 459 for (i = 0; i < nr_contexts; i++) { 460 struct of_phandle_args parent; 461 irq_hw_number_t hwirq; 462 int cpu; 463 unsigned long hartid; 464 465 if (of_irq_parse_one(node, i, &parent)) { 466 pr_err("failed to parse parent for context %d.\n", i); 467 continue; 468 } 469 470 /* 471 * Skip contexts other than external interrupts for our 472 * privilege level. 473 */ 474 if (parent.args[0] != RV_IRQ_EXT) { 475 /* Disable S-mode enable bits if running in M-mode. */ 476 if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { 477 void __iomem *enable_base = priv->regs + 478 CONTEXT_ENABLE_BASE + 479 i * CONTEXT_ENABLE_SIZE; 480 481 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) 482 __plic_toggle(enable_base, hwirq, 0); 483 } 484 continue; 485 } 486 487 error = riscv_of_parent_hartid(parent.np, &hartid); 488 if (error < 0) { 489 pr_warn("failed to parse hart ID for context %d.\n", i); 490 continue; 491 } 492 493 cpu = riscv_hartid_to_cpuid(hartid); 494 if (cpu < 0) { 495 pr_warn("Invalid cpuid for context %d\n", i); 496 continue; 497 } 498 499 /* Find parent domain and register chained handler */ 500 if (!plic_parent_irq && irq_find_host(parent.np)) { 501 plic_parent_irq = irq_of_parse_and_map(node, i); 502 if (plic_parent_irq) 503 irq_set_chained_handler(plic_parent_irq, 504 plic_handle_irq); 505 } 506 507 /* 508 * When running in M-mode we need to ignore the S-mode handler. 509 * Here we assume it always comes later, but that might be a 510 * little fragile. 511 */ 512 handler = per_cpu_ptr(&plic_handlers, cpu); 513 if (handler->present) { 514 pr_warn("handler already present for context %d.\n", i); 515 plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); 516 goto done; 517 } 518 519 cpumask_set_cpu(cpu, &priv->lmask); 520 handler->present = true; 521 handler->hart_base = priv->regs + CONTEXT_BASE + 522 i * CONTEXT_SIZE; 523 raw_spin_lock_init(&handler->enable_lock); 524 handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE + 525 i * CONTEXT_ENABLE_SIZE; 526 handler->priv = priv; 527 528 handler->enable_save = kcalloc(DIV_ROUND_UP(nr_irqs, 32), 529 sizeof(*handler->enable_save), GFP_KERNEL); 530 if (!handler->enable_save) 531 goto out_free_enable_reg; 532 done: 533 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { 534 plic_toggle(handler, hwirq, 0); 535 writel(1, priv->regs + PRIORITY_BASE + 536 hwirq * PRIORITY_PER_ID); 537 } 538 nr_handlers++; 539 } 540 541 /* 542 * We can have multiple PLIC instances so setup cpuhp state 543 * and register syscore operations only when context handler 544 * for current/boot CPU is present. 545 */ 546 handler = this_cpu_ptr(&plic_handlers); 547 if (handler->present && !plic_cpuhp_setup_done) { 548 cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, 549 "irqchip/sifive/plic:starting", 550 plic_starting_cpu, plic_dying_cpu); 551 register_syscore_ops(&plic_irq_syscore_ops); 552 plic_cpuhp_setup_done = true; 553 } 554 555 pr_info("%pOFP: mapped %d interrupts with %d handlers for" 556 " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); 557 return 0; 558 559 out_free_enable_reg: 560 for_each_cpu(cpu, cpu_present_mask) { 561 handler = per_cpu_ptr(&plic_handlers, cpu); 562 kfree(handler->enable_save); 563 } 564 out_free_priority_reg: 565 kfree(priv->prio_save); 566 out_iounmap: 567 iounmap(priv->regs); 568 out_free_priv: 569 kfree(priv); 570 return error; 571 } 572 573 static int __init plic_init(struct device_node *node, 574 struct device_node *parent) 575 { 576 return __plic_init(node, parent, 0); 577 } 578 579 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); 580 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ 581 582 static int __init plic_edge_init(struct device_node *node, 583 struct device_node *parent) 584 { 585 return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); 586 } 587 588 IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init); 589 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); 590