1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2017 SiFive 4 * Copyright (C) 2018 Christoph Hellwig 5 */ 6 #define pr_fmt(fmt) "plic: " fmt 7 #include <linux/cpu.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/module.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/platform_device.h> 19 #include <linux/spinlock.h> 20 #include <asm/smp.h> 21 22 /* 23 * This driver implements a version of the RISC-V PLIC with the actual layout 24 * specified in chapter 8 of the SiFive U5 Coreplex Series Manual: 25 * 26 * https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf 27 * 28 * The largest number supported by devices marked as 'sifive,plic-1.0.0', is 29 * 1024, of which device 0 is defined as non-existent by the RISC-V Privileged 30 * Spec. 31 */ 32 33 #define MAX_DEVICES 1024 34 #define MAX_CONTEXTS 15872 35 36 /* 37 * Each interrupt source has a priority register associated with it. 38 * We always hardwire it to one in Linux. 39 */ 40 #define PRIORITY_BASE 0 41 #define PRIORITY_PER_ID 4 42 43 /* 44 * Each hart context has a vector of interrupt enable bits associated with it. 45 * There's one bit for each interrupt source. 46 */ 47 #define CONTEXT_ENABLE_BASE 0x2000 48 #define CONTEXT_ENABLE_SIZE 0x80 49 50 /* 51 * Each hart context has a set of control registers associated with it. Right 52 * now there's only two: a source priority threshold over which the hart will 53 * take an interrupt, and a register to claim interrupts. 54 */ 55 #define CONTEXT_BASE 0x200000 56 #define CONTEXT_SIZE 0x1000 57 #define CONTEXT_THRESHOLD 0x00 58 #define CONTEXT_CLAIM 0x04 59 60 #define PLIC_DISABLE_THRESHOLD 0x7 61 #define PLIC_ENABLE_THRESHOLD 0 62 63 #define PLIC_QUIRK_EDGE_INTERRUPT 0 64 65 struct plic_priv { 66 struct cpumask lmask; 67 struct irq_domain *irqdomain; 68 void __iomem *regs; 69 unsigned long plic_quirks; 70 }; 71 72 struct plic_handler { 73 bool present; 74 void __iomem *hart_base; 75 /* 76 * Protect mask operations on the registers given that we can't 77 * assume atomic memory operations work on them. 78 */ 79 raw_spinlock_t enable_lock; 80 void __iomem *enable_base; 81 struct plic_priv *priv; 82 }; 83 static int plic_parent_irq __ro_after_init; 84 static bool plic_cpuhp_setup_done __ro_after_init; 85 static DEFINE_PER_CPU(struct plic_handler, plic_handlers); 86 87 static int plic_irq_set_type(struct irq_data *d, unsigned int type); 88 89 static void __plic_toggle(void __iomem *enable_base, int hwirq, int enable) 90 { 91 u32 __iomem *reg = enable_base + (hwirq / 32) * sizeof(u32); 92 u32 hwirq_mask = 1 << (hwirq % 32); 93 94 if (enable) 95 writel(readl(reg) | hwirq_mask, reg); 96 else 97 writel(readl(reg) & ~hwirq_mask, reg); 98 } 99 100 static void plic_toggle(struct plic_handler *handler, int hwirq, int enable) 101 { 102 raw_spin_lock(&handler->enable_lock); 103 __plic_toggle(handler->enable_base, hwirq, enable); 104 raw_spin_unlock(&handler->enable_lock); 105 } 106 107 static inline void plic_irq_toggle(const struct cpumask *mask, 108 struct irq_data *d, int enable) 109 { 110 int cpu; 111 112 for_each_cpu(cpu, mask) { 113 struct plic_handler *handler = per_cpu_ptr(&plic_handlers, cpu); 114 115 plic_toggle(handler, d->hwirq, enable); 116 } 117 } 118 119 static void plic_irq_enable(struct irq_data *d) 120 { 121 plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 1); 122 } 123 124 static void plic_irq_disable(struct irq_data *d) 125 { 126 plic_irq_toggle(irq_data_get_effective_affinity_mask(d), d, 0); 127 } 128 129 static void plic_irq_unmask(struct irq_data *d) 130 { 131 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 132 133 writel(1, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 134 } 135 136 static void plic_irq_mask(struct irq_data *d) 137 { 138 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 139 140 writel(0, priv->regs + PRIORITY_BASE + d->hwirq * PRIORITY_PER_ID); 141 } 142 143 static void plic_irq_eoi(struct irq_data *d) 144 { 145 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 146 147 writel(d->hwirq, handler->hart_base + CONTEXT_CLAIM); 148 } 149 150 #ifdef CONFIG_SMP 151 static int plic_set_affinity(struct irq_data *d, 152 const struct cpumask *mask_val, bool force) 153 { 154 unsigned int cpu; 155 struct cpumask amask; 156 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 157 158 cpumask_and(&amask, &priv->lmask, mask_val); 159 160 if (force) 161 cpu = cpumask_first(&amask); 162 else 163 cpu = cpumask_any_and(&amask, cpu_online_mask); 164 165 if (cpu >= nr_cpu_ids) 166 return -EINVAL; 167 168 plic_irq_disable(d); 169 170 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 171 172 if (!irqd_irq_disabled(d)) 173 plic_irq_enable(d); 174 175 return IRQ_SET_MASK_OK_DONE; 176 } 177 #endif 178 179 static struct irq_chip plic_edge_chip = { 180 .name = "SiFive PLIC", 181 .irq_enable = plic_irq_enable, 182 .irq_disable = plic_irq_disable, 183 .irq_ack = plic_irq_eoi, 184 .irq_mask = plic_irq_mask, 185 .irq_unmask = plic_irq_unmask, 186 #ifdef CONFIG_SMP 187 .irq_set_affinity = plic_set_affinity, 188 #endif 189 .irq_set_type = plic_irq_set_type, 190 .flags = IRQCHIP_AFFINITY_PRE_STARTUP, 191 }; 192 193 static struct irq_chip plic_chip = { 194 .name = "SiFive PLIC", 195 .irq_enable = plic_irq_enable, 196 .irq_disable = plic_irq_disable, 197 .irq_mask = plic_irq_mask, 198 .irq_unmask = plic_irq_unmask, 199 .irq_eoi = plic_irq_eoi, 200 #ifdef CONFIG_SMP 201 .irq_set_affinity = plic_set_affinity, 202 #endif 203 .irq_set_type = plic_irq_set_type, 204 .flags = IRQCHIP_AFFINITY_PRE_STARTUP, 205 }; 206 207 static int plic_irq_set_type(struct irq_data *d, unsigned int type) 208 { 209 struct plic_priv *priv = irq_data_get_irq_chip_data(d); 210 211 if (!test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) 212 return IRQ_SET_MASK_OK_NOCOPY; 213 214 switch (type) { 215 case IRQ_TYPE_EDGE_RISING: 216 irq_set_chip_handler_name_locked(d, &plic_edge_chip, 217 handle_edge_irq, NULL); 218 break; 219 case IRQ_TYPE_LEVEL_HIGH: 220 irq_set_chip_handler_name_locked(d, &plic_chip, 221 handle_fasteoi_irq, NULL); 222 break; 223 default: 224 return -EINVAL; 225 } 226 227 return IRQ_SET_MASK_OK; 228 } 229 230 static int plic_irqdomain_map(struct irq_domain *d, unsigned int irq, 231 irq_hw_number_t hwirq) 232 { 233 struct plic_priv *priv = d->host_data; 234 235 irq_domain_set_info(d, irq, hwirq, &plic_chip, d->host_data, 236 handle_fasteoi_irq, NULL, NULL); 237 irq_set_noprobe(irq); 238 irq_set_affinity(irq, &priv->lmask); 239 return 0; 240 } 241 242 static int plic_irq_domain_translate(struct irq_domain *d, 243 struct irq_fwspec *fwspec, 244 unsigned long *hwirq, 245 unsigned int *type) 246 { 247 struct plic_priv *priv = d->host_data; 248 249 if (test_bit(PLIC_QUIRK_EDGE_INTERRUPT, &priv->plic_quirks)) 250 return irq_domain_translate_twocell(d, fwspec, hwirq, type); 251 252 return irq_domain_translate_onecell(d, fwspec, hwirq, type); 253 } 254 255 static int plic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 256 unsigned int nr_irqs, void *arg) 257 { 258 int i, ret; 259 irq_hw_number_t hwirq; 260 unsigned int type; 261 struct irq_fwspec *fwspec = arg; 262 263 ret = plic_irq_domain_translate(domain, fwspec, &hwirq, &type); 264 if (ret) 265 return ret; 266 267 for (i = 0; i < nr_irqs; i++) { 268 ret = plic_irqdomain_map(domain, virq + i, hwirq + i); 269 if (ret) 270 return ret; 271 } 272 273 return 0; 274 } 275 276 static const struct irq_domain_ops plic_irqdomain_ops = { 277 .translate = plic_irq_domain_translate, 278 .alloc = plic_irq_domain_alloc, 279 .free = irq_domain_free_irqs_top, 280 }; 281 282 /* 283 * Handling an interrupt is a two-step process: first you claim the interrupt 284 * by reading the claim register, then you complete the interrupt by writing 285 * that source ID back to the same claim register. This automatically enables 286 * and disables the interrupt, so there's nothing else to do. 287 */ 288 static void plic_handle_irq(struct irq_desc *desc) 289 { 290 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 291 struct irq_chip *chip = irq_desc_get_chip(desc); 292 void __iomem *claim = handler->hart_base + CONTEXT_CLAIM; 293 irq_hw_number_t hwirq; 294 295 WARN_ON_ONCE(!handler->present); 296 297 chained_irq_enter(chip, desc); 298 299 while ((hwirq = readl(claim))) { 300 int err = generic_handle_domain_irq(handler->priv->irqdomain, 301 hwirq); 302 if (unlikely(err)) 303 pr_warn_ratelimited("can't find mapping for hwirq %lu\n", 304 hwirq); 305 } 306 307 chained_irq_exit(chip, desc); 308 } 309 310 static void plic_set_threshold(struct plic_handler *handler, u32 threshold) 311 { 312 /* priority must be > threshold to trigger an interrupt */ 313 writel(threshold, handler->hart_base + CONTEXT_THRESHOLD); 314 } 315 316 static int plic_dying_cpu(unsigned int cpu) 317 { 318 if (plic_parent_irq) 319 disable_percpu_irq(plic_parent_irq); 320 321 return 0; 322 } 323 324 static int plic_starting_cpu(unsigned int cpu) 325 { 326 struct plic_handler *handler = this_cpu_ptr(&plic_handlers); 327 328 if (plic_parent_irq) 329 enable_percpu_irq(plic_parent_irq, 330 irq_get_trigger_type(plic_parent_irq)); 331 else 332 pr_warn("cpu%d: parent irq not available\n", cpu); 333 plic_set_threshold(handler, PLIC_ENABLE_THRESHOLD); 334 335 return 0; 336 } 337 338 static int __init __plic_init(struct device_node *node, 339 struct device_node *parent, 340 unsigned long plic_quirks) 341 { 342 int error = 0, nr_contexts, nr_handlers = 0, i; 343 u32 nr_irqs; 344 struct plic_priv *priv; 345 struct plic_handler *handler; 346 347 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 348 if (!priv) 349 return -ENOMEM; 350 351 priv->plic_quirks = plic_quirks; 352 353 priv->regs = of_iomap(node, 0); 354 if (WARN_ON(!priv->regs)) { 355 error = -EIO; 356 goto out_free_priv; 357 } 358 359 error = -EINVAL; 360 of_property_read_u32(node, "riscv,ndev", &nr_irqs); 361 if (WARN_ON(!nr_irqs)) 362 goto out_iounmap; 363 364 nr_contexts = of_irq_count(node); 365 if (WARN_ON(!nr_contexts)) 366 goto out_iounmap; 367 368 error = -ENOMEM; 369 priv->irqdomain = irq_domain_add_linear(node, nr_irqs + 1, 370 &plic_irqdomain_ops, priv); 371 if (WARN_ON(!priv->irqdomain)) 372 goto out_iounmap; 373 374 for (i = 0; i < nr_contexts; i++) { 375 struct of_phandle_args parent; 376 irq_hw_number_t hwirq; 377 int cpu; 378 unsigned long hartid; 379 380 if (of_irq_parse_one(node, i, &parent)) { 381 pr_err("failed to parse parent for context %d.\n", i); 382 continue; 383 } 384 385 /* 386 * Skip contexts other than external interrupts for our 387 * privilege level. 388 */ 389 if (parent.args[0] != RV_IRQ_EXT) { 390 /* Disable S-mode enable bits if running in M-mode. */ 391 if (IS_ENABLED(CONFIG_RISCV_M_MODE)) { 392 void __iomem *enable_base = priv->regs + 393 CONTEXT_ENABLE_BASE + 394 i * CONTEXT_ENABLE_SIZE; 395 396 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) 397 __plic_toggle(enable_base, hwirq, 0); 398 } 399 continue; 400 } 401 402 error = riscv_of_parent_hartid(parent.np, &hartid); 403 if (error < 0) { 404 pr_warn("failed to parse hart ID for context %d.\n", i); 405 continue; 406 } 407 408 cpu = riscv_hartid_to_cpuid(hartid); 409 if (cpu < 0) { 410 pr_warn("Invalid cpuid for context %d\n", i); 411 continue; 412 } 413 414 /* Find parent domain and register chained handler */ 415 if (!plic_parent_irq && irq_find_host(parent.np)) { 416 plic_parent_irq = irq_of_parse_and_map(node, i); 417 if (plic_parent_irq) 418 irq_set_chained_handler(plic_parent_irq, 419 plic_handle_irq); 420 } 421 422 /* 423 * When running in M-mode we need to ignore the S-mode handler. 424 * Here we assume it always comes later, but that might be a 425 * little fragile. 426 */ 427 handler = per_cpu_ptr(&plic_handlers, cpu); 428 if (handler->present) { 429 pr_warn("handler already present for context %d.\n", i); 430 plic_set_threshold(handler, PLIC_DISABLE_THRESHOLD); 431 goto done; 432 } 433 434 cpumask_set_cpu(cpu, &priv->lmask); 435 handler->present = true; 436 handler->hart_base = priv->regs + CONTEXT_BASE + 437 i * CONTEXT_SIZE; 438 raw_spin_lock_init(&handler->enable_lock); 439 handler->enable_base = priv->regs + CONTEXT_ENABLE_BASE + 440 i * CONTEXT_ENABLE_SIZE; 441 handler->priv = priv; 442 done: 443 for (hwirq = 1; hwirq <= nr_irqs; hwirq++) { 444 plic_toggle(handler, hwirq, 0); 445 writel(1, priv->regs + PRIORITY_BASE + 446 hwirq * PRIORITY_PER_ID); 447 } 448 nr_handlers++; 449 } 450 451 /* 452 * We can have multiple PLIC instances so setup cpuhp state only 453 * when context handler for current/boot CPU is present. 454 */ 455 handler = this_cpu_ptr(&plic_handlers); 456 if (handler->present && !plic_cpuhp_setup_done) { 457 cpuhp_setup_state(CPUHP_AP_IRQ_SIFIVE_PLIC_STARTING, 458 "irqchip/sifive/plic:starting", 459 plic_starting_cpu, plic_dying_cpu); 460 plic_cpuhp_setup_done = true; 461 } 462 463 pr_info("%pOFP: mapped %d interrupts with %d handlers for" 464 " %d contexts.\n", node, nr_irqs, nr_handlers, nr_contexts); 465 return 0; 466 467 out_iounmap: 468 iounmap(priv->regs); 469 out_free_priv: 470 kfree(priv); 471 return error; 472 } 473 474 static int __init plic_init(struct device_node *node, 475 struct device_node *parent) 476 { 477 return __plic_init(node, parent, 0); 478 } 479 480 IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); 481 IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ 482 483 static int __init plic_edge_init(struct device_node *node, 484 struct device_node *parent) 485 { 486 return __plic_init(node, parent, BIT(PLIC_QUIRK_EDGE_INTERRUPT)); 487 } 488 489 IRQCHIP_DECLARE(andestech_nceplic100, "andestech,nceplic100", plic_edge_init); 490 IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_edge_init); 491