1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2012 Regents of the University of California
4  * Copyright (C) 2017-2018 SiFive
5  * Copyright (C) 2020 Western Digital Corporation or its affiliates.
6  */
7 
8 #define pr_fmt(fmt) "riscv-intc: " fmt
9 #include <linux/atomic.h>
10 #include <linux/bits.h>
11 #include <linux/cpu.h>
12 #include <linux/irq.h>
13 #include <linux/irqchip.h>
14 #include <linux/irqdomain.h>
15 #include <linux/interrupt.h>
16 #include <linux/module.h>
17 #include <linux/of.h>
18 #include <linux/smp.h>
19 
20 static struct irq_domain *intc_domain;
21 
22 static asmlinkage void riscv_intc_irq(struct pt_regs *regs)
23 {
24 	unsigned long cause = regs->cause & ~CAUSE_IRQ_FLAG;
25 
26 	if (unlikely(cause >= BITS_PER_LONG))
27 		panic("unexpected interrupt cause");
28 
29 	generic_handle_domain_irq(intc_domain, cause);
30 }
31 
32 /*
33  * On RISC-V systems local interrupts are masked or unmasked by writing
34  * the SIE (Supervisor Interrupt Enable) CSR.  As CSRs can only be written
35  * on the local hart, these functions can only be called on the hart that
36  * corresponds to the IRQ chip.
37  */
38 
39 static void riscv_intc_irq_mask(struct irq_data *d)
40 {
41 	csr_clear(CSR_IE, BIT(d->hwirq));
42 }
43 
44 static void riscv_intc_irq_unmask(struct irq_data *d)
45 {
46 	csr_set(CSR_IE, BIT(d->hwirq));
47 }
48 
49 static struct irq_chip riscv_intc_chip = {
50 	.name = "RISC-V INTC",
51 	.irq_mask = riscv_intc_irq_mask,
52 	.irq_unmask = riscv_intc_irq_unmask,
53 };
54 
55 static int riscv_intc_domain_map(struct irq_domain *d, unsigned int irq,
56 				 irq_hw_number_t hwirq)
57 {
58 	irq_set_percpu_devid(irq);
59 	irq_domain_set_info(d, irq, hwirq, &riscv_intc_chip, d->host_data,
60 			    handle_percpu_devid_irq, NULL, NULL);
61 
62 	return 0;
63 }
64 
65 static int riscv_intc_domain_alloc(struct irq_domain *domain,
66 				   unsigned int virq, unsigned int nr_irqs,
67 				   void *arg)
68 {
69 	int i, ret;
70 	irq_hw_number_t hwirq;
71 	unsigned int type = IRQ_TYPE_NONE;
72 	struct irq_fwspec *fwspec = arg;
73 
74 	ret = irq_domain_translate_onecell(domain, fwspec, &hwirq, &type);
75 	if (ret)
76 		return ret;
77 
78 	for (i = 0; i < nr_irqs; i++) {
79 		ret = riscv_intc_domain_map(domain, virq + i, hwirq + i);
80 		if (ret)
81 			return ret;
82 	}
83 
84 	return 0;
85 }
86 
87 static const struct irq_domain_ops riscv_intc_domain_ops = {
88 	.map	= riscv_intc_domain_map,
89 	.xlate	= irq_domain_xlate_onecell,
90 	.alloc	= riscv_intc_domain_alloc
91 };
92 
93 static struct fwnode_handle *riscv_intc_hwnode(void)
94 {
95 	return intc_domain->fwnode;
96 }
97 
98 static int __init riscv_intc_init(struct device_node *node,
99 				  struct device_node *parent)
100 {
101 	int rc;
102 	unsigned long hartid;
103 
104 	rc = riscv_of_parent_hartid(node, &hartid);
105 	if (rc < 0) {
106 		pr_warn("unable to find hart id for %pOF\n", node);
107 		return 0;
108 	}
109 
110 	/*
111 	 * The DT will have one INTC DT node under each CPU (or HART)
112 	 * DT node so riscv_intc_init() function will be called once
113 	 * for each INTC DT node. We only need to do INTC initialization
114 	 * for the INTC DT node belonging to boot CPU (or boot HART).
115 	 */
116 	if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
117 		return 0;
118 
119 	intc_domain = irq_domain_add_linear(node, BITS_PER_LONG,
120 					    &riscv_intc_domain_ops, NULL);
121 	if (!intc_domain) {
122 		pr_err("unable to add IRQ domain\n");
123 		return -ENXIO;
124 	}
125 
126 	rc = set_handle_irq(&riscv_intc_irq);
127 	if (rc) {
128 		pr_err("failed to set irq handler\n");
129 		return rc;
130 	}
131 
132 	riscv_set_intc_hwnode_fn(riscv_intc_hwnode);
133 
134 	pr_info("%d local interrupts mapped\n", BITS_PER_LONG);
135 
136 	return 0;
137 }
138 
139 IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init);
140