1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/G2L IRQC Driver 4 * 5 * Copyright (C) 2022 Renesas Electronics Corporation. 6 * 7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/err.h> 13 #include <linux/io.h> 14 #include <linux/irqchip.h> 15 #include <linux/irqdomain.h> 16 #include <linux/of_address.h> 17 #include <linux/of_platform.h> 18 #include <linux/pm_runtime.h> 19 #include <linux/reset.h> 20 #include <linux/spinlock.h> 21 22 #define IRQC_IRQ_START 1 23 #define IRQC_IRQ_COUNT 8 24 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT) 25 #define IRQC_TINT_COUNT 32 26 #define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT) 27 28 #define ISCR 0x10 29 #define IITSR 0x14 30 #define TSCR 0x20 31 #define TITSR(n) (0x24 + (n) * 4) 32 #define TITSR0_MAX_INT 16 33 #define TITSEL_WIDTH 0x2 34 #define TSSR(n) (0x30 + ((n) * 4)) 35 #define TIEN BIT(7) 36 #define TSSEL_SHIFT(n) (8 * (n)) 37 #define TSSEL_MASK GENMASK(7, 0) 38 #define IRQ_MASK 0x3 39 40 #define TSSR_OFFSET(n) ((n) % 4) 41 #define TSSR_INDEX(n) ((n) / 4) 42 43 #define TITSR_TITSEL_EDGE_RISING 0 44 #define TITSR_TITSEL_EDGE_FALLING 1 45 #define TITSR_TITSEL_LEVEL_HIGH 2 46 #define TITSR_TITSEL_LEVEL_LOW 3 47 48 #define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2)) 49 #define IITSR_IITSEL_LEVEL_LOW 0 50 #define IITSR_IITSEL_EDGE_FALLING 1 51 #define IITSR_IITSEL_EDGE_RISING 2 52 #define IITSR_IITSEL_EDGE_BOTH 3 53 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3) 54 55 #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x)) 56 #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x)) 57 58 struct rzg2l_irqc_priv { 59 void __iomem *base; 60 struct irq_fwspec fwspec[IRQC_NUM_IRQ]; 61 raw_spinlock_t lock; 62 }; 63 64 static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data) 65 { 66 return data->domain->host_data; 67 } 68 69 static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) 70 { 71 unsigned int hw_irq = hwirq - IRQC_IRQ_START; 72 u32 bit = BIT(hw_irq); 73 u32 iitsr, iscr; 74 75 iscr = readl_relaxed(priv->base + ISCR); 76 iitsr = readl_relaxed(priv->base + IITSR); 77 78 /* 79 * ISCR can only be cleared if the type is falling-edge, rising-edge or 80 * falling/rising-edge. 81 */ 82 if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) { 83 writel_relaxed(iscr & ~bit, priv->base + ISCR); 84 /* 85 * Enforce that the posted write is flushed to prevent that the 86 * just handled interrupt is raised again. 87 */ 88 readl_relaxed(priv->base + ISCR); 89 } 90 } 91 92 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq) 93 { 94 u32 bit = BIT(hwirq - IRQC_TINT_START); 95 u32 reg; 96 97 reg = readl_relaxed(priv->base + TSCR); 98 if (reg & bit) { 99 writel_relaxed(reg & ~bit, priv->base + TSCR); 100 /* 101 * Enforce that the posted write is flushed to prevent that the 102 * just handled interrupt is raised again. 103 */ 104 readl_relaxed(priv->base + TSCR); 105 } 106 } 107 108 static void rzg2l_irqc_eoi(struct irq_data *d) 109 { 110 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 111 unsigned int hw_irq = irqd_to_hwirq(d); 112 113 raw_spin_lock(&priv->lock); 114 if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) 115 rzg2l_clear_irq_int(priv, hw_irq); 116 else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) 117 rzg2l_clear_tint_int(priv, hw_irq); 118 raw_spin_unlock(&priv->lock); 119 irq_chip_eoi_parent(d); 120 } 121 122 static void rzg2l_irqc_irq_disable(struct irq_data *d) 123 { 124 unsigned int hw_irq = irqd_to_hwirq(d); 125 126 if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { 127 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 128 u32 offset = hw_irq - IRQC_TINT_START; 129 u32 tssr_offset = TSSR_OFFSET(offset); 130 u8 tssr_index = TSSR_INDEX(offset); 131 u32 reg; 132 133 raw_spin_lock(&priv->lock); 134 reg = readl_relaxed(priv->base + TSSR(tssr_index)); 135 reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); 136 writel_relaxed(reg, priv->base + TSSR(tssr_index)); 137 raw_spin_unlock(&priv->lock); 138 } 139 irq_chip_disable_parent(d); 140 } 141 142 static void rzg2l_irqc_irq_enable(struct irq_data *d) 143 { 144 unsigned int hw_irq = irqd_to_hwirq(d); 145 146 if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) { 147 unsigned long tint = (uintptr_t)irq_data_get_irq_chip_data(d); 148 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 149 u32 offset = hw_irq - IRQC_TINT_START; 150 u32 tssr_offset = TSSR_OFFSET(offset); 151 u8 tssr_index = TSSR_INDEX(offset); 152 u32 reg; 153 154 raw_spin_lock(&priv->lock); 155 reg = readl_relaxed(priv->base + TSSR(tssr_index)); 156 reg |= (TIEN | tint) << TSSEL_SHIFT(tssr_offset); 157 writel_relaxed(reg, priv->base + TSSR(tssr_index)); 158 raw_spin_unlock(&priv->lock); 159 } 160 irq_chip_enable_parent(d); 161 } 162 163 static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type) 164 { 165 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 166 unsigned int hwirq = irqd_to_hwirq(d); 167 u32 iitseln = hwirq - IRQC_IRQ_START; 168 bool clear_irq_int = false; 169 u16 sense, tmp; 170 171 switch (type & IRQ_TYPE_SENSE_MASK) { 172 case IRQ_TYPE_LEVEL_LOW: 173 sense = IITSR_IITSEL_LEVEL_LOW; 174 break; 175 176 case IRQ_TYPE_EDGE_FALLING: 177 sense = IITSR_IITSEL_EDGE_FALLING; 178 clear_irq_int = true; 179 break; 180 181 case IRQ_TYPE_EDGE_RISING: 182 sense = IITSR_IITSEL_EDGE_RISING; 183 clear_irq_int = true; 184 break; 185 186 case IRQ_TYPE_EDGE_BOTH: 187 sense = IITSR_IITSEL_EDGE_BOTH; 188 clear_irq_int = true; 189 break; 190 191 default: 192 return -EINVAL; 193 } 194 195 raw_spin_lock(&priv->lock); 196 tmp = readl_relaxed(priv->base + IITSR); 197 tmp &= ~IITSR_IITSEL_MASK(iitseln); 198 tmp |= IITSR_IITSEL(iitseln, sense); 199 if (clear_irq_int) 200 rzg2l_clear_irq_int(priv, hwirq); 201 writel_relaxed(tmp, priv->base + IITSR); 202 raw_spin_unlock(&priv->lock); 203 204 return 0; 205 } 206 207 static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv, 208 u32 reg, u32 tssr_offset, u8 tssr_index) 209 { 210 u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d); 211 u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset)); 212 213 /* Clear the relevant byte in reg */ 214 reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset)); 215 /* Set TINT and leave TIEN clear */ 216 reg |= tint << TSSEL_SHIFT(tssr_offset); 217 writel_relaxed(reg, priv->base + TSSR(tssr_index)); 218 219 return reg | tien; 220 } 221 222 static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type) 223 { 224 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d); 225 unsigned int hwirq = irqd_to_hwirq(d); 226 u32 titseln = hwirq - IRQC_TINT_START; 227 u32 tssr_offset = TSSR_OFFSET(titseln); 228 u8 tssr_index = TSSR_INDEX(titseln); 229 u8 index, sense; 230 u32 reg, tssr; 231 232 switch (type & IRQ_TYPE_SENSE_MASK) { 233 case IRQ_TYPE_EDGE_RISING: 234 sense = TITSR_TITSEL_EDGE_RISING; 235 break; 236 237 case IRQ_TYPE_EDGE_FALLING: 238 sense = TITSR_TITSEL_EDGE_FALLING; 239 break; 240 241 default: 242 return -EINVAL; 243 } 244 245 index = 0; 246 if (titseln >= TITSR0_MAX_INT) { 247 titseln -= TITSR0_MAX_INT; 248 index = 1; 249 } 250 251 raw_spin_lock(&priv->lock); 252 tssr = readl_relaxed(priv->base + TSSR(tssr_index)); 253 tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index); 254 reg = readl_relaxed(priv->base + TITSR(index)); 255 reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH)); 256 reg |= sense << (titseln * TITSEL_WIDTH); 257 writel_relaxed(reg, priv->base + TITSR(index)); 258 rzg2l_clear_tint_int(priv, hwirq); 259 writel_relaxed(tssr, priv->base + TSSR(tssr_index)); 260 raw_spin_unlock(&priv->lock); 261 262 return 0; 263 } 264 265 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type) 266 { 267 unsigned int hw_irq = irqd_to_hwirq(d); 268 int ret = -EINVAL; 269 270 if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT) 271 ret = rzg2l_irq_set_type(d, type); 272 else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) 273 ret = rzg2l_tint_set_edge(d, type); 274 if (ret) 275 return ret; 276 277 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH); 278 } 279 280 static const struct irq_chip irqc_chip = { 281 .name = "rzg2l-irqc", 282 .irq_eoi = rzg2l_irqc_eoi, 283 .irq_mask = irq_chip_mask_parent, 284 .irq_unmask = irq_chip_unmask_parent, 285 .irq_disable = rzg2l_irqc_irq_disable, 286 .irq_enable = rzg2l_irqc_irq_enable, 287 .irq_get_irqchip_state = irq_chip_get_parent_state, 288 .irq_set_irqchip_state = irq_chip_set_parent_state, 289 .irq_retrigger = irq_chip_retrigger_hierarchy, 290 .irq_set_type = rzg2l_irqc_set_type, 291 .flags = IRQCHIP_MASK_ON_SUSPEND | 292 IRQCHIP_SET_TYPE_MASKED | 293 IRQCHIP_SKIP_SET_WAKE, 294 }; 295 296 static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq, 297 unsigned int nr_irqs, void *arg) 298 { 299 struct rzg2l_irqc_priv *priv = domain->host_data; 300 unsigned long tint = 0; 301 irq_hw_number_t hwirq; 302 unsigned int type; 303 int ret; 304 305 ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type); 306 if (ret) 307 return ret; 308 309 /* 310 * For TINT interrupts ie where pinctrl driver is child of irqc domain 311 * the hwirq and TINT are encoded in fwspec->param[0]. 312 * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT 313 * from 16-31 bits. TINT from the pinctrl driver needs to be programmed 314 * in IRQC registers to enable a given gpio pin as interrupt. 315 */ 316 if (hwirq > IRQC_IRQ_COUNT) { 317 tint = TINT_EXTRACT_GPIOINT(hwirq); 318 hwirq = TINT_EXTRACT_HWIRQ(hwirq); 319 320 if (hwirq < IRQC_TINT_START) 321 return -EINVAL; 322 } 323 324 if (hwirq > (IRQC_NUM_IRQ - 1)) 325 return -EINVAL; 326 327 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip, 328 (void *)(uintptr_t)tint); 329 if (ret) 330 return ret; 331 332 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]); 333 } 334 335 static const struct irq_domain_ops rzg2l_irqc_domain_ops = { 336 .alloc = rzg2l_irqc_alloc, 337 .free = irq_domain_free_irqs_common, 338 .translate = irq_domain_translate_twocell, 339 }; 340 341 static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv, 342 struct device_node *np) 343 { 344 struct of_phandle_args map; 345 unsigned int i; 346 int ret; 347 348 for (i = 0; i < IRQC_NUM_IRQ; i++) { 349 ret = of_irq_parse_one(np, i, &map); 350 if (ret) 351 return ret; 352 of_phandle_args_to_fwspec(np, map.args, map.args_count, 353 &priv->fwspec[i]); 354 } 355 356 return 0; 357 } 358 359 static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent) 360 { 361 struct irq_domain *irq_domain, *parent_domain; 362 struct platform_device *pdev; 363 struct reset_control *resetn; 364 struct rzg2l_irqc_priv *priv; 365 int ret; 366 367 pdev = of_find_device_by_node(node); 368 if (!pdev) 369 return -ENODEV; 370 371 parent_domain = irq_find_host(parent); 372 if (!parent_domain) { 373 dev_err(&pdev->dev, "cannot find parent domain\n"); 374 return -ENODEV; 375 } 376 377 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); 378 if (!priv) 379 return -ENOMEM; 380 381 priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL); 382 if (IS_ERR(priv->base)) 383 return PTR_ERR(priv->base); 384 385 ret = rzg2l_irqc_parse_interrupts(priv, node); 386 if (ret) { 387 dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret); 388 return ret; 389 } 390 391 resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL); 392 if (IS_ERR(resetn)) 393 return PTR_ERR(resetn); 394 395 ret = reset_control_deassert(resetn); 396 if (ret) { 397 dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret); 398 return ret; 399 } 400 401 pm_runtime_enable(&pdev->dev); 402 ret = pm_runtime_resume_and_get(&pdev->dev); 403 if (ret < 0) { 404 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret); 405 goto pm_disable; 406 } 407 408 raw_spin_lock_init(&priv->lock); 409 410 irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ, 411 node, &rzg2l_irqc_domain_ops, 412 priv); 413 if (!irq_domain) { 414 dev_err(&pdev->dev, "failed to add irq domain\n"); 415 ret = -ENOMEM; 416 goto pm_put; 417 } 418 419 return 0; 420 421 pm_put: 422 pm_runtime_put(&pdev->dev); 423 pm_disable: 424 pm_runtime_disable(&pdev->dev); 425 reset_control_assert(resetn); 426 return ret; 427 } 428 429 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc) 430 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init) 431 IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc) 432 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>"); 433 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver"); 434