1 /* 2 * Renesas IRQC Driver 3 * 4 * Copyright (C) 2013 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ioport.h> 25 #include <linux/io.h> 26 #include <linux/irq.h> 27 #include <linux/irqdomain.h> 28 #include <linux/err.h> 29 #include <linux/slab.h> 30 #include <linux/module.h> 31 #include <linux/platform_data/irq-renesas-irqc.h> 32 33 #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ 34 35 #define IRQC_REQ_STS 0x00 36 #define IRQC_EN_STS 0x04 37 #define IRQC_EN_SET 0x08 38 #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) 39 #define DETECT_STATUS 0x100 40 #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) 41 42 struct irqc_irq { 43 int hw_irq; 44 int requested_irq; 45 int domain_irq; 46 struct irqc_priv *p; 47 }; 48 49 struct irqc_priv { 50 void __iomem *iomem; 51 void __iomem *cpu_int_base; 52 struct irqc_irq irq[IRQC_IRQ_MAX]; 53 struct renesas_irqc_config config; 54 unsigned int number_of_irqs; 55 struct platform_device *pdev; 56 struct irq_chip irq_chip; 57 struct irq_domain *irq_domain; 58 }; 59 60 static void irqc_dbg(struct irqc_irq *i, char *str) 61 { 62 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", 63 str, i->requested_irq, i->hw_irq, i->domain_irq); 64 } 65 66 static void irqc_irq_enable(struct irq_data *d) 67 { 68 struct irqc_priv *p = irq_data_get_irq_chip_data(d); 69 int hw_irq = irqd_to_hwirq(d); 70 71 irqc_dbg(&p->irq[hw_irq], "enable"); 72 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET); 73 } 74 75 static void irqc_irq_disable(struct irq_data *d) 76 { 77 struct irqc_priv *p = irq_data_get_irq_chip_data(d); 78 int hw_irq = irqd_to_hwirq(d); 79 80 irqc_dbg(&p->irq[hw_irq], "disable"); 81 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); 82 } 83 84 #define INTC_IRQ_SENSE_VALID 0x10 85 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) 86 87 static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { 88 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x01), 89 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x02), 90 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x04), /* Synchronous */ 91 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x08), /* Synchronous */ 92 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x0c), /* Synchronous */ 93 }; 94 95 static int irqc_irq_set_type(struct irq_data *d, unsigned int type) 96 { 97 struct irqc_priv *p = irq_data_get_irq_chip_data(d); 98 int hw_irq = irqd_to_hwirq(d); 99 unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK]; 100 unsigned long tmp; 101 102 irqc_dbg(&p->irq[hw_irq], "sense"); 103 104 if (!(value & INTC_IRQ_SENSE_VALID)) 105 return -EINVAL; 106 107 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); 108 tmp &= ~0x3f; 109 tmp |= value ^ INTC_IRQ_SENSE_VALID; 110 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); 111 return 0; 112 } 113 114 static irqreturn_t irqc_irq_handler(int irq, void *dev_id) 115 { 116 struct irqc_irq *i = dev_id; 117 struct irqc_priv *p = i->p; 118 unsigned long bit = BIT(i->hw_irq); 119 120 irqc_dbg(i, "demux1"); 121 122 if (ioread32(p->iomem + DETECT_STATUS) & bit) { 123 iowrite32(bit, p->iomem + DETECT_STATUS); 124 irqc_dbg(i, "demux2"); 125 generic_handle_irq(i->domain_irq); 126 return IRQ_HANDLED; 127 } 128 return IRQ_NONE; 129 } 130 131 static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, 132 irq_hw_number_t hw) 133 { 134 struct irqc_priv *p = h->host_data; 135 136 p->irq[hw].domain_irq = virq; 137 p->irq[hw].hw_irq = hw; 138 139 irqc_dbg(&p->irq[hw], "map"); 140 irq_set_chip_data(virq, h->host_data); 141 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); 142 set_irq_flags(virq, IRQF_VALID); /* kill me now */ 143 return 0; 144 } 145 146 static struct irq_domain_ops irqc_irq_domain_ops = { 147 .map = irqc_irq_domain_map, 148 .xlate = irq_domain_xlate_twocell, 149 }; 150 151 static int irqc_probe(struct platform_device *pdev) 152 { 153 struct renesas_irqc_config *pdata = pdev->dev.platform_data; 154 struct irqc_priv *p; 155 struct resource *io; 156 struct resource *irq; 157 struct irq_chip *irq_chip; 158 const char *name = dev_name(&pdev->dev); 159 int ret; 160 int k; 161 162 p = kzalloc(sizeof(*p), GFP_KERNEL); 163 if (!p) { 164 dev_err(&pdev->dev, "failed to allocate driver data\n"); 165 ret = -ENOMEM; 166 goto err0; 167 } 168 169 /* deal with driver instance configuration */ 170 if (pdata) 171 memcpy(&p->config, pdata, sizeof(*pdata)); 172 173 p->pdev = pdev; 174 platform_set_drvdata(pdev, p); 175 176 /* get hold of manadatory IOMEM */ 177 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 178 if (!io) { 179 dev_err(&pdev->dev, "not enough IOMEM resources\n"); 180 ret = -EINVAL; 181 goto err1; 182 } 183 184 /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */ 185 for (k = 0; k < IRQC_IRQ_MAX; k++) { 186 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); 187 if (!irq) 188 break; 189 190 p->irq[k].p = p; 191 p->irq[k].requested_irq = irq->start; 192 } 193 194 p->number_of_irqs = k; 195 if (p->number_of_irqs < 1) { 196 dev_err(&pdev->dev, "not enough IRQ resources\n"); 197 ret = -EINVAL; 198 goto err1; 199 } 200 201 /* ioremap IOMEM and setup read/write callbacks */ 202 p->iomem = ioremap_nocache(io->start, resource_size(io)); 203 if (!p->iomem) { 204 dev_err(&pdev->dev, "failed to remap IOMEM\n"); 205 ret = -ENXIO; 206 goto err2; 207 } 208 209 p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */ 210 211 irq_chip = &p->irq_chip; 212 irq_chip->name = name; 213 irq_chip->irq_mask = irqc_irq_disable; 214 irq_chip->irq_unmask = irqc_irq_enable; 215 irq_chip->irq_enable = irqc_irq_enable; 216 irq_chip->irq_disable = irqc_irq_disable; 217 irq_chip->irq_set_type = irqc_irq_set_type; 218 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; 219 220 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 221 p->number_of_irqs, 222 p->config.irq_base, 223 &irqc_irq_domain_ops, p); 224 if (!p->irq_domain) { 225 ret = -ENXIO; 226 dev_err(&pdev->dev, "cannot initialize irq domain\n"); 227 goto err2; 228 } 229 230 /* request interrupts one by one */ 231 for (k = 0; k < p->number_of_irqs; k++) { 232 if (request_irq(p->irq[k].requested_irq, irqc_irq_handler, 233 0, name, &p->irq[k])) { 234 dev_err(&pdev->dev, "failed to request IRQ\n"); 235 ret = -ENOENT; 236 goto err3; 237 } 238 } 239 240 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); 241 242 /* warn in case of mismatch if irq base is specified */ 243 if (p->config.irq_base) { 244 if (p->config.irq_base != p->irq[0].domain_irq) 245 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", 246 p->config.irq_base, p->irq[0].domain_irq); 247 } 248 249 return 0; 250 err3: 251 for (; k >= 0; k--) 252 free_irq(p->irq[k - 1].requested_irq, &p->irq[k - 1]); 253 254 irq_domain_remove(p->irq_domain); 255 err2: 256 iounmap(p->iomem); 257 err1: 258 kfree(p); 259 err0: 260 return ret; 261 } 262 263 static int irqc_remove(struct platform_device *pdev) 264 { 265 struct irqc_priv *p = platform_get_drvdata(pdev); 266 int k; 267 268 for (k = 0; k < p->number_of_irqs; k++) 269 free_irq(p->irq[k].requested_irq, &p->irq[k]); 270 271 irq_domain_remove(p->irq_domain); 272 iounmap(p->iomem); 273 kfree(p); 274 return 0; 275 } 276 277 static const struct of_device_id irqc_dt_ids[] = { 278 { .compatible = "renesas,irqc", }, 279 {}, 280 }; 281 MODULE_DEVICE_TABLE(of, irqc_dt_ids); 282 283 static struct platform_driver irqc_device_driver = { 284 .probe = irqc_probe, 285 .remove = irqc_remove, 286 .driver = { 287 .name = "renesas_irqc", 288 .of_match_table = irqc_dt_ids, 289 .owner = THIS_MODULE, 290 } 291 }; 292 293 static int __init irqc_init(void) 294 { 295 return platform_driver_register(&irqc_device_driver); 296 } 297 postcore_initcall(irqc_init); 298 299 static void __exit irqc_exit(void) 300 { 301 platform_driver_unregister(&irqc_device_driver); 302 } 303 module_exit(irqc_exit); 304 305 MODULE_AUTHOR("Magnus Damm"); 306 MODULE_DESCRIPTION("Renesas IRQC Driver"); 307 MODULE_LICENSE("GPL v2"); 308