1 /* 2 * Renesas IRQC Driver 3 * 4 * Copyright (C) 2013 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/init.h> 22 #include <linux/platform_device.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 #include <linux/ioport.h> 26 #include <linux/io.h> 27 #include <linux/irq.h> 28 #include <linux/irqdomain.h> 29 #include <linux/err.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <linux/pm_runtime.h> 33 34 #define IRQC_IRQ_MAX 32 /* maximum 32 interrupts per driver instance */ 35 36 #define IRQC_REQ_STS 0x00 /* Interrupt Request Status Register */ 37 #define IRQC_EN_STS 0x04 /* Interrupt Enable Status Register */ 38 #define IRQC_EN_SET 0x08 /* Interrupt Enable Set Register */ 39 #define IRQC_INT_CPU_BASE(n) (0x000 + ((n) * 0x10)) 40 /* SYS-CPU vs. RT-CPU */ 41 #define DETECT_STATUS 0x100 /* IRQn Detect Status Register */ 42 #define MONITOR 0x104 /* IRQn Signal Level Monitor Register */ 43 #define HLVL_STS 0x108 /* IRQn High Level Detect Status Register */ 44 #define LLVL_STS 0x10c /* IRQn Low Level Detect Status Register */ 45 #define S_R_EDGE_STS 0x110 /* IRQn Sync Rising Edge Detect Status Reg. */ 46 #define S_F_EDGE_STS 0x114 /* IRQn Sync Falling Edge Detect Status Reg. */ 47 #define A_R_EDGE_STS 0x118 /* IRQn Async Rising Edge Detect Status Reg. */ 48 #define A_F_EDGE_STS 0x11c /* IRQn Async Falling Edge Detect Status Reg. */ 49 #define CHTEN_STS 0x120 /* Chattering Reduction Status Register */ 50 #define IRQC_CONFIG(n) (0x180 + ((n) * 0x04)) 51 /* IRQn Configuration Register */ 52 53 struct irqc_irq { 54 int hw_irq; 55 int requested_irq; 56 struct irqc_priv *p; 57 }; 58 59 struct irqc_priv { 60 void __iomem *iomem; 61 void __iomem *cpu_int_base; 62 struct irqc_irq irq[IRQC_IRQ_MAX]; 63 unsigned int number_of_irqs; 64 struct platform_device *pdev; 65 struct irq_chip irq_chip; 66 struct irq_domain *irq_domain; 67 struct clk *clk; 68 }; 69 70 static void irqc_dbg(struct irqc_irq *i, char *str) 71 { 72 dev_dbg(&i->p->pdev->dev, "%s (%d:%d)\n", 73 str, i->requested_irq, i->hw_irq); 74 } 75 76 static void irqc_irq_enable(struct irq_data *d) 77 { 78 struct irqc_priv *p = irq_data_get_irq_chip_data(d); 79 int hw_irq = irqd_to_hwirq(d); 80 81 irqc_dbg(&p->irq[hw_irq], "enable"); 82 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_SET); 83 } 84 85 static void irqc_irq_disable(struct irq_data *d) 86 { 87 struct irqc_priv *p = irq_data_get_irq_chip_data(d); 88 int hw_irq = irqd_to_hwirq(d); 89 90 irqc_dbg(&p->irq[hw_irq], "disable"); 91 iowrite32(BIT(hw_irq), p->cpu_int_base + IRQC_EN_STS); 92 } 93 94 static unsigned char irqc_sense[IRQ_TYPE_SENSE_MASK + 1] = { 95 [IRQ_TYPE_LEVEL_LOW] = 0x01, 96 [IRQ_TYPE_LEVEL_HIGH] = 0x02, 97 [IRQ_TYPE_EDGE_FALLING] = 0x04, /* Synchronous */ 98 [IRQ_TYPE_EDGE_RISING] = 0x08, /* Synchronous */ 99 [IRQ_TYPE_EDGE_BOTH] = 0x0c, /* Synchronous */ 100 }; 101 102 static int irqc_irq_set_type(struct irq_data *d, unsigned int type) 103 { 104 struct irqc_priv *p = irq_data_get_irq_chip_data(d); 105 int hw_irq = irqd_to_hwirq(d); 106 unsigned char value = irqc_sense[type & IRQ_TYPE_SENSE_MASK]; 107 u32 tmp; 108 109 irqc_dbg(&p->irq[hw_irq], "sense"); 110 111 if (!value) 112 return -EINVAL; 113 114 tmp = ioread32(p->iomem + IRQC_CONFIG(hw_irq)); 115 tmp &= ~0x3f; 116 tmp |= value; 117 iowrite32(tmp, p->iomem + IRQC_CONFIG(hw_irq)); 118 return 0; 119 } 120 121 static int irqc_irq_set_wake(struct irq_data *d, unsigned int on) 122 { 123 struct irqc_priv *p = irq_data_get_irq_chip_data(d); 124 125 if (!p->clk) 126 return 0; 127 128 if (on) 129 clk_enable(p->clk); 130 else 131 clk_disable(p->clk); 132 133 return 0; 134 } 135 136 static irqreturn_t irqc_irq_handler(int irq, void *dev_id) 137 { 138 struct irqc_irq *i = dev_id; 139 struct irqc_priv *p = i->p; 140 u32 bit = BIT(i->hw_irq); 141 142 irqc_dbg(i, "demux1"); 143 144 if (ioread32(p->iomem + DETECT_STATUS) & bit) { 145 iowrite32(bit, p->iomem + DETECT_STATUS); 146 irqc_dbg(i, "demux2"); 147 generic_handle_irq(irq_find_mapping(p->irq_domain, i->hw_irq)); 148 return IRQ_HANDLED; 149 } 150 return IRQ_NONE; 151 } 152 153 static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq, 154 irq_hw_number_t hw) 155 { 156 struct irqc_priv *p = h->host_data; 157 158 irqc_dbg(&p->irq[hw], "map"); 159 irq_set_chip_data(virq, h->host_data); 160 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); 161 return 0; 162 } 163 164 static const struct irq_domain_ops irqc_irq_domain_ops = { 165 .map = irqc_irq_domain_map, 166 .xlate = irq_domain_xlate_twocell, 167 }; 168 169 static int irqc_probe(struct platform_device *pdev) 170 { 171 struct irqc_priv *p; 172 struct resource *io; 173 struct resource *irq; 174 struct irq_chip *irq_chip; 175 const char *name = dev_name(&pdev->dev); 176 int ret; 177 int k; 178 179 p = kzalloc(sizeof(*p), GFP_KERNEL); 180 if (!p) { 181 dev_err(&pdev->dev, "failed to allocate driver data\n"); 182 ret = -ENOMEM; 183 goto err0; 184 } 185 186 p->pdev = pdev; 187 platform_set_drvdata(pdev, p); 188 189 p->clk = devm_clk_get(&pdev->dev, NULL); 190 if (IS_ERR(p->clk)) { 191 dev_warn(&pdev->dev, "unable to get clock\n"); 192 p->clk = NULL; 193 } 194 195 pm_runtime_enable(&pdev->dev); 196 pm_runtime_get_sync(&pdev->dev); 197 198 /* get hold of manadatory IOMEM */ 199 io = platform_get_resource(pdev, IORESOURCE_MEM, 0); 200 if (!io) { 201 dev_err(&pdev->dev, "not enough IOMEM resources\n"); 202 ret = -EINVAL; 203 goto err1; 204 } 205 206 /* allow any number of IRQs between 1 and IRQC_IRQ_MAX */ 207 for (k = 0; k < IRQC_IRQ_MAX; k++) { 208 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); 209 if (!irq) 210 break; 211 212 p->irq[k].p = p; 213 p->irq[k].hw_irq = k; 214 p->irq[k].requested_irq = irq->start; 215 } 216 217 p->number_of_irqs = k; 218 if (p->number_of_irqs < 1) { 219 dev_err(&pdev->dev, "not enough IRQ resources\n"); 220 ret = -EINVAL; 221 goto err1; 222 } 223 224 /* ioremap IOMEM and setup read/write callbacks */ 225 p->iomem = ioremap_nocache(io->start, resource_size(io)); 226 if (!p->iomem) { 227 dev_err(&pdev->dev, "failed to remap IOMEM\n"); 228 ret = -ENXIO; 229 goto err2; 230 } 231 232 p->cpu_int_base = p->iomem + IRQC_INT_CPU_BASE(0); /* SYS-SPI */ 233 234 irq_chip = &p->irq_chip; 235 irq_chip->name = name; 236 irq_chip->irq_mask = irqc_irq_disable; 237 irq_chip->irq_unmask = irqc_irq_enable; 238 irq_chip->irq_set_type = irqc_irq_set_type; 239 irq_chip->irq_set_wake = irqc_irq_set_wake; 240 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND; 241 242 p->irq_domain = irq_domain_add_linear(pdev->dev.of_node, 243 p->number_of_irqs, 244 &irqc_irq_domain_ops, p); 245 if (!p->irq_domain) { 246 ret = -ENXIO; 247 dev_err(&pdev->dev, "cannot initialize irq domain\n"); 248 goto err2; 249 } 250 251 /* request interrupts one by one */ 252 for (k = 0; k < p->number_of_irqs; k++) { 253 if (request_irq(p->irq[k].requested_irq, irqc_irq_handler, 254 0, name, &p->irq[k])) { 255 dev_err(&pdev->dev, "failed to request IRQ\n"); 256 ret = -ENOENT; 257 goto err3; 258 } 259 } 260 261 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); 262 263 return 0; 264 err3: 265 while (--k >= 0) 266 free_irq(p->irq[k].requested_irq, &p->irq[k]); 267 268 irq_domain_remove(p->irq_domain); 269 err2: 270 iounmap(p->iomem); 271 err1: 272 pm_runtime_put(&pdev->dev); 273 pm_runtime_disable(&pdev->dev); 274 kfree(p); 275 err0: 276 return ret; 277 } 278 279 static int irqc_remove(struct platform_device *pdev) 280 { 281 struct irqc_priv *p = platform_get_drvdata(pdev); 282 int k; 283 284 for (k = 0; k < p->number_of_irqs; k++) 285 free_irq(p->irq[k].requested_irq, &p->irq[k]); 286 287 irq_domain_remove(p->irq_domain); 288 iounmap(p->iomem); 289 pm_runtime_put(&pdev->dev); 290 pm_runtime_disable(&pdev->dev); 291 kfree(p); 292 return 0; 293 } 294 295 static const struct of_device_id irqc_dt_ids[] = { 296 { .compatible = "renesas,irqc", }, 297 {}, 298 }; 299 MODULE_DEVICE_TABLE(of, irqc_dt_ids); 300 301 static struct platform_driver irqc_device_driver = { 302 .probe = irqc_probe, 303 .remove = irqc_remove, 304 .driver = { 305 .name = "renesas_irqc", 306 .of_match_table = irqc_dt_ids, 307 } 308 }; 309 310 static int __init irqc_init(void) 311 { 312 return platform_driver_register(&irqc_device_driver); 313 } 314 postcore_initcall(irqc_init); 315 316 static void __exit irqc_exit(void) 317 { 318 platform_driver_unregister(&irqc_device_driver); 319 } 320 module_exit(irqc_exit); 321 322 MODULE_AUTHOR("Magnus Damm"); 323 MODULE_DESCRIPTION("Renesas IRQC Driver"); 324 MODULE_LICENSE("GPL v2"); 325