1 /* 2 * Renesas INTC External IRQ Pin Driver 3 * 4 * Copyright (C) 2013 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/clk.h> 21 #include <linux/init.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/spinlock.h> 25 #include <linux/interrupt.h> 26 #include <linux/ioport.h> 27 #include <linux/io.h> 28 #include <linux/irq.h> 29 #include <linux/irqdomain.h> 30 #include <linux/err.h> 31 #include <linux/slab.h> 32 #include <linux/module.h> 33 #include <linux/of_device.h> 34 #include <linux/pm_runtime.h> 35 36 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */ 37 38 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */ 39 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */ 40 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */ 41 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */ 42 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */ 43 #define INTC_IRQPIN_REG_NR_MANDATORY 5 44 #define INTC_IRQPIN_REG_IRLM 5 /* ICR0 with IRLM bit (optional) */ 45 #define INTC_IRQPIN_REG_NR 6 46 47 /* INTC external IRQ PIN hardware register access: 48 * 49 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*) 50 * PRIO is read-write 32-bit with 4-bits per IRQ (**) 51 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***) 52 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 53 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 54 * 55 * (*) May be accessed by more than one driver instance - lock needed 56 * (**) Read-modify-write access by one driver instance - lock needed 57 * (***) Accessed by one driver instance only - no locking needed 58 */ 59 60 struct intc_irqpin_iomem { 61 void __iomem *iomem; 62 unsigned long (*read)(void __iomem *iomem); 63 void (*write)(void __iomem *iomem, unsigned long data); 64 int width; 65 }; 66 67 struct intc_irqpin_irq { 68 int hw_irq; 69 int requested_irq; 70 int domain_irq; 71 struct intc_irqpin_priv *p; 72 }; 73 74 struct intc_irqpin_priv { 75 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; 76 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX]; 77 unsigned int sense_bitfield_width; 78 struct platform_device *pdev; 79 struct irq_chip irq_chip; 80 struct irq_domain *irq_domain; 81 struct clk *clk; 82 unsigned shared_irqs:1; 83 unsigned needs_clk:1; 84 u8 shared_irq_mask; 85 }; 86 87 struct intc_irqpin_config { 88 unsigned int irlm_bit; 89 unsigned needs_irlm:1; 90 unsigned needs_clk:1; 91 }; 92 93 static unsigned long intc_irqpin_read32(void __iomem *iomem) 94 { 95 return ioread32(iomem); 96 } 97 98 static unsigned long intc_irqpin_read8(void __iomem *iomem) 99 { 100 return ioread8(iomem); 101 } 102 103 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data) 104 { 105 iowrite32(data, iomem); 106 } 107 108 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data) 109 { 110 iowrite8(data, iomem); 111 } 112 113 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, 114 int reg) 115 { 116 struct intc_irqpin_iomem *i = &p->iomem[reg]; 117 118 return i->read(i->iomem); 119 } 120 121 static inline void intc_irqpin_write(struct intc_irqpin_priv *p, 122 int reg, unsigned long data) 123 { 124 struct intc_irqpin_iomem *i = &p->iomem[reg]; 125 126 i->write(i->iomem, data); 127 } 128 129 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p, 130 int reg, int hw_irq) 131 { 132 return BIT((p->iomem[reg].width - 1) - hw_irq); 133 } 134 135 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p, 136 int reg, int hw_irq) 137 { 138 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); 139 } 140 141 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */ 142 143 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, 144 int reg, int shift, 145 int width, int value) 146 { 147 unsigned long flags; 148 unsigned long tmp; 149 150 raw_spin_lock_irqsave(&intc_irqpin_lock, flags); 151 152 tmp = intc_irqpin_read(p, reg); 153 tmp &= ~(((1 << width) - 1) << shift); 154 tmp |= value << shift; 155 intc_irqpin_write(p, reg, tmp); 156 157 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags); 158 } 159 160 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, 161 int irq, int do_mask) 162 { 163 /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */ 164 int bitfield_width = 4; 165 int shift = 32 - (irq + 1) * bitfield_width; 166 167 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, 168 shift, bitfield_width, 169 do_mask ? 0 : (1 << bitfield_width) - 1); 170 } 171 172 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) 173 { 174 /* The SENSE register is assumed to be 32-bit. */ 175 int bitfield_width = p->sense_bitfield_width; 176 int shift = 32 - (irq + 1) * bitfield_width; 177 178 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); 179 180 if (value >= (1 << bitfield_width)) 181 return -EINVAL; 182 183 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift, 184 bitfield_width, value); 185 return 0; 186 } 187 188 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) 189 { 190 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", 191 str, i->requested_irq, i->hw_irq, i->domain_irq); 192 } 193 194 static void intc_irqpin_irq_enable(struct irq_data *d) 195 { 196 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 197 int hw_irq = irqd_to_hwirq(d); 198 199 intc_irqpin_dbg(&p->irq[hw_irq], "enable"); 200 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); 201 } 202 203 static void intc_irqpin_irq_disable(struct irq_data *d) 204 { 205 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 206 int hw_irq = irqd_to_hwirq(d); 207 208 intc_irqpin_dbg(&p->irq[hw_irq], "disable"); 209 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); 210 } 211 212 static void intc_irqpin_shared_irq_enable(struct irq_data *d) 213 { 214 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 215 int hw_irq = irqd_to_hwirq(d); 216 217 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); 218 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); 219 220 p->shared_irq_mask &= ~BIT(hw_irq); 221 } 222 223 static void intc_irqpin_shared_irq_disable(struct irq_data *d) 224 { 225 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 226 int hw_irq = irqd_to_hwirq(d); 227 228 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); 229 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); 230 231 p->shared_irq_mask |= BIT(hw_irq); 232 } 233 234 static void intc_irqpin_irq_enable_force(struct irq_data *d) 235 { 236 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 237 int irq = p->irq[irqd_to_hwirq(d)].requested_irq; 238 239 intc_irqpin_irq_enable(d); 240 241 /* enable interrupt through parent interrupt controller, 242 * assumes non-shared interrupt with 1:1 mapping 243 * needed for busted IRQs on some SoCs like sh73a0 244 */ 245 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); 246 } 247 248 static void intc_irqpin_irq_disable_force(struct irq_data *d) 249 { 250 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 251 int irq = p->irq[irqd_to_hwirq(d)].requested_irq; 252 253 /* disable interrupt through parent interrupt controller, 254 * assumes non-shared interrupt with 1:1 mapping 255 * needed for busted IRQs on some SoCs like sh73a0 256 */ 257 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); 258 intc_irqpin_irq_disable(d); 259 } 260 261 #define INTC_IRQ_SENSE_VALID 0x10 262 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) 263 264 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = { 265 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00), 266 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01), 267 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02), 268 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03), 269 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04), 270 }; 271 272 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type) 273 { 274 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK]; 275 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 276 277 if (!(value & INTC_IRQ_SENSE_VALID)) 278 return -EINVAL; 279 280 return intc_irqpin_set_sense(p, irqd_to_hwirq(d), 281 value ^ INTC_IRQ_SENSE_VALID); 282 } 283 284 static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on) 285 { 286 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 287 int hw_irq = irqd_to_hwirq(d); 288 289 irq_set_irq_wake(p->irq[hw_irq].requested_irq, on); 290 291 if (!p->clk) 292 return 0; 293 294 if (on) 295 clk_enable(p->clk); 296 else 297 clk_disable(p->clk); 298 299 return 0; 300 } 301 302 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) 303 { 304 struct intc_irqpin_irq *i = dev_id; 305 struct intc_irqpin_priv *p = i->p; 306 unsigned long bit; 307 308 intc_irqpin_dbg(i, "demux1"); 309 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq); 310 311 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { 312 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); 313 intc_irqpin_dbg(i, "demux2"); 314 generic_handle_irq(i->domain_irq); 315 return IRQ_HANDLED; 316 } 317 return IRQ_NONE; 318 } 319 320 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) 321 { 322 struct intc_irqpin_priv *p = dev_id; 323 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); 324 irqreturn_t status = IRQ_NONE; 325 int k; 326 327 for (k = 0; k < 8; k++) { 328 if (reg_source & BIT(7 - k)) { 329 if (BIT(k) & p->shared_irq_mask) 330 continue; 331 332 status |= intc_irqpin_irq_handler(irq, &p->irq[k]); 333 } 334 } 335 336 return status; 337 } 338 339 /* 340 * This lock class tells lockdep that INTC External IRQ Pin irqs are in a 341 * different category than their parents, so it won't report false recursion. 342 */ 343 static struct lock_class_key intc_irqpin_irq_lock_class; 344 345 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, 346 irq_hw_number_t hw) 347 { 348 struct intc_irqpin_priv *p = h->host_data; 349 350 p->irq[hw].domain_irq = virq; 351 p->irq[hw].hw_irq = hw; 352 353 intc_irqpin_dbg(&p->irq[hw], "map"); 354 irq_set_chip_data(virq, h->host_data); 355 irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class); 356 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); 357 return 0; 358 } 359 360 static const struct irq_domain_ops intc_irqpin_irq_domain_ops = { 361 .map = intc_irqpin_irq_domain_map, 362 .xlate = irq_domain_xlate_twocell, 363 }; 364 365 static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = { 366 .irlm_bit = 23, /* ICR0.IRLM0 */ 367 .needs_irlm = 1, 368 .needs_clk = 0, 369 }; 370 371 static const struct intc_irqpin_config intc_irqpin_rmobile = { 372 .needs_irlm = 0, 373 .needs_clk = 1, 374 }; 375 376 static const struct of_device_id intc_irqpin_dt_ids[] = { 377 { .compatible = "renesas,intc-irqpin", }, 378 { .compatible = "renesas,intc-irqpin-r8a7778", 379 .data = &intc_irqpin_irlm_r8a777x }, 380 { .compatible = "renesas,intc-irqpin-r8a7779", 381 .data = &intc_irqpin_irlm_r8a777x }, 382 { .compatible = "renesas,intc-irqpin-r8a7740", 383 .data = &intc_irqpin_rmobile }, 384 { .compatible = "renesas,intc-irqpin-sh73a0", 385 .data = &intc_irqpin_rmobile }, 386 {}, 387 }; 388 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); 389 390 static int intc_irqpin_probe(struct platform_device *pdev) 391 { 392 const struct intc_irqpin_config *config = NULL; 393 struct device *dev = &pdev->dev; 394 const struct of_device_id *of_id; 395 struct intc_irqpin_priv *p; 396 struct intc_irqpin_iomem *i; 397 struct resource *io[INTC_IRQPIN_REG_NR]; 398 struct resource *irq; 399 struct irq_chip *irq_chip; 400 void (*enable_fn)(struct irq_data *d); 401 void (*disable_fn)(struct irq_data *d); 402 const char *name = dev_name(dev); 403 bool control_parent; 404 unsigned int nirqs; 405 int ref_irq; 406 int ret; 407 int k; 408 409 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); 410 if (!p) { 411 dev_err(dev, "failed to allocate driver data\n"); 412 return -ENOMEM; 413 } 414 415 /* deal with driver instance configuration */ 416 of_property_read_u32(dev->of_node, "sense-bitfield-width", 417 &p->sense_bitfield_width); 418 control_parent = of_property_read_bool(dev->of_node, "control-parent"); 419 if (!p->sense_bitfield_width) 420 p->sense_bitfield_width = 4; /* default to 4 bits */ 421 422 p->pdev = pdev; 423 platform_set_drvdata(pdev, p); 424 425 of_id = of_match_device(intc_irqpin_dt_ids, dev); 426 if (of_id && of_id->data) { 427 config = of_id->data; 428 p->needs_clk = config->needs_clk; 429 } 430 431 p->clk = devm_clk_get(dev, NULL); 432 if (IS_ERR(p->clk)) { 433 if (p->needs_clk) { 434 dev_err(dev, "unable to get clock\n"); 435 ret = PTR_ERR(p->clk); 436 goto err0; 437 } 438 p->clk = NULL; 439 } 440 441 pm_runtime_enable(dev); 442 pm_runtime_get_sync(dev); 443 444 /* get hold of register banks */ 445 memset(io, 0, sizeof(io)); 446 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { 447 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); 448 if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) { 449 dev_err(dev, "not enough IOMEM resources\n"); 450 ret = -EINVAL; 451 goto err0; 452 } 453 } 454 455 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */ 456 for (k = 0; k < INTC_IRQPIN_MAX; k++) { 457 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); 458 if (!irq) 459 break; 460 461 p->irq[k].p = p; 462 p->irq[k].requested_irq = irq->start; 463 } 464 465 nirqs = k; 466 if (nirqs < 1) { 467 dev_err(dev, "not enough IRQ resources\n"); 468 ret = -EINVAL; 469 goto err0; 470 } 471 472 /* ioremap IOMEM and setup read/write callbacks */ 473 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { 474 i = &p->iomem[k]; 475 476 /* handle optional registers */ 477 if (!io[k]) 478 continue; 479 480 switch (resource_size(io[k])) { 481 case 1: 482 i->width = 8; 483 i->read = intc_irqpin_read8; 484 i->write = intc_irqpin_write8; 485 break; 486 case 4: 487 i->width = 32; 488 i->read = intc_irqpin_read32; 489 i->write = intc_irqpin_write32; 490 break; 491 default: 492 dev_err(dev, "IOMEM size mismatch\n"); 493 ret = -EINVAL; 494 goto err0; 495 } 496 497 i->iomem = devm_ioremap_nocache(dev, io[k]->start, 498 resource_size(io[k])); 499 if (!i->iomem) { 500 dev_err(dev, "failed to remap IOMEM\n"); 501 ret = -ENXIO; 502 goto err0; 503 } 504 } 505 506 /* configure "individual IRQ mode" where needed */ 507 if (config && config->needs_irlm) { 508 if (io[INTC_IRQPIN_REG_IRLM]) 509 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM, 510 config->irlm_bit, 1, 1); 511 else 512 dev_warn(dev, "unable to select IRLM mode\n"); 513 } 514 515 /* mask all interrupts using priority */ 516 for (k = 0; k < nirqs; k++) 517 intc_irqpin_mask_unmask_prio(p, k, 1); 518 519 /* clear all pending interrupts */ 520 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); 521 522 /* scan for shared interrupt lines */ 523 ref_irq = p->irq[0].requested_irq; 524 p->shared_irqs = 1; 525 for (k = 1; k < nirqs; k++) { 526 if (ref_irq != p->irq[k].requested_irq) { 527 p->shared_irqs = 0; 528 break; 529 } 530 } 531 532 /* use more severe masking method if requested */ 533 if (control_parent) { 534 enable_fn = intc_irqpin_irq_enable_force; 535 disable_fn = intc_irqpin_irq_disable_force; 536 } else if (!p->shared_irqs) { 537 enable_fn = intc_irqpin_irq_enable; 538 disable_fn = intc_irqpin_irq_disable; 539 } else { 540 enable_fn = intc_irqpin_shared_irq_enable; 541 disable_fn = intc_irqpin_shared_irq_disable; 542 } 543 544 irq_chip = &p->irq_chip; 545 irq_chip->name = name; 546 irq_chip->irq_mask = disable_fn; 547 irq_chip->irq_unmask = enable_fn; 548 irq_chip->irq_set_type = intc_irqpin_irq_set_type; 549 irq_chip->irq_set_wake = intc_irqpin_irq_set_wake; 550 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND; 551 552 p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0, 553 &intc_irqpin_irq_domain_ops, p); 554 if (!p->irq_domain) { 555 ret = -ENXIO; 556 dev_err(dev, "cannot initialize irq domain\n"); 557 goto err0; 558 } 559 560 if (p->shared_irqs) { 561 /* request one shared interrupt */ 562 if (devm_request_irq(dev, p->irq[0].requested_irq, 563 intc_irqpin_shared_irq_handler, 564 IRQF_SHARED, name, p)) { 565 dev_err(dev, "failed to request low IRQ\n"); 566 ret = -ENOENT; 567 goto err1; 568 } 569 } else { 570 /* request interrupts one by one */ 571 for (k = 0; k < nirqs; k++) { 572 if (devm_request_irq(dev, p->irq[k].requested_irq, 573 intc_irqpin_irq_handler, 0, name, 574 &p->irq[k])) { 575 dev_err(dev, "failed to request low IRQ\n"); 576 ret = -ENOENT; 577 goto err1; 578 } 579 } 580 } 581 582 /* unmask all interrupts on prio level */ 583 for (k = 0; k < nirqs; k++) 584 intc_irqpin_mask_unmask_prio(p, k, 0); 585 586 dev_info(dev, "driving %d irqs\n", nirqs); 587 588 return 0; 589 590 err1: 591 irq_domain_remove(p->irq_domain); 592 err0: 593 pm_runtime_put(dev); 594 pm_runtime_disable(dev); 595 return ret; 596 } 597 598 static int intc_irqpin_remove(struct platform_device *pdev) 599 { 600 struct intc_irqpin_priv *p = platform_get_drvdata(pdev); 601 602 irq_domain_remove(p->irq_domain); 603 pm_runtime_put(&pdev->dev); 604 pm_runtime_disable(&pdev->dev); 605 return 0; 606 } 607 608 static struct platform_driver intc_irqpin_device_driver = { 609 .probe = intc_irqpin_probe, 610 .remove = intc_irqpin_remove, 611 .driver = { 612 .name = "renesas_intc_irqpin", 613 .of_match_table = intc_irqpin_dt_ids, 614 } 615 }; 616 617 static int __init intc_irqpin_init(void) 618 { 619 return platform_driver_register(&intc_irqpin_device_driver); 620 } 621 postcore_initcall(intc_irqpin_init); 622 623 static void __exit intc_irqpin_exit(void) 624 { 625 platform_driver_unregister(&intc_irqpin_device_driver); 626 } 627 module_exit(intc_irqpin_exit); 628 629 MODULE_AUTHOR("Magnus Damm"); 630 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver"); 631 MODULE_LICENSE("GPL v2"); 632