1 /* 2 * Renesas INTC External IRQ Pin Driver 3 * 4 * Copyright (C) 2013 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/init.h> 21 #include <linux/platform_device.h> 22 #include <linux/spinlock.h> 23 #include <linux/interrupt.h> 24 #include <linux/ioport.h> 25 #include <linux/io.h> 26 #include <linux/irq.h> 27 #include <linux/irqdomain.h> 28 #include <linux/err.h> 29 #include <linux/slab.h> 30 #include <linux/module.h> 31 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 32 33 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */ 34 35 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */ 36 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */ 37 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */ 38 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */ 39 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */ 40 #define INTC_IRQPIN_REG_NR 5 41 42 /* INTC external IRQ PIN hardware register access: 43 * 44 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*) 45 * PRIO is read-write 32-bit with 4-bits per IRQ (**) 46 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***) 47 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 48 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 49 * 50 * (*) May be accessed by more than one driver instance - lock needed 51 * (**) Read-modify-write access by one driver instance - lock needed 52 * (***) Accessed by one driver instance only - no locking needed 53 */ 54 55 struct intc_irqpin_iomem { 56 void __iomem *iomem; 57 unsigned long (*read)(void __iomem *iomem); 58 void (*write)(void __iomem *iomem, unsigned long data); 59 int width; 60 }; 61 62 struct intc_irqpin_irq { 63 int hw_irq; 64 int requested_irq; 65 int domain_irq; 66 struct intc_irqpin_priv *p; 67 }; 68 69 struct intc_irqpin_priv { 70 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; 71 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX]; 72 struct renesas_intc_irqpin_config config; 73 unsigned int number_of_irqs; 74 struct platform_device *pdev; 75 struct irq_chip irq_chip; 76 struct irq_domain *irq_domain; 77 bool shared_irqs; 78 u8 shared_irq_mask; 79 }; 80 81 static unsigned long intc_irqpin_read32(void __iomem *iomem) 82 { 83 return ioread32(iomem); 84 } 85 86 static unsigned long intc_irqpin_read8(void __iomem *iomem) 87 { 88 return ioread8(iomem); 89 } 90 91 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data) 92 { 93 iowrite32(data, iomem); 94 } 95 96 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data) 97 { 98 iowrite8(data, iomem); 99 } 100 101 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, 102 int reg) 103 { 104 struct intc_irqpin_iomem *i = &p->iomem[reg]; 105 106 return i->read(i->iomem); 107 } 108 109 static inline void intc_irqpin_write(struct intc_irqpin_priv *p, 110 int reg, unsigned long data) 111 { 112 struct intc_irqpin_iomem *i = &p->iomem[reg]; 113 114 i->write(i->iomem, data); 115 } 116 117 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p, 118 int reg, int hw_irq) 119 { 120 return BIT((p->iomem[reg].width - 1) - hw_irq); 121 } 122 123 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p, 124 int reg, int hw_irq) 125 { 126 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); 127 } 128 129 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */ 130 131 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, 132 int reg, int shift, 133 int width, int value) 134 { 135 unsigned long flags; 136 unsigned long tmp; 137 138 raw_spin_lock_irqsave(&intc_irqpin_lock, flags); 139 140 tmp = intc_irqpin_read(p, reg); 141 tmp &= ~(((1 << width) - 1) << shift); 142 tmp |= value << shift; 143 intc_irqpin_write(p, reg, tmp); 144 145 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags); 146 } 147 148 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, 149 int irq, int do_mask) 150 { 151 int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ 152 int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ 153 154 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, 155 shift, bitfield_width, 156 do_mask ? 0 : (1 << bitfield_width) - 1); 157 } 158 159 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) 160 { 161 int bitfield_width = p->config.sense_bitfield_width; 162 int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ 163 164 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); 165 166 if (value >= (1 << bitfield_width)) 167 return -EINVAL; 168 169 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift, 170 bitfield_width, value); 171 return 0; 172 } 173 174 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) 175 { 176 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", 177 str, i->requested_irq, i->hw_irq, i->domain_irq); 178 } 179 180 static void intc_irqpin_irq_enable(struct irq_data *d) 181 { 182 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 183 int hw_irq = irqd_to_hwirq(d); 184 185 intc_irqpin_dbg(&p->irq[hw_irq], "enable"); 186 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); 187 } 188 189 static void intc_irqpin_irq_disable(struct irq_data *d) 190 { 191 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 192 int hw_irq = irqd_to_hwirq(d); 193 194 intc_irqpin_dbg(&p->irq[hw_irq], "disable"); 195 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); 196 } 197 198 static void intc_irqpin_shared_irq_enable(struct irq_data *d) 199 { 200 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 201 int hw_irq = irqd_to_hwirq(d); 202 203 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); 204 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); 205 206 p->shared_irq_mask &= ~BIT(hw_irq); 207 } 208 209 static void intc_irqpin_shared_irq_disable(struct irq_data *d) 210 { 211 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 212 int hw_irq = irqd_to_hwirq(d); 213 214 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); 215 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); 216 217 p->shared_irq_mask |= BIT(hw_irq); 218 } 219 220 static void intc_irqpin_irq_enable_force(struct irq_data *d) 221 { 222 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 223 int irq = p->irq[irqd_to_hwirq(d)].requested_irq; 224 225 intc_irqpin_irq_enable(d); 226 227 /* enable interrupt through parent interrupt controller, 228 * assumes non-shared interrupt with 1:1 mapping 229 * needed for busted IRQs on some SoCs like sh73a0 230 */ 231 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); 232 } 233 234 static void intc_irqpin_irq_disable_force(struct irq_data *d) 235 { 236 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 237 int irq = p->irq[irqd_to_hwirq(d)].requested_irq; 238 239 /* disable interrupt through parent interrupt controller, 240 * assumes non-shared interrupt with 1:1 mapping 241 * needed for busted IRQs on some SoCs like sh73a0 242 */ 243 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); 244 intc_irqpin_irq_disable(d); 245 } 246 247 #define INTC_IRQ_SENSE_VALID 0x10 248 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) 249 250 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = { 251 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00), 252 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01), 253 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02), 254 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03), 255 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04), 256 }; 257 258 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type) 259 { 260 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK]; 261 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 262 263 if (!(value & INTC_IRQ_SENSE_VALID)) 264 return -EINVAL; 265 266 return intc_irqpin_set_sense(p, irqd_to_hwirq(d), 267 value ^ INTC_IRQ_SENSE_VALID); 268 } 269 270 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) 271 { 272 struct intc_irqpin_irq *i = dev_id; 273 struct intc_irqpin_priv *p = i->p; 274 unsigned long bit; 275 276 intc_irqpin_dbg(i, "demux1"); 277 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq); 278 279 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { 280 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); 281 intc_irqpin_dbg(i, "demux2"); 282 generic_handle_irq(i->domain_irq); 283 return IRQ_HANDLED; 284 } 285 return IRQ_NONE; 286 } 287 288 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) 289 { 290 struct intc_irqpin_priv *p = dev_id; 291 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); 292 irqreturn_t status = IRQ_NONE; 293 int k; 294 295 for (k = 0; k < 8; k++) { 296 if (reg_source & BIT(7 - k)) { 297 if (BIT(k) & p->shared_irq_mask) 298 continue; 299 300 status |= intc_irqpin_irq_handler(irq, &p->irq[k]); 301 } 302 } 303 304 return status; 305 } 306 307 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, 308 irq_hw_number_t hw) 309 { 310 struct intc_irqpin_priv *p = h->host_data; 311 312 p->irq[hw].domain_irq = virq; 313 p->irq[hw].hw_irq = hw; 314 315 intc_irqpin_dbg(&p->irq[hw], "map"); 316 irq_set_chip_data(virq, h->host_data); 317 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); 318 set_irq_flags(virq, IRQF_VALID); /* kill me now */ 319 return 0; 320 } 321 322 static struct irq_domain_ops intc_irqpin_irq_domain_ops = { 323 .map = intc_irqpin_irq_domain_map, 324 .xlate = irq_domain_xlate_twocell, 325 }; 326 327 static int intc_irqpin_probe(struct platform_device *pdev) 328 { 329 struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data; 330 struct intc_irqpin_priv *p; 331 struct intc_irqpin_iomem *i; 332 struct resource *io[INTC_IRQPIN_REG_NR]; 333 struct resource *irq; 334 struct irq_chip *irq_chip; 335 void (*enable_fn)(struct irq_data *d); 336 void (*disable_fn)(struct irq_data *d); 337 const char *name = dev_name(&pdev->dev); 338 int ref_irq; 339 int ret; 340 int k; 341 342 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); 343 if (!p) { 344 dev_err(&pdev->dev, "failed to allocate driver data\n"); 345 ret = -ENOMEM; 346 goto err0; 347 } 348 349 /* deal with driver instance configuration */ 350 if (pdata) 351 memcpy(&p->config, pdata, sizeof(*pdata)); 352 if (!p->config.sense_bitfield_width) 353 p->config.sense_bitfield_width = 4; /* default to 4 bits */ 354 355 p->pdev = pdev; 356 platform_set_drvdata(pdev, p); 357 358 /* get hold of manadatory IOMEM */ 359 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { 360 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); 361 if (!io[k]) { 362 dev_err(&pdev->dev, "not enough IOMEM resources\n"); 363 ret = -EINVAL; 364 goto err0; 365 } 366 } 367 368 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */ 369 for (k = 0; k < INTC_IRQPIN_MAX; k++) { 370 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); 371 if (!irq) 372 break; 373 374 p->irq[k].p = p; 375 p->irq[k].requested_irq = irq->start; 376 } 377 378 p->number_of_irqs = k; 379 if (p->number_of_irqs < 1) { 380 dev_err(&pdev->dev, "not enough IRQ resources\n"); 381 ret = -EINVAL; 382 goto err0; 383 } 384 385 /* ioremap IOMEM and setup read/write callbacks */ 386 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { 387 i = &p->iomem[k]; 388 389 switch (resource_size(io[k])) { 390 case 1: 391 i->width = 8; 392 i->read = intc_irqpin_read8; 393 i->write = intc_irqpin_write8; 394 break; 395 case 4: 396 i->width = 32; 397 i->read = intc_irqpin_read32; 398 i->write = intc_irqpin_write32; 399 break; 400 default: 401 dev_err(&pdev->dev, "IOMEM size mismatch\n"); 402 ret = -EINVAL; 403 goto err0; 404 } 405 406 i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start, 407 resource_size(io[k])); 408 if (!i->iomem) { 409 dev_err(&pdev->dev, "failed to remap IOMEM\n"); 410 ret = -ENXIO; 411 goto err0; 412 } 413 } 414 415 /* mask all interrupts using priority */ 416 for (k = 0; k < p->number_of_irqs; k++) 417 intc_irqpin_mask_unmask_prio(p, k, 1); 418 419 /* clear all pending interrupts */ 420 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); 421 422 /* scan for shared interrupt lines */ 423 ref_irq = p->irq[0].requested_irq; 424 p->shared_irqs = true; 425 for (k = 1; k < p->number_of_irqs; k++) { 426 if (ref_irq != p->irq[k].requested_irq) { 427 p->shared_irqs = false; 428 break; 429 } 430 } 431 432 /* use more severe masking method if requested */ 433 if (p->config.control_parent) { 434 enable_fn = intc_irqpin_irq_enable_force; 435 disable_fn = intc_irqpin_irq_disable_force; 436 } else if (!p->shared_irqs) { 437 enable_fn = intc_irqpin_irq_enable; 438 disable_fn = intc_irqpin_irq_disable; 439 } else { 440 enable_fn = intc_irqpin_shared_irq_enable; 441 disable_fn = intc_irqpin_shared_irq_disable; 442 } 443 444 irq_chip = &p->irq_chip; 445 irq_chip->name = name; 446 irq_chip->irq_mask = disable_fn; 447 irq_chip->irq_unmask = enable_fn; 448 irq_chip->irq_enable = enable_fn; 449 irq_chip->irq_disable = disable_fn; 450 irq_chip->irq_set_type = intc_irqpin_irq_set_type; 451 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; 452 453 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 454 p->number_of_irqs, 455 p->config.irq_base, 456 &intc_irqpin_irq_domain_ops, p); 457 if (!p->irq_domain) { 458 ret = -ENXIO; 459 dev_err(&pdev->dev, "cannot initialize irq domain\n"); 460 goto err0; 461 } 462 463 if (p->shared_irqs) { 464 /* request one shared interrupt */ 465 if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq, 466 intc_irqpin_shared_irq_handler, 467 IRQF_SHARED, name, p)) { 468 dev_err(&pdev->dev, "failed to request low IRQ\n"); 469 ret = -ENOENT; 470 goto err1; 471 } 472 } else { 473 /* request interrupts one by one */ 474 for (k = 0; k < p->number_of_irqs; k++) { 475 if (devm_request_irq(&pdev->dev, 476 p->irq[k].requested_irq, 477 intc_irqpin_irq_handler, 478 0, name, &p->irq[k])) { 479 dev_err(&pdev->dev, 480 "failed to request low IRQ\n"); 481 ret = -ENOENT; 482 goto err1; 483 } 484 } 485 } 486 487 /* unmask all interrupts on prio level */ 488 for (k = 0; k < p->number_of_irqs; k++) 489 intc_irqpin_mask_unmask_prio(p, k, 0); 490 491 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); 492 493 /* warn in case of mismatch if irq base is specified */ 494 if (p->config.irq_base) { 495 if (p->config.irq_base != p->irq[0].domain_irq) 496 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", 497 p->config.irq_base, p->irq[0].domain_irq); 498 } 499 500 return 0; 501 502 err1: 503 irq_domain_remove(p->irq_domain); 504 err0: 505 return ret; 506 } 507 508 static int intc_irqpin_remove(struct platform_device *pdev) 509 { 510 struct intc_irqpin_priv *p = platform_get_drvdata(pdev); 511 512 irq_domain_remove(p->irq_domain); 513 514 return 0; 515 } 516 517 static const struct of_device_id intc_irqpin_dt_ids[] = { 518 { .compatible = "renesas,intc-irqpin", }, 519 {}, 520 }; 521 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); 522 523 static struct platform_driver intc_irqpin_device_driver = { 524 .probe = intc_irqpin_probe, 525 .remove = intc_irqpin_remove, 526 .driver = { 527 .name = "renesas_intc_irqpin", 528 .of_match_table = intc_irqpin_dt_ids, 529 .owner = THIS_MODULE, 530 } 531 }; 532 533 static int __init intc_irqpin_init(void) 534 { 535 return platform_driver_register(&intc_irqpin_device_driver); 536 } 537 postcore_initcall(intc_irqpin_init); 538 539 static void __exit intc_irqpin_exit(void) 540 { 541 platform_driver_unregister(&intc_irqpin_device_driver); 542 } 543 module_exit(intc_irqpin_exit); 544 545 MODULE_AUTHOR("Magnus Damm"); 546 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver"); 547 MODULE_LICENSE("GPL v2"); 548