1 /* 2 * Renesas INTC External IRQ Pin Driver 3 * 4 * Copyright (C) 2013 Magnus Damm 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 18 */ 19 20 #include <linux/init.h> 21 #include <linux/of.h> 22 #include <linux/platform_device.h> 23 #include <linux/spinlock.h> 24 #include <linux/interrupt.h> 25 #include <linux/ioport.h> 26 #include <linux/io.h> 27 #include <linux/irq.h> 28 #include <linux/irqdomain.h> 29 #include <linux/err.h> 30 #include <linux/slab.h> 31 #include <linux/module.h> 32 #include <linux/platform_data/irq-renesas-intc-irqpin.h> 33 34 #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */ 35 36 #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */ 37 #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */ 38 #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */ 39 #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */ 40 #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */ 41 #define INTC_IRQPIN_REG_NR 5 42 43 /* INTC external IRQ PIN hardware register access: 44 * 45 * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*) 46 * PRIO is read-write 32-bit with 4-bits per IRQ (**) 47 * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***) 48 * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 49 * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 50 * 51 * (*) May be accessed by more than one driver instance - lock needed 52 * (**) Read-modify-write access by one driver instance - lock needed 53 * (***) Accessed by one driver instance only - no locking needed 54 */ 55 56 struct intc_irqpin_iomem { 57 void __iomem *iomem; 58 unsigned long (*read)(void __iomem *iomem); 59 void (*write)(void __iomem *iomem, unsigned long data); 60 int width; 61 }; 62 63 struct intc_irqpin_irq { 64 int hw_irq; 65 int requested_irq; 66 int domain_irq; 67 struct intc_irqpin_priv *p; 68 }; 69 70 struct intc_irqpin_priv { 71 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; 72 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX]; 73 struct renesas_intc_irqpin_config config; 74 unsigned int number_of_irqs; 75 struct platform_device *pdev; 76 struct irq_chip irq_chip; 77 struct irq_domain *irq_domain; 78 bool shared_irqs; 79 u8 shared_irq_mask; 80 }; 81 82 static unsigned long intc_irqpin_read32(void __iomem *iomem) 83 { 84 return ioread32(iomem); 85 } 86 87 static unsigned long intc_irqpin_read8(void __iomem *iomem) 88 { 89 return ioread8(iomem); 90 } 91 92 static void intc_irqpin_write32(void __iomem *iomem, unsigned long data) 93 { 94 iowrite32(data, iomem); 95 } 96 97 static void intc_irqpin_write8(void __iomem *iomem, unsigned long data) 98 { 99 iowrite8(data, iomem); 100 } 101 102 static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, 103 int reg) 104 { 105 struct intc_irqpin_iomem *i = &p->iomem[reg]; 106 107 return i->read(i->iomem); 108 } 109 110 static inline void intc_irqpin_write(struct intc_irqpin_priv *p, 111 int reg, unsigned long data) 112 { 113 struct intc_irqpin_iomem *i = &p->iomem[reg]; 114 115 i->write(i->iomem, data); 116 } 117 118 static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p, 119 int reg, int hw_irq) 120 { 121 return BIT((p->iomem[reg].width - 1) - hw_irq); 122 } 123 124 static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p, 125 int reg, int hw_irq) 126 { 127 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); 128 } 129 130 static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */ 131 132 static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, 133 int reg, int shift, 134 int width, int value) 135 { 136 unsigned long flags; 137 unsigned long tmp; 138 139 raw_spin_lock_irqsave(&intc_irqpin_lock, flags); 140 141 tmp = intc_irqpin_read(p, reg); 142 tmp &= ~(((1 << width) - 1) << shift); 143 tmp |= value << shift; 144 intc_irqpin_write(p, reg, tmp); 145 146 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags); 147 } 148 149 static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, 150 int irq, int do_mask) 151 { 152 int bitfield_width = 4; /* PRIO assumed to have fixed bitfield width */ 153 int shift = (7 - irq) * bitfield_width; /* PRIO assumed to be 32-bit */ 154 155 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, 156 shift, bitfield_width, 157 do_mask ? 0 : (1 << bitfield_width) - 1); 158 } 159 160 static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) 161 { 162 int bitfield_width = p->config.sense_bitfield_width; 163 int shift = (7 - irq) * bitfield_width; /* SENSE assumed to be 32-bit */ 164 165 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); 166 167 if (value >= (1 << bitfield_width)) 168 return -EINVAL; 169 170 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift, 171 bitfield_width, value); 172 return 0; 173 } 174 175 static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) 176 { 177 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", 178 str, i->requested_irq, i->hw_irq, i->domain_irq); 179 } 180 181 static void intc_irqpin_irq_enable(struct irq_data *d) 182 { 183 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 184 int hw_irq = irqd_to_hwirq(d); 185 186 intc_irqpin_dbg(&p->irq[hw_irq], "enable"); 187 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); 188 } 189 190 static void intc_irqpin_irq_disable(struct irq_data *d) 191 { 192 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 193 int hw_irq = irqd_to_hwirq(d); 194 195 intc_irqpin_dbg(&p->irq[hw_irq], "disable"); 196 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); 197 } 198 199 static void intc_irqpin_shared_irq_enable(struct irq_data *d) 200 { 201 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 202 int hw_irq = irqd_to_hwirq(d); 203 204 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); 205 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); 206 207 p->shared_irq_mask &= ~BIT(hw_irq); 208 } 209 210 static void intc_irqpin_shared_irq_disable(struct irq_data *d) 211 { 212 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 213 int hw_irq = irqd_to_hwirq(d); 214 215 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); 216 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); 217 218 p->shared_irq_mask |= BIT(hw_irq); 219 } 220 221 static void intc_irqpin_irq_enable_force(struct irq_data *d) 222 { 223 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 224 int irq = p->irq[irqd_to_hwirq(d)].requested_irq; 225 226 intc_irqpin_irq_enable(d); 227 228 /* enable interrupt through parent interrupt controller, 229 * assumes non-shared interrupt with 1:1 mapping 230 * needed for busted IRQs on some SoCs like sh73a0 231 */ 232 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); 233 } 234 235 static void intc_irqpin_irq_disable_force(struct irq_data *d) 236 { 237 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 238 int irq = p->irq[irqd_to_hwirq(d)].requested_irq; 239 240 /* disable interrupt through parent interrupt controller, 241 * assumes non-shared interrupt with 1:1 mapping 242 * needed for busted IRQs on some SoCs like sh73a0 243 */ 244 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); 245 intc_irqpin_irq_disable(d); 246 } 247 248 #define INTC_IRQ_SENSE_VALID 0x10 249 #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) 250 251 static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = { 252 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00), 253 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01), 254 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02), 255 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03), 256 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04), 257 }; 258 259 static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type) 260 { 261 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK]; 262 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 263 264 if (!(value & INTC_IRQ_SENSE_VALID)) 265 return -EINVAL; 266 267 return intc_irqpin_set_sense(p, irqd_to_hwirq(d), 268 value ^ INTC_IRQ_SENSE_VALID); 269 } 270 271 static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) 272 { 273 struct intc_irqpin_irq *i = dev_id; 274 struct intc_irqpin_priv *p = i->p; 275 unsigned long bit; 276 277 intc_irqpin_dbg(i, "demux1"); 278 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq); 279 280 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { 281 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); 282 intc_irqpin_dbg(i, "demux2"); 283 generic_handle_irq(i->domain_irq); 284 return IRQ_HANDLED; 285 } 286 return IRQ_NONE; 287 } 288 289 static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) 290 { 291 struct intc_irqpin_priv *p = dev_id; 292 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); 293 irqreturn_t status = IRQ_NONE; 294 int k; 295 296 for (k = 0; k < 8; k++) { 297 if (reg_source & BIT(7 - k)) { 298 if (BIT(k) & p->shared_irq_mask) 299 continue; 300 301 status |= intc_irqpin_irq_handler(irq, &p->irq[k]); 302 } 303 } 304 305 return status; 306 } 307 308 static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, 309 irq_hw_number_t hw) 310 { 311 struct intc_irqpin_priv *p = h->host_data; 312 313 p->irq[hw].domain_irq = virq; 314 p->irq[hw].hw_irq = hw; 315 316 intc_irqpin_dbg(&p->irq[hw], "map"); 317 irq_set_chip_data(virq, h->host_data); 318 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); 319 set_irq_flags(virq, IRQF_VALID); /* kill me now */ 320 return 0; 321 } 322 323 static struct irq_domain_ops intc_irqpin_irq_domain_ops = { 324 .map = intc_irqpin_irq_domain_map, 325 .xlate = irq_domain_xlate_twocell, 326 }; 327 328 static int intc_irqpin_probe(struct platform_device *pdev) 329 { 330 struct renesas_intc_irqpin_config *pdata = pdev->dev.platform_data; 331 struct intc_irqpin_priv *p; 332 struct intc_irqpin_iomem *i; 333 struct resource *io[INTC_IRQPIN_REG_NR]; 334 struct resource *irq; 335 struct irq_chip *irq_chip; 336 void (*enable_fn)(struct irq_data *d); 337 void (*disable_fn)(struct irq_data *d); 338 const char *name = dev_name(&pdev->dev); 339 int ref_irq; 340 int ret; 341 int k; 342 343 p = devm_kzalloc(&pdev->dev, sizeof(*p), GFP_KERNEL); 344 if (!p) { 345 dev_err(&pdev->dev, "failed to allocate driver data\n"); 346 ret = -ENOMEM; 347 goto err0; 348 } 349 350 /* deal with driver instance configuration */ 351 if (pdata) { 352 memcpy(&p->config, pdata, sizeof(*pdata)); 353 } else { 354 of_property_read_u32(pdev->dev.of_node, "sense-bitfield-width", 355 &p->config.sense_bitfield_width); 356 p->config.control_parent = of_property_read_bool(pdev->dev.of_node, 357 "control-parent"); 358 } 359 if (!p->config.sense_bitfield_width) 360 p->config.sense_bitfield_width = 4; /* default to 4 bits */ 361 362 p->pdev = pdev; 363 platform_set_drvdata(pdev, p); 364 365 /* get hold of manadatory IOMEM */ 366 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { 367 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); 368 if (!io[k]) { 369 dev_err(&pdev->dev, "not enough IOMEM resources\n"); 370 ret = -EINVAL; 371 goto err0; 372 } 373 } 374 375 /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */ 376 for (k = 0; k < INTC_IRQPIN_MAX; k++) { 377 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); 378 if (!irq) 379 break; 380 381 p->irq[k].p = p; 382 p->irq[k].requested_irq = irq->start; 383 } 384 385 p->number_of_irqs = k; 386 if (p->number_of_irqs < 1) { 387 dev_err(&pdev->dev, "not enough IRQ resources\n"); 388 ret = -EINVAL; 389 goto err0; 390 } 391 392 /* ioremap IOMEM and setup read/write callbacks */ 393 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { 394 i = &p->iomem[k]; 395 396 switch (resource_size(io[k])) { 397 case 1: 398 i->width = 8; 399 i->read = intc_irqpin_read8; 400 i->write = intc_irqpin_write8; 401 break; 402 case 4: 403 i->width = 32; 404 i->read = intc_irqpin_read32; 405 i->write = intc_irqpin_write32; 406 break; 407 default: 408 dev_err(&pdev->dev, "IOMEM size mismatch\n"); 409 ret = -EINVAL; 410 goto err0; 411 } 412 413 i->iomem = devm_ioremap_nocache(&pdev->dev, io[k]->start, 414 resource_size(io[k])); 415 if (!i->iomem) { 416 dev_err(&pdev->dev, "failed to remap IOMEM\n"); 417 ret = -ENXIO; 418 goto err0; 419 } 420 } 421 422 /* mask all interrupts using priority */ 423 for (k = 0; k < p->number_of_irqs; k++) 424 intc_irqpin_mask_unmask_prio(p, k, 1); 425 426 /* clear all pending interrupts */ 427 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); 428 429 /* scan for shared interrupt lines */ 430 ref_irq = p->irq[0].requested_irq; 431 p->shared_irqs = true; 432 for (k = 1; k < p->number_of_irqs; k++) { 433 if (ref_irq != p->irq[k].requested_irq) { 434 p->shared_irqs = false; 435 break; 436 } 437 } 438 439 /* use more severe masking method if requested */ 440 if (p->config.control_parent) { 441 enable_fn = intc_irqpin_irq_enable_force; 442 disable_fn = intc_irqpin_irq_disable_force; 443 } else if (!p->shared_irqs) { 444 enable_fn = intc_irqpin_irq_enable; 445 disable_fn = intc_irqpin_irq_disable; 446 } else { 447 enable_fn = intc_irqpin_shared_irq_enable; 448 disable_fn = intc_irqpin_shared_irq_disable; 449 } 450 451 irq_chip = &p->irq_chip; 452 irq_chip->name = name; 453 irq_chip->irq_mask = disable_fn; 454 irq_chip->irq_unmask = enable_fn; 455 irq_chip->irq_enable = enable_fn; 456 irq_chip->irq_disable = disable_fn; 457 irq_chip->irq_set_type = intc_irqpin_irq_set_type; 458 irq_chip->flags = IRQCHIP_SKIP_SET_WAKE; 459 460 p->irq_domain = irq_domain_add_simple(pdev->dev.of_node, 461 p->number_of_irqs, 462 p->config.irq_base, 463 &intc_irqpin_irq_domain_ops, p); 464 if (!p->irq_domain) { 465 ret = -ENXIO; 466 dev_err(&pdev->dev, "cannot initialize irq domain\n"); 467 goto err0; 468 } 469 470 if (p->shared_irqs) { 471 /* request one shared interrupt */ 472 if (devm_request_irq(&pdev->dev, p->irq[0].requested_irq, 473 intc_irqpin_shared_irq_handler, 474 IRQF_SHARED, name, p)) { 475 dev_err(&pdev->dev, "failed to request low IRQ\n"); 476 ret = -ENOENT; 477 goto err1; 478 } 479 } else { 480 /* request interrupts one by one */ 481 for (k = 0; k < p->number_of_irqs; k++) { 482 if (devm_request_irq(&pdev->dev, 483 p->irq[k].requested_irq, 484 intc_irqpin_irq_handler, 485 0, name, &p->irq[k])) { 486 dev_err(&pdev->dev, 487 "failed to request low IRQ\n"); 488 ret = -ENOENT; 489 goto err1; 490 } 491 } 492 } 493 494 /* unmask all interrupts on prio level */ 495 for (k = 0; k < p->number_of_irqs; k++) 496 intc_irqpin_mask_unmask_prio(p, k, 0); 497 498 dev_info(&pdev->dev, "driving %d irqs\n", p->number_of_irqs); 499 500 /* warn in case of mismatch if irq base is specified */ 501 if (p->config.irq_base) { 502 if (p->config.irq_base != p->irq[0].domain_irq) 503 dev_warn(&pdev->dev, "irq base mismatch (%d/%d)\n", 504 p->config.irq_base, p->irq[0].domain_irq); 505 } 506 507 return 0; 508 509 err1: 510 irq_domain_remove(p->irq_domain); 511 err0: 512 return ret; 513 } 514 515 static int intc_irqpin_remove(struct platform_device *pdev) 516 { 517 struct intc_irqpin_priv *p = platform_get_drvdata(pdev); 518 519 irq_domain_remove(p->irq_domain); 520 521 return 0; 522 } 523 524 static const struct of_device_id intc_irqpin_dt_ids[] = { 525 { .compatible = "renesas,intc-irqpin", }, 526 {}, 527 }; 528 MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); 529 530 static struct platform_driver intc_irqpin_device_driver = { 531 .probe = intc_irqpin_probe, 532 .remove = intc_irqpin_remove, 533 .driver = { 534 .name = "renesas_intc_irqpin", 535 .of_match_table = intc_irqpin_dt_ids, 536 .owner = THIS_MODULE, 537 } 538 }; 539 540 static int __init intc_irqpin_init(void) 541 { 542 return platform_driver_register(&intc_irqpin_device_driver); 543 } 544 postcore_initcall(intc_irqpin_init); 545 546 static void __exit intc_irqpin_exit(void) 547 { 548 platform_driver_unregister(&intc_irqpin_device_driver); 549 } 550 module_exit(intc_irqpin_exit); 551 552 MODULE_AUTHOR("Magnus Damm"); 553 MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver"); 554 MODULE_LICENSE("GPL v2"); 555