144358048SMagnus Damm /* 244358048SMagnus Damm * Renesas INTC External IRQ Pin Driver 344358048SMagnus Damm * 444358048SMagnus Damm * Copyright (C) 2013 Magnus Damm 544358048SMagnus Damm * 644358048SMagnus Damm * This program is free software; you can redistribute it and/or modify 744358048SMagnus Damm * it under the terms of the GNU General Public License as published by 844358048SMagnus Damm * the Free Software Foundation; either version 2 of the License 944358048SMagnus Damm * 1044358048SMagnus Damm * This program is distributed in the hope that it will be useful, 1144358048SMagnus Damm * but WITHOUT ANY WARRANTY; without even the implied warranty of 1244358048SMagnus Damm * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1344358048SMagnus Damm * GNU General Public License for more details. 1444358048SMagnus Damm * 1544358048SMagnus Damm * You should have received a copy of the GNU General Public License 1644358048SMagnus Damm * along with this program; if not, write to the Free Software 1744358048SMagnus Damm * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 1844358048SMagnus Damm */ 1944358048SMagnus Damm 2044358048SMagnus Damm #include <linux/init.h> 21894db164SGuennadi Liakhovetski #include <linux/of.h> 2244358048SMagnus Damm #include <linux/platform_device.h> 2344358048SMagnus Damm #include <linux/spinlock.h> 2444358048SMagnus Damm #include <linux/interrupt.h> 2544358048SMagnus Damm #include <linux/ioport.h> 2644358048SMagnus Damm #include <linux/io.h> 2744358048SMagnus Damm #include <linux/irq.h> 2844358048SMagnus Damm #include <linux/irqdomain.h> 2944358048SMagnus Damm #include <linux/err.h> 3044358048SMagnus Damm #include <linux/slab.h> 3144358048SMagnus Damm #include <linux/module.h> 3244358048SMagnus Damm #include <linux/platform_data/irq-renesas-intc-irqpin.h> 3344358048SMagnus Damm 3444358048SMagnus Damm #define INTC_IRQPIN_MAX 8 /* maximum 8 interrupts per driver instance */ 3544358048SMagnus Damm 3644358048SMagnus Damm #define INTC_IRQPIN_REG_SENSE 0 /* ICRn */ 3744358048SMagnus Damm #define INTC_IRQPIN_REG_PRIO 1 /* INTPRInn */ 3844358048SMagnus Damm #define INTC_IRQPIN_REG_SOURCE 2 /* INTREQnn */ 3944358048SMagnus Damm #define INTC_IRQPIN_REG_MASK 3 /* INTMSKnn */ 4044358048SMagnus Damm #define INTC_IRQPIN_REG_CLEAR 4 /* INTMSKCLRnn */ 4144358048SMagnus Damm #define INTC_IRQPIN_REG_NR 5 4244358048SMagnus Damm 4344358048SMagnus Damm /* INTC external IRQ PIN hardware register access: 4444358048SMagnus Damm * 4544358048SMagnus Damm * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*) 4644358048SMagnus Damm * PRIO is read-write 32-bit with 4-bits per IRQ (**) 4744358048SMagnus Damm * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***) 4844358048SMagnus Damm * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 4944358048SMagnus Damm * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***) 5044358048SMagnus Damm * 5144358048SMagnus Damm * (*) May be accessed by more than one driver instance - lock needed 5244358048SMagnus Damm * (**) Read-modify-write access by one driver instance - lock needed 5344358048SMagnus Damm * (***) Accessed by one driver instance only - no locking needed 5444358048SMagnus Damm */ 5544358048SMagnus Damm 5644358048SMagnus Damm struct intc_irqpin_iomem { 5744358048SMagnus Damm void __iomem *iomem; 5844358048SMagnus Damm unsigned long (*read)(void __iomem *iomem); 5944358048SMagnus Damm void (*write)(void __iomem *iomem, unsigned long data); 6044358048SMagnus Damm int width; 6144358048SMagnus Damm }; 6244358048SMagnus Damm 6344358048SMagnus Damm struct intc_irqpin_irq { 6444358048SMagnus Damm int hw_irq; 6533f958f2SMagnus Damm int requested_irq; 6633f958f2SMagnus Damm int domain_irq; 6744358048SMagnus Damm struct intc_irqpin_priv *p; 6844358048SMagnus Damm }; 6944358048SMagnus Damm 7044358048SMagnus Damm struct intc_irqpin_priv { 7144358048SMagnus Damm struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR]; 7244358048SMagnus Damm struct intc_irqpin_irq irq[INTC_IRQPIN_MAX]; 7344358048SMagnus Damm struct renesas_intc_irqpin_config config; 7444358048SMagnus Damm unsigned int number_of_irqs; 7544358048SMagnus Damm struct platform_device *pdev; 7644358048SMagnus Damm struct irq_chip irq_chip; 7744358048SMagnus Damm struct irq_domain *irq_domain; 78427cc720SBastian Hecht bool shared_irqs; 79427cc720SBastian Hecht u8 shared_irq_mask; 8044358048SMagnus Damm }; 8144358048SMagnus Damm 8244358048SMagnus Damm static unsigned long intc_irqpin_read32(void __iomem *iomem) 8344358048SMagnus Damm { 8444358048SMagnus Damm return ioread32(iomem); 8544358048SMagnus Damm } 8644358048SMagnus Damm 8744358048SMagnus Damm static unsigned long intc_irqpin_read8(void __iomem *iomem) 8844358048SMagnus Damm { 8944358048SMagnus Damm return ioread8(iomem); 9044358048SMagnus Damm } 9144358048SMagnus Damm 9244358048SMagnus Damm static void intc_irqpin_write32(void __iomem *iomem, unsigned long data) 9344358048SMagnus Damm { 9444358048SMagnus Damm iowrite32(data, iomem); 9544358048SMagnus Damm } 9644358048SMagnus Damm 9744358048SMagnus Damm static void intc_irqpin_write8(void __iomem *iomem, unsigned long data) 9844358048SMagnus Damm { 9944358048SMagnus Damm iowrite8(data, iomem); 10044358048SMagnus Damm } 10144358048SMagnus Damm 10244358048SMagnus Damm static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p, 10344358048SMagnus Damm int reg) 10444358048SMagnus Damm { 10544358048SMagnus Damm struct intc_irqpin_iomem *i = &p->iomem[reg]; 106862d3098SMagnus Damm 10744358048SMagnus Damm return i->read(i->iomem); 10844358048SMagnus Damm } 10944358048SMagnus Damm 11044358048SMagnus Damm static inline void intc_irqpin_write(struct intc_irqpin_priv *p, 11144358048SMagnus Damm int reg, unsigned long data) 11244358048SMagnus Damm { 11344358048SMagnus Damm struct intc_irqpin_iomem *i = &p->iomem[reg]; 114862d3098SMagnus Damm 11544358048SMagnus Damm i->write(i->iomem, data); 11644358048SMagnus Damm } 11744358048SMagnus Damm 11844358048SMagnus Damm static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p, 11944358048SMagnus Damm int reg, int hw_irq) 12044358048SMagnus Damm { 12144358048SMagnus Damm return BIT((p->iomem[reg].width - 1) - hw_irq); 12244358048SMagnus Damm } 12344358048SMagnus Damm 12444358048SMagnus Damm static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p, 12544358048SMagnus Damm int reg, int hw_irq) 12644358048SMagnus Damm { 12744358048SMagnus Damm intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq)); 12844358048SMagnus Damm } 12944358048SMagnus Damm 13044358048SMagnus Damm static DEFINE_RAW_SPINLOCK(intc_irqpin_lock); /* only used by slow path */ 13144358048SMagnus Damm 13244358048SMagnus Damm static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p, 13344358048SMagnus Damm int reg, int shift, 13444358048SMagnus Damm int width, int value) 13544358048SMagnus Damm { 13644358048SMagnus Damm unsigned long flags; 13744358048SMagnus Damm unsigned long tmp; 13844358048SMagnus Damm 13944358048SMagnus Damm raw_spin_lock_irqsave(&intc_irqpin_lock, flags); 14044358048SMagnus Damm 14144358048SMagnus Damm tmp = intc_irqpin_read(p, reg); 14244358048SMagnus Damm tmp &= ~(((1 << width) - 1) << shift); 14344358048SMagnus Damm tmp |= value << shift; 14444358048SMagnus Damm intc_irqpin_write(p, reg, tmp); 14544358048SMagnus Damm 14644358048SMagnus Damm raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags); 14744358048SMagnus Damm } 14844358048SMagnus Damm 14944358048SMagnus Damm static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p, 15044358048SMagnus Damm int irq, int do_mask) 15144358048SMagnus Damm { 152e55bc558SLaurent Pinchart /* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */ 153e55bc558SLaurent Pinchart int bitfield_width = 4; 154e55bc558SLaurent Pinchart int shift = 32 - (irq + 1) * bitfield_width; 15544358048SMagnus Damm 15644358048SMagnus Damm intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO, 15744358048SMagnus Damm shift, bitfield_width, 15844358048SMagnus Damm do_mask ? 0 : (1 << bitfield_width) - 1); 15944358048SMagnus Damm } 16044358048SMagnus Damm 16144358048SMagnus Damm static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value) 16244358048SMagnus Damm { 163e55bc558SLaurent Pinchart /* The SENSE register is assumed to be 32-bit. */ 16444358048SMagnus Damm int bitfield_width = p->config.sense_bitfield_width; 165e55bc558SLaurent Pinchart int shift = 32 - (irq + 1) * bitfield_width; 16644358048SMagnus Damm 16744358048SMagnus Damm dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value); 16844358048SMagnus Damm 16944358048SMagnus Damm if (value >= (1 << bitfield_width)) 17044358048SMagnus Damm return -EINVAL; 17144358048SMagnus Damm 17244358048SMagnus Damm intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift, 17344358048SMagnus Damm bitfield_width, value); 17444358048SMagnus Damm return 0; 17544358048SMagnus Damm } 17644358048SMagnus Damm 17744358048SMagnus Damm static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str) 17844358048SMagnus Damm { 17944358048SMagnus Damm dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n", 18033f958f2SMagnus Damm str, i->requested_irq, i->hw_irq, i->domain_irq); 18144358048SMagnus Damm } 18244358048SMagnus Damm 18344358048SMagnus Damm static void intc_irqpin_irq_enable(struct irq_data *d) 18444358048SMagnus Damm { 18544358048SMagnus Damm struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 18644358048SMagnus Damm int hw_irq = irqd_to_hwirq(d); 18744358048SMagnus Damm 18844358048SMagnus Damm intc_irqpin_dbg(&p->irq[hw_irq], "enable"); 18944358048SMagnus Damm intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); 19044358048SMagnus Damm } 19144358048SMagnus Damm 19244358048SMagnus Damm static void intc_irqpin_irq_disable(struct irq_data *d) 19344358048SMagnus Damm { 19444358048SMagnus Damm struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 19544358048SMagnus Damm int hw_irq = irqd_to_hwirq(d); 19644358048SMagnus Damm 19744358048SMagnus Damm intc_irqpin_dbg(&p->irq[hw_irq], "disable"); 19844358048SMagnus Damm intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); 19944358048SMagnus Damm } 20044358048SMagnus Damm 201427cc720SBastian Hecht static void intc_irqpin_shared_irq_enable(struct irq_data *d) 202427cc720SBastian Hecht { 203427cc720SBastian Hecht struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 204427cc720SBastian Hecht int hw_irq = irqd_to_hwirq(d); 205427cc720SBastian Hecht 206427cc720SBastian Hecht intc_irqpin_dbg(&p->irq[hw_irq], "shared enable"); 207427cc720SBastian Hecht intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq); 208427cc720SBastian Hecht 209427cc720SBastian Hecht p->shared_irq_mask &= ~BIT(hw_irq); 210427cc720SBastian Hecht } 211427cc720SBastian Hecht 212427cc720SBastian Hecht static void intc_irqpin_shared_irq_disable(struct irq_data *d) 213427cc720SBastian Hecht { 214427cc720SBastian Hecht struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 215427cc720SBastian Hecht int hw_irq = irqd_to_hwirq(d); 216427cc720SBastian Hecht 217427cc720SBastian Hecht intc_irqpin_dbg(&p->irq[hw_irq], "shared disable"); 218427cc720SBastian Hecht intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq); 219427cc720SBastian Hecht 220427cc720SBastian Hecht p->shared_irq_mask |= BIT(hw_irq); 221427cc720SBastian Hecht } 222427cc720SBastian Hecht 22344358048SMagnus Damm static void intc_irqpin_irq_enable_force(struct irq_data *d) 22444358048SMagnus Damm { 22544358048SMagnus Damm struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 22633f958f2SMagnus Damm int irq = p->irq[irqd_to_hwirq(d)].requested_irq; 22744358048SMagnus Damm 22844358048SMagnus Damm intc_irqpin_irq_enable(d); 229d1b6aecdSMagnus Damm 230d1b6aecdSMagnus Damm /* enable interrupt through parent interrupt controller, 231d1b6aecdSMagnus Damm * assumes non-shared interrupt with 1:1 mapping 232d1b6aecdSMagnus Damm * needed for busted IRQs on some SoCs like sh73a0 233d1b6aecdSMagnus Damm */ 23444358048SMagnus Damm irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq)); 23544358048SMagnus Damm } 23644358048SMagnus Damm 23744358048SMagnus Damm static void intc_irqpin_irq_disable_force(struct irq_data *d) 23844358048SMagnus Damm { 23944358048SMagnus Damm struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 24033f958f2SMagnus Damm int irq = p->irq[irqd_to_hwirq(d)].requested_irq; 24144358048SMagnus Damm 242d1b6aecdSMagnus Damm /* disable interrupt through parent interrupt controller, 243d1b6aecdSMagnus Damm * assumes non-shared interrupt with 1:1 mapping 244d1b6aecdSMagnus Damm * needed for busted IRQs on some SoCs like sh73a0 245d1b6aecdSMagnus Damm */ 24644358048SMagnus Damm irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq)); 24744358048SMagnus Damm intc_irqpin_irq_disable(d); 24844358048SMagnus Damm } 24944358048SMagnus Damm 25044358048SMagnus Damm #define INTC_IRQ_SENSE_VALID 0x10 25144358048SMagnus Damm #define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID) 25244358048SMagnus Damm 25344358048SMagnus Damm static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = { 25444358048SMagnus Damm [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00), 25544358048SMagnus Damm [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01), 25644358048SMagnus Damm [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02), 25744358048SMagnus Damm [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03), 25844358048SMagnus Damm [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04), 25944358048SMagnus Damm }; 26044358048SMagnus Damm 26144358048SMagnus Damm static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type) 26244358048SMagnus Damm { 26344358048SMagnus Damm unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK]; 26444358048SMagnus Damm struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d); 26544358048SMagnus Damm 26644358048SMagnus Damm if (!(value & INTC_IRQ_SENSE_VALID)) 26744358048SMagnus Damm return -EINVAL; 26844358048SMagnus Damm 26944358048SMagnus Damm return intc_irqpin_set_sense(p, irqd_to_hwirq(d), 27044358048SMagnus Damm value ^ INTC_IRQ_SENSE_VALID); 27144358048SMagnus Damm } 27244358048SMagnus Damm 27344358048SMagnus Damm static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id) 27444358048SMagnus Damm { 27544358048SMagnus Damm struct intc_irqpin_irq *i = dev_id; 27644358048SMagnus Damm struct intc_irqpin_priv *p = i->p; 27744358048SMagnus Damm unsigned long bit; 27844358048SMagnus Damm 27944358048SMagnus Damm intc_irqpin_dbg(i, "demux1"); 28044358048SMagnus Damm bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq); 28144358048SMagnus Damm 28244358048SMagnus Damm if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) { 28344358048SMagnus Damm intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit); 28444358048SMagnus Damm intc_irqpin_dbg(i, "demux2"); 28533f958f2SMagnus Damm generic_handle_irq(i->domain_irq); 28644358048SMagnus Damm return IRQ_HANDLED; 28744358048SMagnus Damm } 28844358048SMagnus Damm return IRQ_NONE; 28944358048SMagnus Damm } 29044358048SMagnus Damm 291427cc720SBastian Hecht static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id) 292427cc720SBastian Hecht { 293427cc720SBastian Hecht struct intc_irqpin_priv *p = dev_id; 294427cc720SBastian Hecht unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE); 295427cc720SBastian Hecht irqreturn_t status = IRQ_NONE; 296427cc720SBastian Hecht int k; 297427cc720SBastian Hecht 298427cc720SBastian Hecht for (k = 0; k < 8; k++) { 299427cc720SBastian Hecht if (reg_source & BIT(7 - k)) { 300427cc720SBastian Hecht if (BIT(k) & p->shared_irq_mask) 301427cc720SBastian Hecht continue; 302427cc720SBastian Hecht 303427cc720SBastian Hecht status |= intc_irqpin_irq_handler(irq, &p->irq[k]); 304427cc720SBastian Hecht } 305427cc720SBastian Hecht } 306427cc720SBastian Hecht 307427cc720SBastian Hecht return status; 308427cc720SBastian Hecht } 309427cc720SBastian Hecht 31044358048SMagnus Damm static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq, 31144358048SMagnus Damm irq_hw_number_t hw) 31244358048SMagnus Damm { 31344358048SMagnus Damm struct intc_irqpin_priv *p = h->host_data; 31444358048SMagnus Damm 31533f958f2SMagnus Damm p->irq[hw].domain_irq = virq; 31633f958f2SMagnus Damm p->irq[hw].hw_irq = hw; 31733f958f2SMagnus Damm 31844358048SMagnus Damm intc_irqpin_dbg(&p->irq[hw], "map"); 31944358048SMagnus Damm irq_set_chip_data(virq, h->host_data); 32044358048SMagnus Damm irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq); 32144358048SMagnus Damm set_irq_flags(virq, IRQF_VALID); /* kill me now */ 32244358048SMagnus Damm return 0; 32344358048SMagnus Damm } 32444358048SMagnus Damm 32544358048SMagnus Damm static struct irq_domain_ops intc_irqpin_irq_domain_ops = { 32644358048SMagnus Damm .map = intc_irqpin_irq_domain_map, 3279d833bbeSMagnus Damm .xlate = irq_domain_xlate_twocell, 32844358048SMagnus Damm }; 32944358048SMagnus Damm 33044358048SMagnus Damm static int intc_irqpin_probe(struct platform_device *pdev) 33144358048SMagnus Damm { 33236845f1bSGeert Uytterhoeven struct device *dev = &pdev->dev; 33336845f1bSGeert Uytterhoeven struct renesas_intc_irqpin_config *pdata = dev->platform_data; 33444358048SMagnus Damm struct intc_irqpin_priv *p; 33544358048SMagnus Damm struct intc_irqpin_iomem *i; 33644358048SMagnus Damm struct resource *io[INTC_IRQPIN_REG_NR]; 33744358048SMagnus Damm struct resource *irq; 33844358048SMagnus Damm struct irq_chip *irq_chip; 33944358048SMagnus Damm void (*enable_fn)(struct irq_data *d); 34044358048SMagnus Damm void (*disable_fn)(struct irq_data *d); 34136845f1bSGeert Uytterhoeven const char *name = dev_name(dev); 342427cc720SBastian Hecht int ref_irq; 34344358048SMagnus Damm int ret; 34444358048SMagnus Damm int k; 34544358048SMagnus Damm 34636845f1bSGeert Uytterhoeven p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL); 34744358048SMagnus Damm if (!p) { 34836845f1bSGeert Uytterhoeven dev_err(dev, "failed to allocate driver data\n"); 34944358048SMagnus Damm ret = -ENOMEM; 35044358048SMagnus Damm goto err0; 35144358048SMagnus Damm } 35244358048SMagnus Damm 35344358048SMagnus Damm /* deal with driver instance configuration */ 354c4fa4946SGuennadi Liakhovetski if (pdata) { 35544358048SMagnus Damm memcpy(&p->config, pdata, sizeof(*pdata)); 356c4fa4946SGuennadi Liakhovetski } else { 35736845f1bSGeert Uytterhoeven of_property_read_u32(dev->of_node, "sense-bitfield-width", 358894db164SGuennadi Liakhovetski &p->config.sense_bitfield_width); 35936845f1bSGeert Uytterhoeven p->config.control_parent = of_property_read_bool(dev->of_node, 360c4fa4946SGuennadi Liakhovetski "control-parent"); 361c4fa4946SGuennadi Liakhovetski } 36244358048SMagnus Damm if (!p->config.sense_bitfield_width) 36344358048SMagnus Damm p->config.sense_bitfield_width = 4; /* default to 4 bits */ 36444358048SMagnus Damm 36544358048SMagnus Damm p->pdev = pdev; 36644358048SMagnus Damm platform_set_drvdata(pdev, p); 36744358048SMagnus Damm 36844358048SMagnus Damm /* get hold of manadatory IOMEM */ 36944358048SMagnus Damm for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { 37044358048SMagnus Damm io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k); 37144358048SMagnus Damm if (!io[k]) { 37236845f1bSGeert Uytterhoeven dev_err(dev, "not enough IOMEM resources\n"); 37344358048SMagnus Damm ret = -EINVAL; 37408eba5baSMagnus Damm goto err0; 37544358048SMagnus Damm } 37644358048SMagnus Damm } 37744358048SMagnus Damm 37844358048SMagnus Damm /* allow any number of IRQs between 1 and INTC_IRQPIN_MAX */ 37944358048SMagnus Damm for (k = 0; k < INTC_IRQPIN_MAX; k++) { 38044358048SMagnus Damm irq = platform_get_resource(pdev, IORESOURCE_IRQ, k); 38144358048SMagnus Damm if (!irq) 38244358048SMagnus Damm break; 38344358048SMagnus Damm 38444358048SMagnus Damm p->irq[k].p = p; 38533f958f2SMagnus Damm p->irq[k].requested_irq = irq->start; 38644358048SMagnus Damm } 38744358048SMagnus Damm 38844358048SMagnus Damm p->number_of_irqs = k; 38944358048SMagnus Damm if (p->number_of_irqs < 1) { 39036845f1bSGeert Uytterhoeven dev_err(dev, "not enough IRQ resources\n"); 39144358048SMagnus Damm ret = -EINVAL; 39208eba5baSMagnus Damm goto err0; 39344358048SMagnus Damm } 39444358048SMagnus Damm 39544358048SMagnus Damm /* ioremap IOMEM and setup read/write callbacks */ 39644358048SMagnus Damm for (k = 0; k < INTC_IRQPIN_REG_NR; k++) { 39744358048SMagnus Damm i = &p->iomem[k]; 39844358048SMagnus Damm 39944358048SMagnus Damm switch (resource_size(io[k])) { 40044358048SMagnus Damm case 1: 40144358048SMagnus Damm i->width = 8; 40244358048SMagnus Damm i->read = intc_irqpin_read8; 40344358048SMagnus Damm i->write = intc_irqpin_write8; 40444358048SMagnus Damm break; 40544358048SMagnus Damm case 4: 40644358048SMagnus Damm i->width = 32; 40744358048SMagnus Damm i->read = intc_irqpin_read32; 40844358048SMagnus Damm i->write = intc_irqpin_write32; 40944358048SMagnus Damm break; 41044358048SMagnus Damm default: 41136845f1bSGeert Uytterhoeven dev_err(dev, "IOMEM size mismatch\n"); 41244358048SMagnus Damm ret = -EINVAL; 41308eba5baSMagnus Damm goto err0; 41444358048SMagnus Damm } 41544358048SMagnus Damm 41636845f1bSGeert Uytterhoeven i->iomem = devm_ioremap_nocache(dev, io[k]->start, 41708eba5baSMagnus Damm resource_size(io[k])); 41844358048SMagnus Damm if (!i->iomem) { 41936845f1bSGeert Uytterhoeven dev_err(dev, "failed to remap IOMEM\n"); 42044358048SMagnus Damm ret = -ENXIO; 42108eba5baSMagnus Damm goto err0; 42244358048SMagnus Damm } 42344358048SMagnus Damm } 42444358048SMagnus Damm 42544358048SMagnus Damm /* mask all interrupts using priority */ 42644358048SMagnus Damm for (k = 0; k < p->number_of_irqs; k++) 42744358048SMagnus Damm intc_irqpin_mask_unmask_prio(p, k, 1); 42844358048SMagnus Damm 429427cc720SBastian Hecht /* clear all pending interrupts */ 430427cc720SBastian Hecht intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0); 431427cc720SBastian Hecht 432427cc720SBastian Hecht /* scan for shared interrupt lines */ 433427cc720SBastian Hecht ref_irq = p->irq[0].requested_irq; 434427cc720SBastian Hecht p->shared_irqs = true; 435427cc720SBastian Hecht for (k = 1; k < p->number_of_irqs; k++) { 436427cc720SBastian Hecht if (ref_irq != p->irq[k].requested_irq) { 437427cc720SBastian Hecht p->shared_irqs = false; 438427cc720SBastian Hecht break; 439427cc720SBastian Hecht } 440427cc720SBastian Hecht } 441427cc720SBastian Hecht 44244358048SMagnus Damm /* use more severe masking method if requested */ 44344358048SMagnus Damm if (p->config.control_parent) { 44444358048SMagnus Damm enable_fn = intc_irqpin_irq_enable_force; 44544358048SMagnus Damm disable_fn = intc_irqpin_irq_disable_force; 446427cc720SBastian Hecht } else if (!p->shared_irqs) { 44744358048SMagnus Damm enable_fn = intc_irqpin_irq_enable; 44844358048SMagnus Damm disable_fn = intc_irqpin_irq_disable; 449427cc720SBastian Hecht } else { 450427cc720SBastian Hecht enable_fn = intc_irqpin_shared_irq_enable; 451427cc720SBastian Hecht disable_fn = intc_irqpin_shared_irq_disable; 45244358048SMagnus Damm } 45344358048SMagnus Damm 45444358048SMagnus Damm irq_chip = &p->irq_chip; 45544358048SMagnus Damm irq_chip->name = name; 45644358048SMagnus Damm irq_chip->irq_mask = disable_fn; 45744358048SMagnus Damm irq_chip->irq_unmask = enable_fn; 45844358048SMagnus Damm irq_chip->irq_set_type = intc_irqpin_irq_set_type; 4591c36d42cSGeert Uytterhoeven irq_chip->flags = IRQCHIP_SKIP_SET_WAKE | IRQCHIP_MASK_ON_SUSPEND; 46044358048SMagnus Damm 46136845f1bSGeert Uytterhoeven p->irq_domain = irq_domain_add_simple(dev->of_node, 46244358048SMagnus Damm p->number_of_irqs, 46344358048SMagnus Damm p->config.irq_base, 46444358048SMagnus Damm &intc_irqpin_irq_domain_ops, p); 46544358048SMagnus Damm if (!p->irq_domain) { 46644358048SMagnus Damm ret = -ENXIO; 46736845f1bSGeert Uytterhoeven dev_err(dev, "cannot initialize irq domain\n"); 46808eba5baSMagnus Damm goto err0; 46944358048SMagnus Damm } 47044358048SMagnus Damm 471427cc720SBastian Hecht if (p->shared_irqs) { 472427cc720SBastian Hecht /* request one shared interrupt */ 47336845f1bSGeert Uytterhoeven if (devm_request_irq(dev, p->irq[0].requested_irq, 474427cc720SBastian Hecht intc_irqpin_shared_irq_handler, 475427cc720SBastian Hecht IRQF_SHARED, name, p)) { 47636845f1bSGeert Uytterhoeven dev_err(dev, "failed to request low IRQ\n"); 47744358048SMagnus Damm ret = -ENOENT; 47808eba5baSMagnus Damm goto err1; 47944358048SMagnus Damm } 480427cc720SBastian Hecht } else { 481427cc720SBastian Hecht /* request interrupts one by one */ 482427cc720SBastian Hecht for (k = 0; k < p->number_of_irqs; k++) { 48336845f1bSGeert Uytterhoeven if (devm_request_irq(dev, p->irq[k].requested_irq, 48436845f1bSGeert Uytterhoeven intc_irqpin_irq_handler, 0, name, 48536845f1bSGeert Uytterhoeven &p->irq[k])) { 48636845f1bSGeert Uytterhoeven dev_err(dev, "failed to request low IRQ\n"); 487427cc720SBastian Hecht ret = -ENOENT; 488427cc720SBastian Hecht goto err1; 48944358048SMagnus Damm } 490427cc720SBastian Hecht } 491427cc720SBastian Hecht } 492427cc720SBastian Hecht 493427cc720SBastian Hecht /* unmask all interrupts on prio level */ 494427cc720SBastian Hecht for (k = 0; k < p->number_of_irqs; k++) 495427cc720SBastian Hecht intc_irqpin_mask_unmask_prio(p, k, 0); 49644358048SMagnus Damm 49736845f1bSGeert Uytterhoeven dev_info(dev, "driving %d irqs\n", p->number_of_irqs); 49844358048SMagnus Damm 49944358048SMagnus Damm /* warn in case of mismatch if irq base is specified */ 50044358048SMagnus Damm if (p->config.irq_base) { 50133f958f2SMagnus Damm if (p->config.irq_base != p->irq[0].domain_irq) 50236845f1bSGeert Uytterhoeven dev_warn(dev, "irq base mismatch (%d/%d)\n", 50333f958f2SMagnus Damm p->config.irq_base, p->irq[0].domain_irq); 50444358048SMagnus Damm } 50544358048SMagnus Damm 50644358048SMagnus Damm return 0; 50744358048SMagnus Damm 50844358048SMagnus Damm err1: 50908eba5baSMagnus Damm irq_domain_remove(p->irq_domain); 51044358048SMagnus Damm err0: 51144358048SMagnus Damm return ret; 51244358048SMagnus Damm } 51344358048SMagnus Damm 51444358048SMagnus Damm static int intc_irqpin_remove(struct platform_device *pdev) 51544358048SMagnus Damm { 51644358048SMagnus Damm struct intc_irqpin_priv *p = platform_get_drvdata(pdev); 51744358048SMagnus Damm 51844358048SMagnus Damm irq_domain_remove(p->irq_domain); 51944358048SMagnus Damm 52044358048SMagnus Damm return 0; 52144358048SMagnus Damm } 52244358048SMagnus Damm 5239d833bbeSMagnus Damm static const struct of_device_id intc_irqpin_dt_ids[] = { 5249d833bbeSMagnus Damm { .compatible = "renesas,intc-irqpin", }, 5259d833bbeSMagnus Damm {}, 5269d833bbeSMagnus Damm }; 5279d833bbeSMagnus Damm MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids); 5289d833bbeSMagnus Damm 52944358048SMagnus Damm static struct platform_driver intc_irqpin_device_driver = { 53044358048SMagnus Damm .probe = intc_irqpin_probe, 53144358048SMagnus Damm .remove = intc_irqpin_remove, 53244358048SMagnus Damm .driver = { 53344358048SMagnus Damm .name = "renesas_intc_irqpin", 5349d833bbeSMagnus Damm .of_match_table = intc_irqpin_dt_ids, 5359d833bbeSMagnus Damm .owner = THIS_MODULE, 53644358048SMagnus Damm } 53744358048SMagnus Damm }; 53844358048SMagnus Damm 53944358048SMagnus Damm static int __init intc_irqpin_init(void) 54044358048SMagnus Damm { 54144358048SMagnus Damm return platform_driver_register(&intc_irqpin_device_driver); 54244358048SMagnus Damm } 54344358048SMagnus Damm postcore_initcall(intc_irqpin_init); 54444358048SMagnus Damm 54544358048SMagnus Damm static void __exit intc_irqpin_exit(void) 54644358048SMagnus Damm { 54744358048SMagnus Damm platform_driver_unregister(&intc_irqpin_device_driver); 54844358048SMagnus Damm } 54944358048SMagnus Damm module_exit(intc_irqpin_exit); 55044358048SMagnus Damm 55144358048SMagnus Damm MODULE_AUTHOR("Magnus Damm"); 55244358048SMagnus Damm MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver"); 55344358048SMagnus Damm MODULE_LICENSE("GPL v2"); 554