12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 2aaa8666aSCristian Birsan /* 3aaa8666aSCristian Birsan * Cristian Birsan <cristian.birsan@microchip.com> 4aaa8666aSCristian Birsan * Joshua Henderson <joshua.henderson@microchip.com> 5aaa8666aSCristian Birsan * Copyright (C) 2016 Microchip Technology Inc. All rights reserved. 6aaa8666aSCristian Birsan */ 7aaa8666aSCristian Birsan #include <linux/kernel.h> 8aaa8666aSCristian Birsan #include <linux/module.h> 9aaa8666aSCristian Birsan #include <linux/interrupt.h> 10aaa8666aSCristian Birsan #include <linux/irqdomain.h> 11aaa8666aSCristian Birsan #include <linux/of_address.h> 12aaa8666aSCristian Birsan #include <linux/slab.h> 13aaa8666aSCristian Birsan #include <linux/io.h> 14aaa8666aSCristian Birsan #include <linux/irqchip.h> 15aaa8666aSCristian Birsan #include <linux/irq.h> 16aaa8666aSCristian Birsan 17aaa8666aSCristian Birsan #include <asm/irq.h> 18aaa8666aSCristian Birsan #include <asm/traps.h> 19aaa8666aSCristian Birsan #include <asm/mach-pic32/pic32.h> 20aaa8666aSCristian Birsan 21aaa8666aSCristian Birsan #define REG_INTCON 0x0000 22aaa8666aSCristian Birsan #define REG_INTSTAT 0x0020 23aaa8666aSCristian Birsan #define REG_IFS_OFFSET 0x0040 24aaa8666aSCristian Birsan #define REG_IEC_OFFSET 0x00C0 25aaa8666aSCristian Birsan #define REG_IPC_OFFSET 0x0140 26aaa8666aSCristian Birsan #define REG_OFF_OFFSET 0x0540 27aaa8666aSCristian Birsan 28aaa8666aSCristian Birsan #define MAJPRI_MASK 0x07 29aaa8666aSCristian Birsan #define SUBPRI_MASK 0x03 30aaa8666aSCristian Birsan #define PRIORITY_MASK 0x1F 31aaa8666aSCristian Birsan 32aaa8666aSCristian Birsan #define PIC32_INT_PRI(pri, subpri) \ 33aaa8666aSCristian Birsan ((((pri) & MAJPRI_MASK) << 2) | ((subpri) & SUBPRI_MASK)) 34aaa8666aSCristian Birsan 35aaa8666aSCristian Birsan struct evic_chip_data { 36aaa8666aSCristian Birsan u32 irq_types[NR_IRQS]; 37aaa8666aSCristian Birsan u32 ext_irqs[8]; 38aaa8666aSCristian Birsan }; 39aaa8666aSCristian Birsan 40aaa8666aSCristian Birsan static struct irq_domain *evic_irq_domain; 41aaa8666aSCristian Birsan static void __iomem *evic_base; 42aaa8666aSCristian Birsan 43aaa8666aSCristian Birsan asmlinkage void __weak plat_irq_dispatch(void) 44aaa8666aSCristian Birsan { 45aaa8666aSCristian Birsan unsigned int irq, hwirq; 46aaa8666aSCristian Birsan 47aaa8666aSCristian Birsan hwirq = readl(evic_base + REG_INTSTAT) & 0xFF; 48aaa8666aSCristian Birsan irq = irq_linear_revmap(evic_irq_domain, hwirq); 49aaa8666aSCristian Birsan do_IRQ(irq); 50aaa8666aSCristian Birsan } 51aaa8666aSCristian Birsan 52aaa8666aSCristian Birsan static struct evic_chip_data *irqd_to_priv(struct irq_data *data) 53aaa8666aSCristian Birsan { 54aaa8666aSCristian Birsan return (struct evic_chip_data *)data->domain->host_data; 55aaa8666aSCristian Birsan } 56aaa8666aSCristian Birsan 57aaa8666aSCristian Birsan static int pic32_set_ext_polarity(int bit, u32 type) 58aaa8666aSCristian Birsan { 59aaa8666aSCristian Birsan /* 60aaa8666aSCristian Birsan * External interrupts can be either edge rising or edge falling, 61aaa8666aSCristian Birsan * but not both. 62aaa8666aSCristian Birsan */ 63aaa8666aSCristian Birsan switch (type) { 64aaa8666aSCristian Birsan case IRQ_TYPE_EDGE_RISING: 65aaa8666aSCristian Birsan writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON)); 66aaa8666aSCristian Birsan break; 67aaa8666aSCristian Birsan case IRQ_TYPE_EDGE_FALLING: 68aaa8666aSCristian Birsan writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON)); 69aaa8666aSCristian Birsan break; 70aaa8666aSCristian Birsan default: 71aaa8666aSCristian Birsan return -EINVAL; 72aaa8666aSCristian Birsan } 73aaa8666aSCristian Birsan 74aaa8666aSCristian Birsan return 0; 75aaa8666aSCristian Birsan } 76aaa8666aSCristian Birsan 77aaa8666aSCristian Birsan static int pic32_set_type_edge(struct irq_data *data, 78aaa8666aSCristian Birsan unsigned int flow_type) 79aaa8666aSCristian Birsan { 80aaa8666aSCristian Birsan struct evic_chip_data *priv = irqd_to_priv(data); 81aaa8666aSCristian Birsan int ret; 82aaa8666aSCristian Birsan int i; 83aaa8666aSCristian Birsan 84aaa8666aSCristian Birsan if (!(flow_type & IRQ_TYPE_EDGE_BOTH)) 85aaa8666aSCristian Birsan return -EBADR; 86aaa8666aSCristian Birsan 87aaa8666aSCristian Birsan /* set polarity for external interrupts only */ 88aaa8666aSCristian Birsan for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) { 89aaa8666aSCristian Birsan if (priv->ext_irqs[i] == data->hwirq) { 900de6b997SJoshua Henderson ret = pic32_set_ext_polarity(i, flow_type); 91aaa8666aSCristian Birsan if (ret) 92aaa8666aSCristian Birsan return ret; 93aaa8666aSCristian Birsan } 94aaa8666aSCristian Birsan } 95aaa8666aSCristian Birsan 96aaa8666aSCristian Birsan irqd_set_trigger_type(data, flow_type); 97aaa8666aSCristian Birsan 98aaa8666aSCristian Birsan return IRQ_SET_MASK_OK; 99aaa8666aSCristian Birsan } 100aaa8666aSCristian Birsan 101aaa8666aSCristian Birsan static void pic32_bind_evic_interrupt(int irq, int set) 102aaa8666aSCristian Birsan { 103aaa8666aSCristian Birsan writel(set, evic_base + REG_OFF_OFFSET + irq * 4); 104aaa8666aSCristian Birsan } 105aaa8666aSCristian Birsan 106aaa8666aSCristian Birsan static void pic32_set_irq_priority(int irq, int priority) 107aaa8666aSCristian Birsan { 108aaa8666aSCristian Birsan u32 reg, shift; 109aaa8666aSCristian Birsan 110aaa8666aSCristian Birsan reg = irq / 4; 111aaa8666aSCristian Birsan shift = (irq % 4) * 8; 112aaa8666aSCristian Birsan 113aaa8666aSCristian Birsan writel(PRIORITY_MASK << shift, 114aaa8666aSCristian Birsan evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10)); 115aaa8666aSCristian Birsan writel(priority << shift, 116aaa8666aSCristian Birsan evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10)); 117aaa8666aSCristian Birsan } 118aaa8666aSCristian Birsan 119aaa8666aSCristian Birsan #define IRQ_REG_MASK(_hwirq, _reg, _mask) \ 120aaa8666aSCristian Birsan do { \ 121aaa8666aSCristian Birsan _reg = _hwirq / 32; \ 122aaa8666aSCristian Birsan _mask = 1 << (_hwirq % 32); \ 123aaa8666aSCristian Birsan } while (0) 124aaa8666aSCristian Birsan 125aaa8666aSCristian Birsan static int pic32_irq_domain_map(struct irq_domain *d, unsigned int virq, 126aaa8666aSCristian Birsan irq_hw_number_t hw) 127aaa8666aSCristian Birsan { 128aaa8666aSCristian Birsan struct evic_chip_data *priv = d->host_data; 129aaa8666aSCristian Birsan struct irq_data *data; 130aaa8666aSCristian Birsan int ret; 131aaa8666aSCristian Birsan u32 iecclr, ifsclr; 132aaa8666aSCristian Birsan u32 reg, mask; 133aaa8666aSCristian Birsan 134aaa8666aSCristian Birsan ret = irq_map_generic_chip(d, virq, hw); 135aaa8666aSCristian Birsan if (ret) 136aaa8666aSCristian Birsan return ret; 137aaa8666aSCristian Birsan 138aaa8666aSCristian Birsan /* 139aaa8666aSCristian Birsan * Piggyback on xlate function to move to an alternate chip as necessary 140aaa8666aSCristian Birsan * at time of mapping instead of allowing the flow handler/chip to be 141aaa8666aSCristian Birsan * changed later. This requires all interrupts to be configured through 142aaa8666aSCristian Birsan * DT. 143aaa8666aSCristian Birsan */ 144aaa8666aSCristian Birsan if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) { 145aaa8666aSCristian Birsan data = irq_domain_get_irq_data(d, virq); 146aaa8666aSCristian Birsan irqd_set_trigger_type(data, priv->irq_types[hw]); 147aaa8666aSCristian Birsan irq_setup_alt_chip(data, priv->irq_types[hw]); 148aaa8666aSCristian Birsan } 149aaa8666aSCristian Birsan 150aaa8666aSCristian Birsan IRQ_REG_MASK(hw, reg, mask); 151aaa8666aSCristian Birsan 152aaa8666aSCristian Birsan iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10); 153aaa8666aSCristian Birsan ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10); 154aaa8666aSCristian Birsan 155aaa8666aSCristian Birsan /* mask and clear flag */ 156aaa8666aSCristian Birsan writel(mask, evic_base + iecclr); 157aaa8666aSCristian Birsan writel(mask, evic_base + ifsclr); 158aaa8666aSCristian Birsan 159aaa8666aSCristian Birsan /* default priority is required */ 160aaa8666aSCristian Birsan pic32_set_irq_priority(hw, PIC32_INT_PRI(2, 0)); 161aaa8666aSCristian Birsan 162aaa8666aSCristian Birsan return ret; 163aaa8666aSCristian Birsan } 164aaa8666aSCristian Birsan 165aaa8666aSCristian Birsan int pic32_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, 166aaa8666aSCristian Birsan const u32 *intspec, unsigned int intsize, 167aaa8666aSCristian Birsan irq_hw_number_t *out_hwirq, unsigned int *out_type) 168aaa8666aSCristian Birsan { 169aaa8666aSCristian Birsan struct evic_chip_data *priv = d->host_data; 170aaa8666aSCristian Birsan 171aaa8666aSCristian Birsan if (WARN_ON(intsize < 2)) 172aaa8666aSCristian Birsan return -EINVAL; 173aaa8666aSCristian Birsan 174aaa8666aSCristian Birsan if (WARN_ON(intspec[0] >= NR_IRQS)) 175aaa8666aSCristian Birsan return -EINVAL; 176aaa8666aSCristian Birsan 177aaa8666aSCristian Birsan *out_hwirq = intspec[0]; 178aaa8666aSCristian Birsan *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; 179aaa8666aSCristian Birsan 180aaa8666aSCristian Birsan priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK; 181aaa8666aSCristian Birsan 182aaa8666aSCristian Birsan return 0; 183aaa8666aSCristian Birsan } 184aaa8666aSCristian Birsan 185aaa8666aSCristian Birsan static const struct irq_domain_ops pic32_irq_domain_ops = { 186aaa8666aSCristian Birsan .map = pic32_irq_domain_map, 187aaa8666aSCristian Birsan .xlate = pic32_irq_domain_xlate, 188aaa8666aSCristian Birsan }; 189aaa8666aSCristian Birsan 190aaa8666aSCristian Birsan static void __init pic32_ext_irq_of_init(struct irq_domain *domain) 191aaa8666aSCristian Birsan { 192aaa8666aSCristian Birsan struct device_node *node = irq_domain_get_of_node(domain); 193aaa8666aSCristian Birsan struct evic_chip_data *priv = domain->host_data; 194aaa8666aSCristian Birsan struct property *prop; 195aaa8666aSCristian Birsan const __le32 *p; 196aaa8666aSCristian Birsan u32 hwirq; 197aaa8666aSCristian Birsan int i = 0; 198aaa8666aSCristian Birsan const char *pname = "microchip,external-irqs"; 199aaa8666aSCristian Birsan 200aaa8666aSCristian Birsan of_property_for_each_u32(node, pname, prop, p, hwirq) { 201aaa8666aSCristian Birsan if (i >= ARRAY_SIZE(priv->ext_irqs)) { 202aaa8666aSCristian Birsan pr_warn("More than %d external irq, skip rest\n", 203aaa8666aSCristian Birsan ARRAY_SIZE(priv->ext_irqs)); 204aaa8666aSCristian Birsan break; 205aaa8666aSCristian Birsan } 206aaa8666aSCristian Birsan 207aaa8666aSCristian Birsan priv->ext_irqs[i] = hwirq; 208aaa8666aSCristian Birsan i++; 209aaa8666aSCristian Birsan } 210aaa8666aSCristian Birsan } 211aaa8666aSCristian Birsan 212aaa8666aSCristian Birsan static int __init pic32_of_init(struct device_node *node, 213aaa8666aSCristian Birsan struct device_node *parent) 214aaa8666aSCristian Birsan { 215aaa8666aSCristian Birsan struct irq_chip_generic *gc; 216aaa8666aSCristian Birsan struct evic_chip_data *priv; 217aaa8666aSCristian Birsan unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 218aaa8666aSCristian Birsan int nchips, ret; 219aaa8666aSCristian Birsan int i; 220aaa8666aSCristian Birsan 221aaa8666aSCristian Birsan nchips = DIV_ROUND_UP(NR_IRQS, 32); 222aaa8666aSCristian Birsan 223aaa8666aSCristian Birsan evic_base = of_iomap(node, 0); 224aaa8666aSCristian Birsan if (!evic_base) 225aaa8666aSCristian Birsan return -ENOMEM; 226aaa8666aSCristian Birsan 227aaa8666aSCristian Birsan priv = kcalloc(nchips, sizeof(*priv), GFP_KERNEL); 228aaa8666aSCristian Birsan if (!priv) { 229aaa8666aSCristian Birsan ret = -ENOMEM; 230aaa8666aSCristian Birsan goto err_iounmap; 231aaa8666aSCristian Birsan } 232aaa8666aSCristian Birsan 233aaa8666aSCristian Birsan evic_irq_domain = irq_domain_add_linear(node, nchips * 32, 234aaa8666aSCristian Birsan &pic32_irq_domain_ops, 235aaa8666aSCristian Birsan priv); 236aaa8666aSCristian Birsan if (!evic_irq_domain) { 237aaa8666aSCristian Birsan ret = -ENOMEM; 238aaa8666aSCristian Birsan goto err_free_priv; 239aaa8666aSCristian Birsan } 240aaa8666aSCristian Birsan 241aaa8666aSCristian Birsan /* 242aaa8666aSCristian Birsan * The PIC32 EVIC has a linear list of irqs and the type of each 243aaa8666aSCristian Birsan * irq is determined by the hardware peripheral the EVIC is arbitrating. 244aaa8666aSCristian Birsan * These irq types are defined in the datasheet as "persistent" and 245aaa8666aSCristian Birsan * "non-persistent" which are mapped here to level and edge 246aaa8666aSCristian Birsan * respectively. To manage the different flow handler requirements of 247aaa8666aSCristian Birsan * each irq type, different chip_types are used. 248aaa8666aSCristian Birsan */ 249aaa8666aSCristian Birsan ret = irq_alloc_domain_generic_chips(evic_irq_domain, 32, 2, 250aaa8666aSCristian Birsan "evic-level", handle_level_irq, 251aaa8666aSCristian Birsan clr, 0, 0); 252aaa8666aSCristian Birsan if (ret) 253aaa8666aSCristian Birsan goto err_domain_remove; 254aaa8666aSCristian Birsan 255aaa8666aSCristian Birsan board_bind_eic_interrupt = &pic32_bind_evic_interrupt; 256aaa8666aSCristian Birsan 257aaa8666aSCristian Birsan for (i = 0; i < nchips; i++) { 258aaa8666aSCristian Birsan u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10)); 259aaa8666aSCristian Birsan u32 iec = REG_IEC_OFFSET + (i * 0x10); 260aaa8666aSCristian Birsan 261aaa8666aSCristian Birsan gc = irq_get_domain_generic_chip(evic_irq_domain, i * 32); 262aaa8666aSCristian Birsan 263aaa8666aSCristian Birsan gc->reg_base = evic_base; 264aaa8666aSCristian Birsan gc->unused = 0; 265aaa8666aSCristian Birsan 266aaa8666aSCristian Birsan /* 267aaa8666aSCristian Birsan * Level/persistent interrupts have a special requirement that 268aaa8666aSCristian Birsan * the condition generating the interrupt be cleared before the 269aaa8666aSCristian Birsan * interrupt flag (ifs) can be cleared. chip.irq_eoi is used to 270aaa8666aSCristian Birsan * complete the interrupt with an ack. 271aaa8666aSCristian Birsan */ 272aaa8666aSCristian Birsan gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; 273aaa8666aSCristian Birsan gc->chip_types[0].handler = handle_fasteoi_irq; 274aaa8666aSCristian Birsan gc->chip_types[0].regs.ack = ifsclr; 275aaa8666aSCristian Birsan gc->chip_types[0].regs.mask = iec; 276aaa8666aSCristian Birsan gc->chip_types[0].chip.name = "evic-level"; 277aaa8666aSCristian Birsan gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; 278aaa8666aSCristian Birsan gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; 279aaa8666aSCristian Birsan gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; 280aaa8666aSCristian Birsan gc->chip_types[0].chip.flags = IRQCHIP_SKIP_SET_WAKE; 281aaa8666aSCristian Birsan 282aaa8666aSCristian Birsan /* Edge interrupts */ 283aaa8666aSCristian Birsan gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; 284aaa8666aSCristian Birsan gc->chip_types[1].handler = handle_edge_irq; 285aaa8666aSCristian Birsan gc->chip_types[1].regs.ack = ifsclr; 286aaa8666aSCristian Birsan gc->chip_types[1].regs.mask = iec; 287aaa8666aSCristian Birsan gc->chip_types[1].chip.name = "evic-edge"; 288aaa8666aSCristian Birsan gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; 289aaa8666aSCristian Birsan gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; 290aaa8666aSCristian Birsan gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; 291aaa8666aSCristian Birsan gc->chip_types[1].chip.irq_set_type = pic32_set_type_edge; 292aaa8666aSCristian Birsan gc->chip_types[1].chip.flags = IRQCHIP_SKIP_SET_WAKE; 293aaa8666aSCristian Birsan 294aaa8666aSCristian Birsan gc->private = &priv[i]; 295aaa8666aSCristian Birsan } 296aaa8666aSCristian Birsan 297aaa8666aSCristian Birsan irq_set_default_host(evic_irq_domain); 298aaa8666aSCristian Birsan 299aaa8666aSCristian Birsan /* 300aaa8666aSCristian Birsan * External interrupts have software configurable edge polarity. These 301aaa8666aSCristian Birsan * interrupts are defined in DT allowing polarity to be configured only 302aaa8666aSCristian Birsan * for these interrupts when requested. 303aaa8666aSCristian Birsan */ 304aaa8666aSCristian Birsan pic32_ext_irq_of_init(evic_irq_domain); 305aaa8666aSCristian Birsan 306aaa8666aSCristian Birsan return 0; 307aaa8666aSCristian Birsan 308aaa8666aSCristian Birsan err_domain_remove: 309aaa8666aSCristian Birsan irq_domain_remove(evic_irq_domain); 310aaa8666aSCristian Birsan 311aaa8666aSCristian Birsan err_free_priv: 312aaa8666aSCristian Birsan kfree(priv); 313aaa8666aSCristian Birsan 314aaa8666aSCristian Birsan err_iounmap: 315aaa8666aSCristian Birsan iounmap(evic_base); 316aaa8666aSCristian Birsan 317aaa8666aSCristian Birsan return ret; 318aaa8666aSCristian Birsan } 319aaa8666aSCristian Birsan 320aaa8666aSCristian Birsan IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init); 321