1aaa8666aSCristian Birsan /* 2aaa8666aSCristian Birsan * Cristian Birsan <cristian.birsan@microchip.com> 3aaa8666aSCristian Birsan * Joshua Henderson <joshua.henderson@microchip.com> 4aaa8666aSCristian Birsan * Copyright (C) 2016 Microchip Technology Inc. All rights reserved. 5aaa8666aSCristian Birsan * 6aaa8666aSCristian Birsan * This program is free software; you can redistribute it and/or modify it 7aaa8666aSCristian Birsan * under the terms of the GNU General Public License as published by the 8aaa8666aSCristian Birsan * Free Software Foundation; either version 2 of the License, or (at your 9aaa8666aSCristian Birsan * option) any later version. 10aaa8666aSCristian Birsan */ 11aaa8666aSCristian Birsan #include <linux/kernel.h> 12aaa8666aSCristian Birsan #include <linux/module.h> 13aaa8666aSCristian Birsan #include <linux/interrupt.h> 14aaa8666aSCristian Birsan #include <linux/irqdomain.h> 15aaa8666aSCristian Birsan #include <linux/of_address.h> 16aaa8666aSCristian Birsan #include <linux/slab.h> 17aaa8666aSCristian Birsan #include <linux/io.h> 18aaa8666aSCristian Birsan #include <linux/irqchip.h> 19aaa8666aSCristian Birsan #include <linux/irq.h> 20aaa8666aSCristian Birsan 21aaa8666aSCristian Birsan #include <asm/irq.h> 22aaa8666aSCristian Birsan #include <asm/traps.h> 23aaa8666aSCristian Birsan #include <asm/mach-pic32/pic32.h> 24aaa8666aSCristian Birsan 25aaa8666aSCristian Birsan #define REG_INTCON 0x0000 26aaa8666aSCristian Birsan #define REG_INTSTAT 0x0020 27aaa8666aSCristian Birsan #define REG_IFS_OFFSET 0x0040 28aaa8666aSCristian Birsan #define REG_IEC_OFFSET 0x00C0 29aaa8666aSCristian Birsan #define REG_IPC_OFFSET 0x0140 30aaa8666aSCristian Birsan #define REG_OFF_OFFSET 0x0540 31aaa8666aSCristian Birsan 32aaa8666aSCristian Birsan #define MAJPRI_MASK 0x07 33aaa8666aSCristian Birsan #define SUBPRI_MASK 0x03 34aaa8666aSCristian Birsan #define PRIORITY_MASK 0x1F 35aaa8666aSCristian Birsan 36aaa8666aSCristian Birsan #define PIC32_INT_PRI(pri, subpri) \ 37aaa8666aSCristian Birsan ((((pri) & MAJPRI_MASK) << 2) | ((subpri) & SUBPRI_MASK)) 38aaa8666aSCristian Birsan 39aaa8666aSCristian Birsan struct evic_chip_data { 40aaa8666aSCristian Birsan u32 irq_types[NR_IRQS]; 41aaa8666aSCristian Birsan u32 ext_irqs[8]; 42aaa8666aSCristian Birsan }; 43aaa8666aSCristian Birsan 44aaa8666aSCristian Birsan static struct irq_domain *evic_irq_domain; 45aaa8666aSCristian Birsan static void __iomem *evic_base; 46aaa8666aSCristian Birsan 47aaa8666aSCristian Birsan asmlinkage void __weak plat_irq_dispatch(void) 48aaa8666aSCristian Birsan { 49aaa8666aSCristian Birsan unsigned int irq, hwirq; 50aaa8666aSCristian Birsan 51aaa8666aSCristian Birsan hwirq = readl(evic_base + REG_INTSTAT) & 0xFF; 52aaa8666aSCristian Birsan irq = irq_linear_revmap(evic_irq_domain, hwirq); 53aaa8666aSCristian Birsan do_IRQ(irq); 54aaa8666aSCristian Birsan } 55aaa8666aSCristian Birsan 56aaa8666aSCristian Birsan static struct evic_chip_data *irqd_to_priv(struct irq_data *data) 57aaa8666aSCristian Birsan { 58aaa8666aSCristian Birsan return (struct evic_chip_data *)data->domain->host_data; 59aaa8666aSCristian Birsan } 60aaa8666aSCristian Birsan 61aaa8666aSCristian Birsan static int pic32_set_ext_polarity(int bit, u32 type) 62aaa8666aSCristian Birsan { 63aaa8666aSCristian Birsan /* 64aaa8666aSCristian Birsan * External interrupts can be either edge rising or edge falling, 65aaa8666aSCristian Birsan * but not both. 66aaa8666aSCristian Birsan */ 67aaa8666aSCristian Birsan switch (type) { 68aaa8666aSCristian Birsan case IRQ_TYPE_EDGE_RISING: 69aaa8666aSCristian Birsan writel(BIT(bit), evic_base + PIC32_SET(REG_INTCON)); 70aaa8666aSCristian Birsan break; 71aaa8666aSCristian Birsan case IRQ_TYPE_EDGE_FALLING: 72aaa8666aSCristian Birsan writel(BIT(bit), evic_base + PIC32_CLR(REG_INTCON)); 73aaa8666aSCristian Birsan break; 74aaa8666aSCristian Birsan default: 75aaa8666aSCristian Birsan return -EINVAL; 76aaa8666aSCristian Birsan } 77aaa8666aSCristian Birsan 78aaa8666aSCristian Birsan return 0; 79aaa8666aSCristian Birsan } 80aaa8666aSCristian Birsan 81aaa8666aSCristian Birsan static int pic32_set_type_edge(struct irq_data *data, 82aaa8666aSCristian Birsan unsigned int flow_type) 83aaa8666aSCristian Birsan { 84aaa8666aSCristian Birsan struct evic_chip_data *priv = irqd_to_priv(data); 85aaa8666aSCristian Birsan int ret; 86aaa8666aSCristian Birsan int i; 87aaa8666aSCristian Birsan 88aaa8666aSCristian Birsan if (!(flow_type & IRQ_TYPE_EDGE_BOTH)) 89aaa8666aSCristian Birsan return -EBADR; 90aaa8666aSCristian Birsan 91aaa8666aSCristian Birsan /* set polarity for external interrupts only */ 92aaa8666aSCristian Birsan for (i = 0; i < ARRAY_SIZE(priv->ext_irqs); i++) { 93aaa8666aSCristian Birsan if (priv->ext_irqs[i] == data->hwirq) { 940de6b997SJoshua Henderson ret = pic32_set_ext_polarity(i, flow_type); 95aaa8666aSCristian Birsan if (ret) 96aaa8666aSCristian Birsan return ret; 97aaa8666aSCristian Birsan } 98aaa8666aSCristian Birsan } 99aaa8666aSCristian Birsan 100aaa8666aSCristian Birsan irqd_set_trigger_type(data, flow_type); 101aaa8666aSCristian Birsan 102aaa8666aSCristian Birsan return IRQ_SET_MASK_OK; 103aaa8666aSCristian Birsan } 104aaa8666aSCristian Birsan 105aaa8666aSCristian Birsan static void pic32_bind_evic_interrupt(int irq, int set) 106aaa8666aSCristian Birsan { 107aaa8666aSCristian Birsan writel(set, evic_base + REG_OFF_OFFSET + irq * 4); 108aaa8666aSCristian Birsan } 109aaa8666aSCristian Birsan 110aaa8666aSCristian Birsan static void pic32_set_irq_priority(int irq, int priority) 111aaa8666aSCristian Birsan { 112aaa8666aSCristian Birsan u32 reg, shift; 113aaa8666aSCristian Birsan 114aaa8666aSCristian Birsan reg = irq / 4; 115aaa8666aSCristian Birsan shift = (irq % 4) * 8; 116aaa8666aSCristian Birsan 117aaa8666aSCristian Birsan writel(PRIORITY_MASK << shift, 118aaa8666aSCristian Birsan evic_base + PIC32_CLR(REG_IPC_OFFSET + reg * 0x10)); 119aaa8666aSCristian Birsan writel(priority << shift, 120aaa8666aSCristian Birsan evic_base + PIC32_SET(REG_IPC_OFFSET + reg * 0x10)); 121aaa8666aSCristian Birsan } 122aaa8666aSCristian Birsan 123aaa8666aSCristian Birsan #define IRQ_REG_MASK(_hwirq, _reg, _mask) \ 124aaa8666aSCristian Birsan do { \ 125aaa8666aSCristian Birsan _reg = _hwirq / 32; \ 126aaa8666aSCristian Birsan _mask = 1 << (_hwirq % 32); \ 127aaa8666aSCristian Birsan } while (0) 128aaa8666aSCristian Birsan 129aaa8666aSCristian Birsan static int pic32_irq_domain_map(struct irq_domain *d, unsigned int virq, 130aaa8666aSCristian Birsan irq_hw_number_t hw) 131aaa8666aSCristian Birsan { 132aaa8666aSCristian Birsan struct evic_chip_data *priv = d->host_data; 133aaa8666aSCristian Birsan struct irq_data *data; 134aaa8666aSCristian Birsan int ret; 135aaa8666aSCristian Birsan u32 iecclr, ifsclr; 136aaa8666aSCristian Birsan u32 reg, mask; 137aaa8666aSCristian Birsan 138aaa8666aSCristian Birsan ret = irq_map_generic_chip(d, virq, hw); 139aaa8666aSCristian Birsan if (ret) 140aaa8666aSCristian Birsan return ret; 141aaa8666aSCristian Birsan 142aaa8666aSCristian Birsan /* 143aaa8666aSCristian Birsan * Piggyback on xlate function to move to an alternate chip as necessary 144aaa8666aSCristian Birsan * at time of mapping instead of allowing the flow handler/chip to be 145aaa8666aSCristian Birsan * changed later. This requires all interrupts to be configured through 146aaa8666aSCristian Birsan * DT. 147aaa8666aSCristian Birsan */ 148aaa8666aSCristian Birsan if (priv->irq_types[hw] & IRQ_TYPE_SENSE_MASK) { 149aaa8666aSCristian Birsan data = irq_domain_get_irq_data(d, virq); 150aaa8666aSCristian Birsan irqd_set_trigger_type(data, priv->irq_types[hw]); 151aaa8666aSCristian Birsan irq_setup_alt_chip(data, priv->irq_types[hw]); 152aaa8666aSCristian Birsan } 153aaa8666aSCristian Birsan 154aaa8666aSCristian Birsan IRQ_REG_MASK(hw, reg, mask); 155aaa8666aSCristian Birsan 156aaa8666aSCristian Birsan iecclr = PIC32_CLR(REG_IEC_OFFSET + reg * 0x10); 157aaa8666aSCristian Birsan ifsclr = PIC32_CLR(REG_IFS_OFFSET + reg * 0x10); 158aaa8666aSCristian Birsan 159aaa8666aSCristian Birsan /* mask and clear flag */ 160aaa8666aSCristian Birsan writel(mask, evic_base + iecclr); 161aaa8666aSCristian Birsan writel(mask, evic_base + ifsclr); 162aaa8666aSCristian Birsan 163aaa8666aSCristian Birsan /* default priority is required */ 164aaa8666aSCristian Birsan pic32_set_irq_priority(hw, PIC32_INT_PRI(2, 0)); 165aaa8666aSCristian Birsan 166aaa8666aSCristian Birsan return ret; 167aaa8666aSCristian Birsan } 168aaa8666aSCristian Birsan 169aaa8666aSCristian Birsan int pic32_irq_domain_xlate(struct irq_domain *d, struct device_node *ctrlr, 170aaa8666aSCristian Birsan const u32 *intspec, unsigned int intsize, 171aaa8666aSCristian Birsan irq_hw_number_t *out_hwirq, unsigned int *out_type) 172aaa8666aSCristian Birsan { 173aaa8666aSCristian Birsan struct evic_chip_data *priv = d->host_data; 174aaa8666aSCristian Birsan 175aaa8666aSCristian Birsan if (WARN_ON(intsize < 2)) 176aaa8666aSCristian Birsan return -EINVAL; 177aaa8666aSCristian Birsan 178aaa8666aSCristian Birsan if (WARN_ON(intspec[0] >= NR_IRQS)) 179aaa8666aSCristian Birsan return -EINVAL; 180aaa8666aSCristian Birsan 181aaa8666aSCristian Birsan *out_hwirq = intspec[0]; 182aaa8666aSCristian Birsan *out_type = intspec[1] & IRQ_TYPE_SENSE_MASK; 183aaa8666aSCristian Birsan 184aaa8666aSCristian Birsan priv->irq_types[intspec[0]] = intspec[1] & IRQ_TYPE_SENSE_MASK; 185aaa8666aSCristian Birsan 186aaa8666aSCristian Birsan return 0; 187aaa8666aSCristian Birsan } 188aaa8666aSCristian Birsan 189aaa8666aSCristian Birsan static const struct irq_domain_ops pic32_irq_domain_ops = { 190aaa8666aSCristian Birsan .map = pic32_irq_domain_map, 191aaa8666aSCristian Birsan .xlate = pic32_irq_domain_xlate, 192aaa8666aSCristian Birsan }; 193aaa8666aSCristian Birsan 194aaa8666aSCristian Birsan static void __init pic32_ext_irq_of_init(struct irq_domain *domain) 195aaa8666aSCristian Birsan { 196aaa8666aSCristian Birsan struct device_node *node = irq_domain_get_of_node(domain); 197aaa8666aSCristian Birsan struct evic_chip_data *priv = domain->host_data; 198aaa8666aSCristian Birsan struct property *prop; 199aaa8666aSCristian Birsan const __le32 *p; 200aaa8666aSCristian Birsan u32 hwirq; 201aaa8666aSCristian Birsan int i = 0; 202aaa8666aSCristian Birsan const char *pname = "microchip,external-irqs"; 203aaa8666aSCristian Birsan 204aaa8666aSCristian Birsan of_property_for_each_u32(node, pname, prop, p, hwirq) { 205aaa8666aSCristian Birsan if (i >= ARRAY_SIZE(priv->ext_irqs)) { 206aaa8666aSCristian Birsan pr_warn("More than %d external irq, skip rest\n", 207aaa8666aSCristian Birsan ARRAY_SIZE(priv->ext_irqs)); 208aaa8666aSCristian Birsan break; 209aaa8666aSCristian Birsan } 210aaa8666aSCristian Birsan 211aaa8666aSCristian Birsan priv->ext_irqs[i] = hwirq; 212aaa8666aSCristian Birsan i++; 213aaa8666aSCristian Birsan } 214aaa8666aSCristian Birsan } 215aaa8666aSCristian Birsan 216aaa8666aSCristian Birsan static int __init pic32_of_init(struct device_node *node, 217aaa8666aSCristian Birsan struct device_node *parent) 218aaa8666aSCristian Birsan { 219aaa8666aSCristian Birsan struct irq_chip_generic *gc; 220aaa8666aSCristian Birsan struct evic_chip_data *priv; 221aaa8666aSCristian Birsan unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN; 222aaa8666aSCristian Birsan int nchips, ret; 223aaa8666aSCristian Birsan int i; 224aaa8666aSCristian Birsan 225aaa8666aSCristian Birsan nchips = DIV_ROUND_UP(NR_IRQS, 32); 226aaa8666aSCristian Birsan 227aaa8666aSCristian Birsan evic_base = of_iomap(node, 0); 228aaa8666aSCristian Birsan if (!evic_base) 229aaa8666aSCristian Birsan return -ENOMEM; 230aaa8666aSCristian Birsan 231aaa8666aSCristian Birsan priv = kcalloc(nchips, sizeof(*priv), GFP_KERNEL); 232aaa8666aSCristian Birsan if (!priv) { 233aaa8666aSCristian Birsan ret = -ENOMEM; 234aaa8666aSCristian Birsan goto err_iounmap; 235aaa8666aSCristian Birsan } 236aaa8666aSCristian Birsan 237aaa8666aSCristian Birsan evic_irq_domain = irq_domain_add_linear(node, nchips * 32, 238aaa8666aSCristian Birsan &pic32_irq_domain_ops, 239aaa8666aSCristian Birsan priv); 240aaa8666aSCristian Birsan if (!evic_irq_domain) { 241aaa8666aSCristian Birsan ret = -ENOMEM; 242aaa8666aSCristian Birsan goto err_free_priv; 243aaa8666aSCristian Birsan } 244aaa8666aSCristian Birsan 245aaa8666aSCristian Birsan /* 246aaa8666aSCristian Birsan * The PIC32 EVIC has a linear list of irqs and the type of each 247aaa8666aSCristian Birsan * irq is determined by the hardware peripheral the EVIC is arbitrating. 248aaa8666aSCristian Birsan * These irq types are defined in the datasheet as "persistent" and 249aaa8666aSCristian Birsan * "non-persistent" which are mapped here to level and edge 250aaa8666aSCristian Birsan * respectively. To manage the different flow handler requirements of 251aaa8666aSCristian Birsan * each irq type, different chip_types are used. 252aaa8666aSCristian Birsan */ 253aaa8666aSCristian Birsan ret = irq_alloc_domain_generic_chips(evic_irq_domain, 32, 2, 254aaa8666aSCristian Birsan "evic-level", handle_level_irq, 255aaa8666aSCristian Birsan clr, 0, 0); 256aaa8666aSCristian Birsan if (ret) 257aaa8666aSCristian Birsan goto err_domain_remove; 258aaa8666aSCristian Birsan 259aaa8666aSCristian Birsan board_bind_eic_interrupt = &pic32_bind_evic_interrupt; 260aaa8666aSCristian Birsan 261aaa8666aSCristian Birsan for (i = 0; i < nchips; i++) { 262aaa8666aSCristian Birsan u32 ifsclr = PIC32_CLR(REG_IFS_OFFSET + (i * 0x10)); 263aaa8666aSCristian Birsan u32 iec = REG_IEC_OFFSET + (i * 0x10); 264aaa8666aSCristian Birsan 265aaa8666aSCristian Birsan gc = irq_get_domain_generic_chip(evic_irq_domain, i * 32); 266aaa8666aSCristian Birsan 267aaa8666aSCristian Birsan gc->reg_base = evic_base; 268aaa8666aSCristian Birsan gc->unused = 0; 269aaa8666aSCristian Birsan 270aaa8666aSCristian Birsan /* 271aaa8666aSCristian Birsan * Level/persistent interrupts have a special requirement that 272aaa8666aSCristian Birsan * the condition generating the interrupt be cleared before the 273aaa8666aSCristian Birsan * interrupt flag (ifs) can be cleared. chip.irq_eoi is used to 274aaa8666aSCristian Birsan * complete the interrupt with an ack. 275aaa8666aSCristian Birsan */ 276aaa8666aSCristian Birsan gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK; 277aaa8666aSCristian Birsan gc->chip_types[0].handler = handle_fasteoi_irq; 278aaa8666aSCristian Birsan gc->chip_types[0].regs.ack = ifsclr; 279aaa8666aSCristian Birsan gc->chip_types[0].regs.mask = iec; 280aaa8666aSCristian Birsan gc->chip_types[0].chip.name = "evic-level"; 281aaa8666aSCristian Birsan gc->chip_types[0].chip.irq_eoi = irq_gc_ack_set_bit; 282aaa8666aSCristian Birsan gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit; 283aaa8666aSCristian Birsan gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit; 284aaa8666aSCristian Birsan gc->chip_types[0].chip.flags = IRQCHIP_SKIP_SET_WAKE; 285aaa8666aSCristian Birsan 286aaa8666aSCristian Birsan /* Edge interrupts */ 287aaa8666aSCristian Birsan gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH; 288aaa8666aSCristian Birsan gc->chip_types[1].handler = handle_edge_irq; 289aaa8666aSCristian Birsan gc->chip_types[1].regs.ack = ifsclr; 290aaa8666aSCristian Birsan gc->chip_types[1].regs.mask = iec; 291aaa8666aSCristian Birsan gc->chip_types[1].chip.name = "evic-edge"; 292aaa8666aSCristian Birsan gc->chip_types[1].chip.irq_ack = irq_gc_ack_set_bit; 293aaa8666aSCristian Birsan gc->chip_types[1].chip.irq_mask = irq_gc_mask_clr_bit; 294aaa8666aSCristian Birsan gc->chip_types[1].chip.irq_unmask = irq_gc_mask_set_bit; 295aaa8666aSCristian Birsan gc->chip_types[1].chip.irq_set_type = pic32_set_type_edge; 296aaa8666aSCristian Birsan gc->chip_types[1].chip.flags = IRQCHIP_SKIP_SET_WAKE; 297aaa8666aSCristian Birsan 298aaa8666aSCristian Birsan gc->private = &priv[i]; 299aaa8666aSCristian Birsan } 300aaa8666aSCristian Birsan 301aaa8666aSCristian Birsan irq_set_default_host(evic_irq_domain); 302aaa8666aSCristian Birsan 303aaa8666aSCristian Birsan /* 304aaa8666aSCristian Birsan * External interrupts have software configurable edge polarity. These 305aaa8666aSCristian Birsan * interrupts are defined in DT allowing polarity to be configured only 306aaa8666aSCristian Birsan * for these interrupts when requested. 307aaa8666aSCristian Birsan */ 308aaa8666aSCristian Birsan pic32_ext_irq_of_init(evic_irq_domain); 309aaa8666aSCristian Birsan 310aaa8666aSCristian Birsan return 0; 311aaa8666aSCristian Birsan 312aaa8666aSCristian Birsan err_domain_remove: 313aaa8666aSCristian Birsan irq_domain_remove(evic_irq_domain); 314aaa8666aSCristian Birsan 315aaa8666aSCristian Birsan err_free_priv: 316aaa8666aSCristian Birsan kfree(priv); 317aaa8666aSCristian Birsan 318aaa8666aSCristian Birsan err_iounmap: 319aaa8666aSCristian Birsan iounmap(evic_base); 320aaa8666aSCristian Birsan 321aaa8666aSCristian Birsan return ret; 322aaa8666aSCristian Birsan } 323aaa8666aSCristian Birsan 324aaa8666aSCristian Birsan IRQCHIP_DECLARE(pic32_evic, "microchip,pic32mzda-evic", pic32_of_init); 325