18598066cSFelipe Balbi /* 28598066cSFelipe Balbi * linux/arch/arm/mach-omap2/irq.c 38598066cSFelipe Balbi * 48598066cSFelipe Balbi * Interrupt handler for OMAP2 boards. 58598066cSFelipe Balbi * 68598066cSFelipe Balbi * Copyright (C) 2005 Nokia Corporation 78598066cSFelipe Balbi * Author: Paul Mundt <paul.mundt@nokia.com> 88598066cSFelipe Balbi * 98598066cSFelipe Balbi * This file is subject to the terms and conditions of the GNU General Public 108598066cSFelipe Balbi * License. See the file "COPYING" in the main directory of this archive 118598066cSFelipe Balbi * for more details. 128598066cSFelipe Balbi */ 138598066cSFelipe Balbi #include <linux/kernel.h> 148598066cSFelipe Balbi #include <linux/module.h> 158598066cSFelipe Balbi #include <linux/init.h> 168598066cSFelipe Balbi #include <linux/interrupt.h> 178598066cSFelipe Balbi #include <linux/io.h> 188598066cSFelipe Balbi 198598066cSFelipe Balbi #include <asm/exception.h> 208598066cSFelipe Balbi #include <linux/irqdomain.h> 218598066cSFelipe Balbi #include <linux/of.h> 228598066cSFelipe Balbi #include <linux/of_address.h> 238598066cSFelipe Balbi #include <linux/of_irq.h> 248598066cSFelipe Balbi 258598066cSFelipe Balbi #include "irqchip.h" 268598066cSFelipe Balbi 278598066cSFelipe Balbi /* Define these here for now until we drop all board-files */ 288598066cSFelipe Balbi #define OMAP24XX_IC_BASE 0x480fe000 298598066cSFelipe Balbi #define OMAP34XX_IC_BASE 0x48200000 308598066cSFelipe Balbi 318598066cSFelipe Balbi /* selected INTC register offsets */ 328598066cSFelipe Balbi 338598066cSFelipe Balbi #define INTC_REVISION 0x0000 348598066cSFelipe Balbi #define INTC_SYSCONFIG 0x0010 358598066cSFelipe Balbi #define INTC_SYSSTATUS 0x0014 368598066cSFelipe Balbi #define INTC_SIR 0x0040 378598066cSFelipe Balbi #define INTC_CONTROL 0x0048 388598066cSFelipe Balbi #define INTC_PROTECTION 0x004C 398598066cSFelipe Balbi #define INTC_IDLE 0x0050 408598066cSFelipe Balbi #define INTC_THRESHOLD 0x0068 418598066cSFelipe Balbi #define INTC_MIR0 0x0084 428598066cSFelipe Balbi #define INTC_MIR_CLEAR0 0x0088 438598066cSFelipe Balbi #define INTC_MIR_SET0 0x008c 448598066cSFelipe Balbi #define INTC_PENDING_IRQ0 0x0098 458598066cSFelipe Balbi #define INTC_PENDING_IRQ1 0x00b8 468598066cSFelipe Balbi #define INTC_PENDING_IRQ2 0x00d8 478598066cSFelipe Balbi #define INTC_PENDING_IRQ3 0x00f8 488598066cSFelipe Balbi #define INTC_ILR0 0x0100 498598066cSFelipe Balbi 508598066cSFelipe Balbi #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ 518598066cSFelipe Balbi #define INTCPS_NR_ILR_REGS 128 5274b6c8efSFelipe Balbi #define INTCPS_NR_MIR_REGS 4 538598066cSFelipe Balbi 54b3079149SFelipe Balbi #define INTC_IDLE_FUNCIDLE (1 << 0) 55b3079149SFelipe Balbi #define INTC_IDLE_TURBO (1 << 1) 56b3079149SFelipe Balbi 579836ee9fSFelipe Balbi #define INTC_PROTECTION_ENABLE (1 << 0) 589836ee9fSFelipe Balbi 598598066cSFelipe Balbi struct omap_intc_regs { 608598066cSFelipe Balbi u32 sysconfig; 618598066cSFelipe Balbi u32 protection; 628598066cSFelipe Balbi u32 idle; 638598066cSFelipe Balbi u32 threshold; 648598066cSFelipe Balbi u32 ilr[INTCPS_NR_ILR_REGS]; 658598066cSFelipe Balbi u32 mir[INTCPS_NR_MIR_REGS]; 668598066cSFelipe Balbi }; 678598066cSFelipe Balbi static struct omap_intc_regs intc_context; 688598066cSFelipe Balbi 698598066cSFelipe Balbi static struct irq_domain *domain; 708598066cSFelipe Balbi static void __iomem *omap_irq_base; 718598066cSFelipe Balbi static int omap_nr_pending = 3; 728598066cSFelipe Balbi static int omap_nr_irqs = 96; 738598066cSFelipe Balbi 748598066cSFelipe Balbi static void intc_writel(u32 reg, u32 val) 758598066cSFelipe Balbi { 768598066cSFelipe Balbi writel_relaxed(val, omap_irq_base + reg); 778598066cSFelipe Balbi } 788598066cSFelipe Balbi 798598066cSFelipe Balbi static u32 intc_readl(u32 reg) 808598066cSFelipe Balbi { 818598066cSFelipe Balbi return readl_relaxed(omap_irq_base + reg); 828598066cSFelipe Balbi } 838598066cSFelipe Balbi 848598066cSFelipe Balbi void omap_intc_save_context(void) 858598066cSFelipe Balbi { 868598066cSFelipe Balbi int i; 878598066cSFelipe Balbi 888598066cSFelipe Balbi intc_context.sysconfig = 898598066cSFelipe Balbi intc_readl(INTC_SYSCONFIG); 908598066cSFelipe Balbi intc_context.protection = 918598066cSFelipe Balbi intc_readl(INTC_PROTECTION); 928598066cSFelipe Balbi intc_context.idle = 938598066cSFelipe Balbi intc_readl(INTC_IDLE); 948598066cSFelipe Balbi intc_context.threshold = 958598066cSFelipe Balbi intc_readl(INTC_THRESHOLD); 968598066cSFelipe Balbi 978598066cSFelipe Balbi for (i = 0; i < omap_nr_irqs; i++) 988598066cSFelipe Balbi intc_context.ilr[i] = 998598066cSFelipe Balbi intc_readl((INTC_ILR0 + 0x4 * i)); 1008598066cSFelipe Balbi for (i = 0; i < INTCPS_NR_MIR_REGS; i++) 1018598066cSFelipe Balbi intc_context.mir[i] = 1028598066cSFelipe Balbi intc_readl(INTC_MIR0 + (0x20 * i)); 1038598066cSFelipe Balbi } 1048598066cSFelipe Balbi 1058598066cSFelipe Balbi void omap_intc_restore_context(void) 1068598066cSFelipe Balbi { 1078598066cSFelipe Balbi int i; 1088598066cSFelipe Balbi 1098598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); 1108598066cSFelipe Balbi intc_writel(INTC_PROTECTION, intc_context.protection); 1118598066cSFelipe Balbi intc_writel(INTC_IDLE, intc_context.idle); 1128598066cSFelipe Balbi intc_writel(INTC_THRESHOLD, intc_context.threshold); 1138598066cSFelipe Balbi 1148598066cSFelipe Balbi for (i = 0; i < omap_nr_irqs; i++) 1158598066cSFelipe Balbi intc_writel(INTC_ILR0 + 0x4 * i, 1168598066cSFelipe Balbi intc_context.ilr[i]); 1178598066cSFelipe Balbi 1188598066cSFelipe Balbi for (i = 0; i < INTCPS_NR_MIR_REGS; i++) 1198598066cSFelipe Balbi intc_writel(INTC_MIR0 + 0x20 * i, 1208598066cSFelipe Balbi intc_context.mir[i]); 1218598066cSFelipe Balbi /* MIRs are saved and restore with other PRCM registers */ 1228598066cSFelipe Balbi } 1238598066cSFelipe Balbi 1248598066cSFelipe Balbi void omap3_intc_prepare_idle(void) 1258598066cSFelipe Balbi { 1268598066cSFelipe Balbi /* 1278598066cSFelipe Balbi * Disable autoidle as it can stall interrupt controller, 1288598066cSFelipe Balbi * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) 1298598066cSFelipe Balbi */ 1308598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 0); 131b3079149SFelipe Balbi intc_writel(INTC_IDLE, INTC_IDLE_TURBO); 1328598066cSFelipe Balbi } 1338598066cSFelipe Balbi 1348598066cSFelipe Balbi void omap3_intc_resume_idle(void) 1358598066cSFelipe Balbi { 1368598066cSFelipe Balbi /* Re-enable autoidle */ 1378598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 1); 138b3079149SFelipe Balbi intc_writel(INTC_IDLE, 0); 1398598066cSFelipe Balbi } 1408598066cSFelipe Balbi 1418598066cSFelipe Balbi /* XXX: FIQ and additional INTC support (only MPU at the moment) */ 1428598066cSFelipe Balbi static void omap_ack_irq(struct irq_data *d) 1438598066cSFelipe Balbi { 1448598066cSFelipe Balbi intc_writel(INTC_CONTROL, 0x1); 1458598066cSFelipe Balbi } 1468598066cSFelipe Balbi 1478598066cSFelipe Balbi static void omap_mask_ack_irq(struct irq_data *d) 1488598066cSFelipe Balbi { 1498598066cSFelipe Balbi irq_gc_mask_disable_reg(d); 1508598066cSFelipe Balbi omap_ack_irq(d); 1518598066cSFelipe Balbi } 1528598066cSFelipe Balbi 1538598066cSFelipe Balbi static void __init omap_irq_soft_reset(void) 1548598066cSFelipe Balbi { 1558598066cSFelipe Balbi unsigned long tmp; 1568598066cSFelipe Balbi 1578598066cSFelipe Balbi tmp = intc_readl(INTC_REVISION) & 0xff; 1588598066cSFelipe Balbi 1598598066cSFelipe Balbi pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", 1608598066cSFelipe Balbi omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs); 1618598066cSFelipe Balbi 1628598066cSFelipe Balbi tmp = intc_readl(INTC_SYSCONFIG); 1638598066cSFelipe Balbi tmp |= 1 << 1; /* soft reset */ 1648598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, tmp); 1658598066cSFelipe Balbi 1668598066cSFelipe Balbi while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) 1678598066cSFelipe Balbi /* Wait for reset to complete */; 1688598066cSFelipe Balbi 1698598066cSFelipe Balbi /* Enable autoidle */ 1708598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 1 << 0); 1718598066cSFelipe Balbi } 1728598066cSFelipe Balbi 1738598066cSFelipe Balbi int omap_irq_pending(void) 1748598066cSFelipe Balbi { 1756bd0f16eSFelipe Balbi int i; 1768598066cSFelipe Balbi 1776bd0f16eSFelipe Balbi for (i = 0; i < omap_nr_pending; i++) 1786bd0f16eSFelipe Balbi if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i))) 1798598066cSFelipe Balbi return 1; 1808598066cSFelipe Balbi return 0; 1818598066cSFelipe Balbi } 1828598066cSFelipe Balbi 1838598066cSFelipe Balbi void omap3_intc_suspend(void) 1848598066cSFelipe Balbi { 1858598066cSFelipe Balbi /* A pending interrupt would prevent OMAP from entering suspend */ 1868598066cSFelipe Balbi omap_ack_irq(NULL); 1878598066cSFelipe Balbi } 1888598066cSFelipe Balbi 1898598066cSFelipe Balbi static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base) 1908598066cSFelipe Balbi { 1918598066cSFelipe Balbi int ret; 1928598066cSFelipe Balbi int i; 1938598066cSFelipe Balbi 1948598066cSFelipe Balbi ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC", 1958598066cSFelipe Balbi handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE, 1968598066cSFelipe Balbi IRQ_LEVEL, 0); 1978598066cSFelipe Balbi if (ret) { 1988598066cSFelipe Balbi pr_warn("Failed to allocate irq chips\n"); 1998598066cSFelipe Balbi return ret; 2008598066cSFelipe Balbi } 2018598066cSFelipe Balbi 2028598066cSFelipe Balbi for (i = 0; i < omap_nr_pending; i++) { 2038598066cSFelipe Balbi struct irq_chip_generic *gc; 2048598066cSFelipe Balbi struct irq_chip_type *ct; 2058598066cSFelipe Balbi 2068598066cSFelipe Balbi gc = irq_get_domain_generic_chip(d, 32 * i); 2078598066cSFelipe Balbi gc->reg_base = base; 2088598066cSFelipe Balbi ct = gc->chip_types; 2098598066cSFelipe Balbi 2108598066cSFelipe Balbi ct->type = IRQ_TYPE_LEVEL_MASK; 2118598066cSFelipe Balbi ct->handler = handle_level_irq; 2128598066cSFelipe Balbi 2138598066cSFelipe Balbi ct->chip.irq_ack = omap_mask_ack_irq; 2148598066cSFelipe Balbi ct->chip.irq_mask = irq_gc_mask_disable_reg; 2158598066cSFelipe Balbi ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 2168598066cSFelipe Balbi 2178598066cSFelipe Balbi ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; 2188598066cSFelipe Balbi 2198598066cSFelipe Balbi ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i; 2208598066cSFelipe Balbi ct->regs.disable = INTC_MIR_SET0 + 32 * i; 2218598066cSFelipe Balbi } 2228598066cSFelipe Balbi 2238598066cSFelipe Balbi return 0; 2248598066cSFelipe Balbi } 2258598066cSFelipe Balbi 2268598066cSFelipe Balbi static void __init omap_alloc_gc_legacy(void __iomem *base, 2278598066cSFelipe Balbi unsigned int irq_start, unsigned int num) 2288598066cSFelipe Balbi { 2298598066cSFelipe Balbi struct irq_chip_generic *gc; 2308598066cSFelipe Balbi struct irq_chip_type *ct; 2318598066cSFelipe Balbi 2328598066cSFelipe Balbi gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, 2338598066cSFelipe Balbi handle_level_irq); 2348598066cSFelipe Balbi ct = gc->chip_types; 2358598066cSFelipe Balbi ct->chip.irq_ack = omap_mask_ack_irq; 2368598066cSFelipe Balbi ct->chip.irq_mask = irq_gc_mask_disable_reg; 2378598066cSFelipe Balbi ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 2388598066cSFelipe Balbi ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; 2398598066cSFelipe Balbi 2408598066cSFelipe Balbi ct->regs.enable = INTC_MIR_CLEAR0; 2418598066cSFelipe Balbi ct->regs.disable = INTC_MIR_SET0; 2428598066cSFelipe Balbi irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 2438598066cSFelipe Balbi IRQ_NOREQUEST | IRQ_NOPROBE, 0); 2448598066cSFelipe Balbi } 2458598066cSFelipe Balbi 2468598066cSFelipe Balbi static int __init omap_init_irq_of(struct device_node *node) 2478598066cSFelipe Balbi { 2488598066cSFelipe Balbi int ret; 2498598066cSFelipe Balbi 2508598066cSFelipe Balbi omap_irq_base = of_iomap(node, 0); 2518598066cSFelipe Balbi if (WARN_ON(!omap_irq_base)) 2528598066cSFelipe Balbi return -ENOMEM; 2538598066cSFelipe Balbi 2548598066cSFelipe Balbi domain = irq_domain_add_linear(node, omap_nr_irqs, 2558598066cSFelipe Balbi &irq_generic_chip_ops, NULL); 2568598066cSFelipe Balbi 2578598066cSFelipe Balbi omap_irq_soft_reset(); 2588598066cSFelipe Balbi 2598598066cSFelipe Balbi ret = omap_alloc_gc_of(domain, omap_irq_base); 2608598066cSFelipe Balbi if (ret < 0) 2618598066cSFelipe Balbi irq_domain_remove(domain); 2628598066cSFelipe Balbi 2638598066cSFelipe Balbi return ret; 2648598066cSFelipe Balbi } 2658598066cSFelipe Balbi 2668598066cSFelipe Balbi static int __init omap_init_irq_legacy(u32 base) 2678598066cSFelipe Balbi { 2688598066cSFelipe Balbi int j, irq_base; 2698598066cSFelipe Balbi 2708598066cSFelipe Balbi omap_irq_base = ioremap(base, SZ_4K); 2718598066cSFelipe Balbi if (WARN_ON(!omap_irq_base)) 2728598066cSFelipe Balbi return -ENOMEM; 2738598066cSFelipe Balbi 2748598066cSFelipe Balbi irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0); 2758598066cSFelipe Balbi if (irq_base < 0) { 2768598066cSFelipe Balbi pr_warn("Couldn't allocate IRQ numbers\n"); 2778598066cSFelipe Balbi irq_base = 0; 2788598066cSFelipe Balbi } 2798598066cSFelipe Balbi 2808598066cSFelipe Balbi domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0, 2818598066cSFelipe Balbi &irq_domain_simple_ops, NULL); 2828598066cSFelipe Balbi 2838598066cSFelipe Balbi omap_irq_soft_reset(); 2848598066cSFelipe Balbi 2858598066cSFelipe Balbi for (j = 0; j < omap_nr_irqs; j += 32) 2868598066cSFelipe Balbi omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32); 2878598066cSFelipe Balbi 2888598066cSFelipe Balbi return 0; 2898598066cSFelipe Balbi } 2908598066cSFelipe Balbi 2919836ee9fSFelipe Balbi static void __init omap_irq_enable_protection(void) 2929836ee9fSFelipe Balbi { 2939836ee9fSFelipe Balbi u32 reg; 2949836ee9fSFelipe Balbi 2959836ee9fSFelipe Balbi reg = intc_readl(INTC_PROTECTION); 2969836ee9fSFelipe Balbi reg |= INTC_PROTECTION_ENABLE; 2979836ee9fSFelipe Balbi intc_writel(INTC_PROTECTION, reg); 2989836ee9fSFelipe Balbi } 2999836ee9fSFelipe Balbi 3008598066cSFelipe Balbi static int __init omap_init_irq(u32 base, struct device_node *node) 3018598066cSFelipe Balbi { 3029836ee9fSFelipe Balbi int ret; 3039836ee9fSFelipe Balbi 3048598066cSFelipe Balbi if (node) 3059836ee9fSFelipe Balbi ret = omap_init_irq_of(node); 3068598066cSFelipe Balbi else 3079836ee9fSFelipe Balbi ret = omap_init_irq_legacy(base); 3089836ee9fSFelipe Balbi 3099836ee9fSFelipe Balbi if (ret == 0) 3109836ee9fSFelipe Balbi omap_irq_enable_protection(); 3119836ee9fSFelipe Balbi 3129836ee9fSFelipe Balbi return ret; 3138598066cSFelipe Balbi } 3148598066cSFelipe Balbi 3158598066cSFelipe Balbi static asmlinkage void __exception_irq_entry 3168598066cSFelipe Balbi omap_intc_handle_irq(struct pt_regs *regs) 3178598066cSFelipe Balbi { 3188598066cSFelipe Balbi u32 irqnr = 0; 3198598066cSFelipe Balbi int handled_irq = 0; 3208598066cSFelipe Balbi int i; 3218598066cSFelipe Balbi 3228598066cSFelipe Balbi do { 3238598066cSFelipe Balbi for (i = 0; i < omap_nr_pending; i++) { 3248598066cSFelipe Balbi irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)); 3258598066cSFelipe Balbi if (irqnr) 3268598066cSFelipe Balbi goto out; 3278598066cSFelipe Balbi } 3288598066cSFelipe Balbi 3298598066cSFelipe Balbi out: 3308598066cSFelipe Balbi if (!irqnr) 3318598066cSFelipe Balbi break; 3328598066cSFelipe Balbi 3338598066cSFelipe Balbi irqnr = intc_readl(INTC_SIR); 3348598066cSFelipe Balbi irqnr &= ACTIVEIRQ_MASK; 3358598066cSFelipe Balbi 3368598066cSFelipe Balbi if (irqnr) { 337782d59c5SLinus Torvalds handle_domain_irq(domain, irqnr, regs); 3388598066cSFelipe Balbi handled_irq = 1; 3398598066cSFelipe Balbi } 3408598066cSFelipe Balbi } while (irqnr); 3418598066cSFelipe Balbi 342503b8d12SFelipe Balbi /* 343503b8d12SFelipe Balbi * If an irq is masked or deasserted while active, we will 3448598066cSFelipe Balbi * keep ending up here with no irq handled. So remove it from 345503b8d12SFelipe Balbi * the INTC with an ack. 346503b8d12SFelipe Balbi */ 3478598066cSFelipe Balbi if (!handled_irq) 3488598066cSFelipe Balbi omap_ack_irq(NULL); 3498598066cSFelipe Balbi } 3508598066cSFelipe Balbi 3518598066cSFelipe Balbi void __init omap2_init_irq(void) 3528598066cSFelipe Balbi { 3538598066cSFelipe Balbi omap_nr_irqs = 96; 3548598066cSFelipe Balbi omap_nr_pending = 3; 3558598066cSFelipe Balbi omap_init_irq(OMAP24XX_IC_BASE, NULL); 3568598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3578598066cSFelipe Balbi } 3588598066cSFelipe Balbi 3598598066cSFelipe Balbi void __init omap3_init_irq(void) 3608598066cSFelipe Balbi { 3618598066cSFelipe Balbi omap_nr_irqs = 96; 3628598066cSFelipe Balbi omap_nr_pending = 3; 3638598066cSFelipe Balbi omap_init_irq(OMAP34XX_IC_BASE, NULL); 3648598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3658598066cSFelipe Balbi } 3668598066cSFelipe Balbi 3678598066cSFelipe Balbi void __init ti81xx_init_irq(void) 3688598066cSFelipe Balbi { 3698598066cSFelipe Balbi omap_nr_irqs = 96; 3708598066cSFelipe Balbi omap_nr_pending = 4; 3718598066cSFelipe Balbi omap_init_irq(OMAP34XX_IC_BASE, NULL); 3728598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3738598066cSFelipe Balbi } 3748598066cSFelipe Balbi 3758598066cSFelipe Balbi static int __init intc_of_init(struct device_node *node, 3768598066cSFelipe Balbi struct device_node *parent) 3778598066cSFelipe Balbi { 3788598066cSFelipe Balbi int ret; 3798598066cSFelipe Balbi 3808598066cSFelipe Balbi omap_nr_pending = 3; 3818598066cSFelipe Balbi omap_nr_irqs = 96; 3828598066cSFelipe Balbi 3838598066cSFelipe Balbi if (WARN_ON(!node)) 3848598066cSFelipe Balbi return -ENODEV; 3858598066cSFelipe Balbi 3868598066cSFelipe Balbi if (of_device_is_compatible(node, "ti,am33xx-intc")) { 3878598066cSFelipe Balbi omap_nr_irqs = 128; 3888598066cSFelipe Balbi omap_nr_pending = 4; 3898598066cSFelipe Balbi } 3908598066cSFelipe Balbi 3918598066cSFelipe Balbi ret = omap_init_irq(-1, of_node_get(node)); 3928598066cSFelipe Balbi if (ret < 0) 3938598066cSFelipe Balbi return ret; 3948598066cSFelipe Balbi 3958598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3968598066cSFelipe Balbi 3978598066cSFelipe Balbi return 0; 3988598066cSFelipe Balbi } 3998598066cSFelipe Balbi 4008598066cSFelipe Balbi IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init); 4018598066cSFelipe Balbi IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init); 4028598066cSFelipe Balbi IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init); 403