18598066cSFelipe Balbi /* 28598066cSFelipe Balbi * linux/arch/arm/mach-omap2/irq.c 38598066cSFelipe Balbi * 48598066cSFelipe Balbi * Interrupt handler for OMAP2 boards. 58598066cSFelipe Balbi * 68598066cSFelipe Balbi * Copyright (C) 2005 Nokia Corporation 78598066cSFelipe Balbi * Author: Paul Mundt <paul.mundt@nokia.com> 88598066cSFelipe Balbi * 98598066cSFelipe Balbi * This file is subject to the terms and conditions of the GNU General Public 108598066cSFelipe Balbi * License. See the file "COPYING" in the main directory of this archive 118598066cSFelipe Balbi * for more details. 128598066cSFelipe Balbi */ 138598066cSFelipe Balbi #include <linux/kernel.h> 148598066cSFelipe Balbi #include <linux/module.h> 158598066cSFelipe Balbi #include <linux/init.h> 168598066cSFelipe Balbi #include <linux/interrupt.h> 178598066cSFelipe Balbi #include <linux/io.h> 188598066cSFelipe Balbi 198598066cSFelipe Balbi #include <asm/exception.h> 2041a83e06SJoel Porquet #include <linux/irqchip.h> 218598066cSFelipe Balbi #include <linux/irqdomain.h> 228598066cSFelipe Balbi #include <linux/of.h> 238598066cSFelipe Balbi #include <linux/of_address.h> 248598066cSFelipe Balbi #include <linux/of_irq.h> 258598066cSFelipe Balbi 26f3142635SBen Dooks #include <linux/irqchip/irq-omap-intc.h> 27f3142635SBen Dooks 288598066cSFelipe Balbi /* selected INTC register offsets */ 298598066cSFelipe Balbi 308598066cSFelipe Balbi #define INTC_REVISION 0x0000 318598066cSFelipe Balbi #define INTC_SYSCONFIG 0x0010 328598066cSFelipe Balbi #define INTC_SYSSTATUS 0x0014 338598066cSFelipe Balbi #define INTC_SIR 0x0040 348598066cSFelipe Balbi #define INTC_CONTROL 0x0048 358598066cSFelipe Balbi #define INTC_PROTECTION 0x004C 368598066cSFelipe Balbi #define INTC_IDLE 0x0050 378598066cSFelipe Balbi #define INTC_THRESHOLD 0x0068 388598066cSFelipe Balbi #define INTC_MIR0 0x0084 398598066cSFelipe Balbi #define INTC_MIR_CLEAR0 0x0088 408598066cSFelipe Balbi #define INTC_MIR_SET0 0x008c 418598066cSFelipe Balbi #define INTC_PENDING_IRQ0 0x0098 428598066cSFelipe Balbi #define INTC_PENDING_IRQ1 0x00b8 438598066cSFelipe Balbi #define INTC_PENDING_IRQ2 0x00d8 448598066cSFelipe Balbi #define INTC_PENDING_IRQ3 0x00f8 458598066cSFelipe Balbi #define INTC_ILR0 0x0100 468598066cSFelipe Balbi 478598066cSFelipe Balbi #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ 48d3b421cdSSekhar Nori #define SPURIOUSIRQ_MASK (0x1ffffff << 7) 498598066cSFelipe Balbi #define INTCPS_NR_ILR_REGS 128 5074b6c8efSFelipe Balbi #define INTCPS_NR_MIR_REGS 4 518598066cSFelipe Balbi 52b3079149SFelipe Balbi #define INTC_IDLE_FUNCIDLE (1 << 0) 53b3079149SFelipe Balbi #define INTC_IDLE_TURBO (1 << 1) 54b3079149SFelipe Balbi 559836ee9fSFelipe Balbi #define INTC_PROTECTION_ENABLE (1 << 0) 569836ee9fSFelipe Balbi 578598066cSFelipe Balbi struct omap_intc_regs { 588598066cSFelipe Balbi u32 sysconfig; 598598066cSFelipe Balbi u32 protection; 608598066cSFelipe Balbi u32 idle; 618598066cSFelipe Balbi u32 threshold; 628598066cSFelipe Balbi u32 ilr[INTCPS_NR_ILR_REGS]; 638598066cSFelipe Balbi u32 mir[INTCPS_NR_MIR_REGS]; 648598066cSFelipe Balbi }; 658598066cSFelipe Balbi static struct omap_intc_regs intc_context; 668598066cSFelipe Balbi 678598066cSFelipe Balbi static struct irq_domain *domain; 688598066cSFelipe Balbi static void __iomem *omap_irq_base; 6977c858faSLadislav Michl static int omap_nr_pending; 7077c858faSLadislav Michl static int omap_nr_irqs; 718598066cSFelipe Balbi 728598066cSFelipe Balbi static void intc_writel(u32 reg, u32 val) 738598066cSFelipe Balbi { 748598066cSFelipe Balbi writel_relaxed(val, omap_irq_base + reg); 758598066cSFelipe Balbi } 768598066cSFelipe Balbi 778598066cSFelipe Balbi static u32 intc_readl(u32 reg) 788598066cSFelipe Balbi { 798598066cSFelipe Balbi return readl_relaxed(omap_irq_base + reg); 808598066cSFelipe Balbi } 818598066cSFelipe Balbi 828598066cSFelipe Balbi void omap_intc_save_context(void) 838598066cSFelipe Balbi { 848598066cSFelipe Balbi int i; 858598066cSFelipe Balbi 868598066cSFelipe Balbi intc_context.sysconfig = 878598066cSFelipe Balbi intc_readl(INTC_SYSCONFIG); 888598066cSFelipe Balbi intc_context.protection = 898598066cSFelipe Balbi intc_readl(INTC_PROTECTION); 908598066cSFelipe Balbi intc_context.idle = 918598066cSFelipe Balbi intc_readl(INTC_IDLE); 928598066cSFelipe Balbi intc_context.threshold = 938598066cSFelipe Balbi intc_readl(INTC_THRESHOLD); 948598066cSFelipe Balbi 958598066cSFelipe Balbi for (i = 0; i < omap_nr_irqs; i++) 968598066cSFelipe Balbi intc_context.ilr[i] = 978598066cSFelipe Balbi intc_readl((INTC_ILR0 + 0x4 * i)); 988598066cSFelipe Balbi for (i = 0; i < INTCPS_NR_MIR_REGS; i++) 998598066cSFelipe Balbi intc_context.mir[i] = 1008598066cSFelipe Balbi intc_readl(INTC_MIR0 + (0x20 * i)); 1018598066cSFelipe Balbi } 1028598066cSFelipe Balbi 1038598066cSFelipe Balbi void omap_intc_restore_context(void) 1048598066cSFelipe Balbi { 1058598066cSFelipe Balbi int i; 1068598066cSFelipe Balbi 1078598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); 1088598066cSFelipe Balbi intc_writel(INTC_PROTECTION, intc_context.protection); 1098598066cSFelipe Balbi intc_writel(INTC_IDLE, intc_context.idle); 1108598066cSFelipe Balbi intc_writel(INTC_THRESHOLD, intc_context.threshold); 1118598066cSFelipe Balbi 1128598066cSFelipe Balbi for (i = 0; i < omap_nr_irqs; i++) 1138598066cSFelipe Balbi intc_writel(INTC_ILR0 + 0x4 * i, 1148598066cSFelipe Balbi intc_context.ilr[i]); 1158598066cSFelipe Balbi 1168598066cSFelipe Balbi for (i = 0; i < INTCPS_NR_MIR_REGS; i++) 1178598066cSFelipe Balbi intc_writel(INTC_MIR0 + 0x20 * i, 1188598066cSFelipe Balbi intc_context.mir[i]); 1198598066cSFelipe Balbi /* MIRs are saved and restore with other PRCM registers */ 1208598066cSFelipe Balbi } 1218598066cSFelipe Balbi 1228598066cSFelipe Balbi void omap3_intc_prepare_idle(void) 1238598066cSFelipe Balbi { 1248598066cSFelipe Balbi /* 1258598066cSFelipe Balbi * Disable autoidle as it can stall interrupt controller, 1268598066cSFelipe Balbi * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) 1278598066cSFelipe Balbi */ 1288598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 0); 129b3079149SFelipe Balbi intc_writel(INTC_IDLE, INTC_IDLE_TURBO); 1308598066cSFelipe Balbi } 1318598066cSFelipe Balbi 1328598066cSFelipe Balbi void omap3_intc_resume_idle(void) 1338598066cSFelipe Balbi { 1348598066cSFelipe Balbi /* Re-enable autoidle */ 1358598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 1); 136b3079149SFelipe Balbi intc_writel(INTC_IDLE, 0); 1378598066cSFelipe Balbi } 1388598066cSFelipe Balbi 1398598066cSFelipe Balbi /* XXX: FIQ and additional INTC support (only MPU at the moment) */ 1408598066cSFelipe Balbi static void omap_ack_irq(struct irq_data *d) 1418598066cSFelipe Balbi { 1428598066cSFelipe Balbi intc_writel(INTC_CONTROL, 0x1); 1438598066cSFelipe Balbi } 1448598066cSFelipe Balbi 1458598066cSFelipe Balbi static void omap_mask_ack_irq(struct irq_data *d) 1468598066cSFelipe Balbi { 1478598066cSFelipe Balbi irq_gc_mask_disable_reg(d); 1488598066cSFelipe Balbi omap_ack_irq(d); 1498598066cSFelipe Balbi } 1508598066cSFelipe Balbi 1518598066cSFelipe Balbi static void __init omap_irq_soft_reset(void) 1528598066cSFelipe Balbi { 1538598066cSFelipe Balbi unsigned long tmp; 1548598066cSFelipe Balbi 1558598066cSFelipe Balbi tmp = intc_readl(INTC_REVISION) & 0xff; 1568598066cSFelipe Balbi 1578598066cSFelipe Balbi pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", 1588598066cSFelipe Balbi omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs); 1598598066cSFelipe Balbi 1608598066cSFelipe Balbi tmp = intc_readl(INTC_SYSCONFIG); 1618598066cSFelipe Balbi tmp |= 1 << 1; /* soft reset */ 1628598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, tmp); 1638598066cSFelipe Balbi 1648598066cSFelipe Balbi while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) 1658598066cSFelipe Balbi /* Wait for reset to complete */; 1668598066cSFelipe Balbi 1678598066cSFelipe Balbi /* Enable autoidle */ 1688598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 1 << 0); 1698598066cSFelipe Balbi } 1708598066cSFelipe Balbi 1718598066cSFelipe Balbi int omap_irq_pending(void) 1728598066cSFelipe Balbi { 1736bd0f16eSFelipe Balbi int i; 1748598066cSFelipe Balbi 1756bd0f16eSFelipe Balbi for (i = 0; i < omap_nr_pending; i++) 1766bd0f16eSFelipe Balbi if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i))) 1778598066cSFelipe Balbi return 1; 1788598066cSFelipe Balbi return 0; 1798598066cSFelipe Balbi } 1808598066cSFelipe Balbi 1818598066cSFelipe Balbi void omap3_intc_suspend(void) 1828598066cSFelipe Balbi { 1838598066cSFelipe Balbi /* A pending interrupt would prevent OMAP from entering suspend */ 1848598066cSFelipe Balbi omap_ack_irq(NULL); 1858598066cSFelipe Balbi } 1868598066cSFelipe Balbi 1878598066cSFelipe Balbi static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base) 1888598066cSFelipe Balbi { 1898598066cSFelipe Balbi int ret; 1908598066cSFelipe Balbi int i; 1918598066cSFelipe Balbi 1928598066cSFelipe Balbi ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC", 1938598066cSFelipe Balbi handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE, 1948598066cSFelipe Balbi IRQ_LEVEL, 0); 1958598066cSFelipe Balbi if (ret) { 1968598066cSFelipe Balbi pr_warn("Failed to allocate irq chips\n"); 1978598066cSFelipe Balbi return ret; 1988598066cSFelipe Balbi } 1998598066cSFelipe Balbi 2008598066cSFelipe Balbi for (i = 0; i < omap_nr_pending; i++) { 2018598066cSFelipe Balbi struct irq_chip_generic *gc; 2028598066cSFelipe Balbi struct irq_chip_type *ct; 2038598066cSFelipe Balbi 2048598066cSFelipe Balbi gc = irq_get_domain_generic_chip(d, 32 * i); 2058598066cSFelipe Balbi gc->reg_base = base; 2068598066cSFelipe Balbi ct = gc->chip_types; 2078598066cSFelipe Balbi 2088598066cSFelipe Balbi ct->type = IRQ_TYPE_LEVEL_MASK; 2098598066cSFelipe Balbi 2108598066cSFelipe Balbi ct->chip.irq_ack = omap_mask_ack_irq; 2118598066cSFelipe Balbi ct->chip.irq_mask = irq_gc_mask_disable_reg; 2128598066cSFelipe Balbi ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 2138598066cSFelipe Balbi 2148598066cSFelipe Balbi ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; 2158598066cSFelipe Balbi 2168598066cSFelipe Balbi ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i; 2178598066cSFelipe Balbi ct->regs.disable = INTC_MIR_SET0 + 32 * i; 2188598066cSFelipe Balbi } 2198598066cSFelipe Balbi 2208598066cSFelipe Balbi return 0; 2218598066cSFelipe Balbi } 2228598066cSFelipe Balbi 2238598066cSFelipe Balbi static void __init omap_alloc_gc_legacy(void __iomem *base, 2248598066cSFelipe Balbi unsigned int irq_start, unsigned int num) 2258598066cSFelipe Balbi { 2268598066cSFelipe Balbi struct irq_chip_generic *gc; 2278598066cSFelipe Balbi struct irq_chip_type *ct; 2288598066cSFelipe Balbi 2298598066cSFelipe Balbi gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, 2308598066cSFelipe Balbi handle_level_irq); 2318598066cSFelipe Balbi ct = gc->chip_types; 2328598066cSFelipe Balbi ct->chip.irq_ack = omap_mask_ack_irq; 2338598066cSFelipe Balbi ct->chip.irq_mask = irq_gc_mask_disable_reg; 2348598066cSFelipe Balbi ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 2358598066cSFelipe Balbi ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; 2368598066cSFelipe Balbi 2378598066cSFelipe Balbi ct->regs.enable = INTC_MIR_CLEAR0; 2388598066cSFelipe Balbi ct->regs.disable = INTC_MIR_SET0; 2398598066cSFelipe Balbi irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 2408598066cSFelipe Balbi IRQ_NOREQUEST | IRQ_NOPROBE, 0); 2418598066cSFelipe Balbi } 2428598066cSFelipe Balbi 2438598066cSFelipe Balbi static int __init omap_init_irq_of(struct device_node *node) 2448598066cSFelipe Balbi { 2458598066cSFelipe Balbi int ret; 2468598066cSFelipe Balbi 2478598066cSFelipe Balbi omap_irq_base = of_iomap(node, 0); 2488598066cSFelipe Balbi if (WARN_ON(!omap_irq_base)) 2498598066cSFelipe Balbi return -ENOMEM; 2508598066cSFelipe Balbi 2518598066cSFelipe Balbi domain = irq_domain_add_linear(node, omap_nr_irqs, 2528598066cSFelipe Balbi &irq_generic_chip_ops, NULL); 2538598066cSFelipe Balbi 2548598066cSFelipe Balbi omap_irq_soft_reset(); 2558598066cSFelipe Balbi 2568598066cSFelipe Balbi ret = omap_alloc_gc_of(domain, omap_irq_base); 2578598066cSFelipe Balbi if (ret < 0) 2588598066cSFelipe Balbi irq_domain_remove(domain); 2598598066cSFelipe Balbi 2608598066cSFelipe Balbi return ret; 2618598066cSFelipe Balbi } 2628598066cSFelipe Balbi 2634b149e41SFelipe Balbi static int __init omap_init_irq_legacy(u32 base, struct device_node *node) 2648598066cSFelipe Balbi { 2658598066cSFelipe Balbi int j, irq_base; 2668598066cSFelipe Balbi 2678598066cSFelipe Balbi omap_irq_base = ioremap(base, SZ_4K); 2688598066cSFelipe Balbi if (WARN_ON(!omap_irq_base)) 2698598066cSFelipe Balbi return -ENOMEM; 2708598066cSFelipe Balbi 2718598066cSFelipe Balbi irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0); 2728598066cSFelipe Balbi if (irq_base < 0) { 2738598066cSFelipe Balbi pr_warn("Couldn't allocate IRQ numbers\n"); 2748598066cSFelipe Balbi irq_base = 0; 2758598066cSFelipe Balbi } 2768598066cSFelipe Balbi 2774b149e41SFelipe Balbi domain = irq_domain_add_legacy(node, omap_nr_irqs, irq_base, 0, 2788598066cSFelipe Balbi &irq_domain_simple_ops, NULL); 2798598066cSFelipe Balbi 2808598066cSFelipe Balbi omap_irq_soft_reset(); 2818598066cSFelipe Balbi 2828598066cSFelipe Balbi for (j = 0; j < omap_nr_irqs; j += 32) 2838598066cSFelipe Balbi omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32); 2848598066cSFelipe Balbi 2858598066cSFelipe Balbi return 0; 2868598066cSFelipe Balbi } 2878598066cSFelipe Balbi 2889836ee9fSFelipe Balbi static void __init omap_irq_enable_protection(void) 2899836ee9fSFelipe Balbi { 2909836ee9fSFelipe Balbi u32 reg; 2919836ee9fSFelipe Balbi 2929836ee9fSFelipe Balbi reg = intc_readl(INTC_PROTECTION); 2939836ee9fSFelipe Balbi reg |= INTC_PROTECTION_ENABLE; 2949836ee9fSFelipe Balbi intc_writel(INTC_PROTECTION, reg); 2959836ee9fSFelipe Balbi } 2969836ee9fSFelipe Balbi 2978598066cSFelipe Balbi static int __init omap_init_irq(u32 base, struct device_node *node) 2988598066cSFelipe Balbi { 2999836ee9fSFelipe Balbi int ret; 3009836ee9fSFelipe Balbi 3014b149e41SFelipe Balbi /* 3024b149e41SFelipe Balbi * FIXME legacy OMAP DMA driver sitting under arch/arm/plat-omap/dma.c 3034b149e41SFelipe Balbi * depends is still not ready for linear IRQ domains; because of that 3044b149e41SFelipe Balbi * we need to temporarily "blacklist" OMAP2 and OMAP3 devices from using 3054b149e41SFelipe Balbi * linear IRQ Domain until that driver is finally fixed. 3064b149e41SFelipe Balbi */ 3074b149e41SFelipe Balbi if (of_device_is_compatible(node, "ti,omap2-intc") || 3084b149e41SFelipe Balbi of_device_is_compatible(node, "ti,omap3-intc")) { 3094b149e41SFelipe Balbi struct resource res; 3104b149e41SFelipe Balbi 3114b149e41SFelipe Balbi if (of_address_to_resource(node, 0, &res)) 3124b149e41SFelipe Balbi return -ENOMEM; 3134b149e41SFelipe Balbi 3144b149e41SFelipe Balbi base = res.start; 3154b149e41SFelipe Balbi ret = omap_init_irq_legacy(base, node); 3164b149e41SFelipe Balbi } else if (node) { 3179836ee9fSFelipe Balbi ret = omap_init_irq_of(node); 3184b149e41SFelipe Balbi } else { 3194b149e41SFelipe Balbi ret = omap_init_irq_legacy(base, NULL); 3204b149e41SFelipe Balbi } 3219836ee9fSFelipe Balbi 3229836ee9fSFelipe Balbi if (ret == 0) 3239836ee9fSFelipe Balbi omap_irq_enable_protection(); 3249836ee9fSFelipe Balbi 3259836ee9fSFelipe Balbi return ret; 3268598066cSFelipe Balbi } 3278598066cSFelipe Balbi 3288598066cSFelipe Balbi static asmlinkage void __exception_irq_entry 3298598066cSFelipe Balbi omap_intc_handle_irq(struct pt_regs *regs) 3308598066cSFelipe Balbi { 331d3b421cdSSekhar Nori extern unsigned long irq_err_count; 3326ed34648SFelipe Balbi u32 irqnr; 3338598066cSFelipe Balbi 3348598066cSFelipe Balbi irqnr = intc_readl(INTC_SIR); 335d3b421cdSSekhar Nori 336d3b421cdSSekhar Nori /* 337d3b421cdSSekhar Nori * A spurious IRQ can result if interrupt that triggered the 338d3b421cdSSekhar Nori * sorting is no longer active during the sorting (10 INTC 339d3b421cdSSekhar Nori * functional clock cycles after interrupt assertion). Or a 340d3b421cdSSekhar Nori * change in interrupt mask affected the result during sorting 341d3b421cdSSekhar Nori * time. There is no special handling required except ignoring 342d3b421cdSSekhar Nori * the SIR register value just read and retrying. 343d3b421cdSSekhar Nori * See section 6.2.5 of AM335x TRM Literature Number: SPRUH73K 344d3b421cdSSekhar Nori * 345d3b421cdSSekhar Nori * Many a times, a spurious interrupt situation has been fixed 346d3b421cdSSekhar Nori * by adding a flush for the posted write acking the IRQ in 347d3b421cdSSekhar Nori * the device driver. Typically, this is going be the device 348d3b421cdSSekhar Nori * driver whose interrupt was handled just before the spurious 349d3b421cdSSekhar Nori * IRQ occurred. Pay attention to those device drivers if you 350d3b421cdSSekhar Nori * run into hitting the spurious IRQ condition below. 351d3b421cdSSekhar Nori */ 352d3b421cdSSekhar Nori if (unlikely((irqnr & SPURIOUSIRQ_MASK) == SPURIOUSIRQ_MASK)) { 353d3b421cdSSekhar Nori pr_err_once("%s: spurious irq!\n", __func__); 354d3b421cdSSekhar Nori irq_err_count++; 355d3b421cdSSekhar Nori omap_ack_irq(NULL); 356d3b421cdSSekhar Nori return; 357d3b421cdSSekhar Nori } 358d3b421cdSSekhar Nori 3598598066cSFelipe Balbi irqnr &= ACTIVEIRQ_MASK; 360782d59c5SLinus Torvalds handle_domain_irq(domain, irqnr, regs); 3618598066cSFelipe Balbi } 3628598066cSFelipe Balbi 3638598066cSFelipe Balbi static int __init intc_of_init(struct device_node *node, 3648598066cSFelipe Balbi struct device_node *parent) 3658598066cSFelipe Balbi { 3668598066cSFelipe Balbi int ret; 3678598066cSFelipe Balbi 3688598066cSFelipe Balbi omap_nr_pending = 3; 3698598066cSFelipe Balbi omap_nr_irqs = 96; 3708598066cSFelipe Balbi 3718598066cSFelipe Balbi if (WARN_ON(!node)) 3728598066cSFelipe Balbi return -ENODEV; 3738598066cSFelipe Balbi 37419f92b23STony Lindgren if (of_device_is_compatible(node, "ti,dm814-intc") || 37519f92b23STony Lindgren of_device_is_compatible(node, "ti,dm816-intc") || 37619f92b23STony Lindgren of_device_is_compatible(node, "ti,am33xx-intc")) { 3778598066cSFelipe Balbi omap_nr_irqs = 128; 3788598066cSFelipe Balbi omap_nr_pending = 4; 3798598066cSFelipe Balbi } 3808598066cSFelipe Balbi 3818598066cSFelipe Balbi ret = omap_init_irq(-1, of_node_get(node)); 3828598066cSFelipe Balbi if (ret < 0) 3838598066cSFelipe Balbi return ret; 3848598066cSFelipe Balbi 3858598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3868598066cSFelipe Balbi 3878598066cSFelipe Balbi return 0; 3888598066cSFelipe Balbi } 3898598066cSFelipe Balbi 3908598066cSFelipe Balbi IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init); 3918598066cSFelipe Balbi IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init); 39219f92b23STony Lindgren IRQCHIP_DECLARE(dm814x_intc, "ti,dm814-intc", intc_of_init); 39319f92b23STony Lindgren IRQCHIP_DECLARE(dm816x_intc, "ti,dm816-intc", intc_of_init); 3948598066cSFelipe Balbi IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init); 395