18598066cSFelipe Balbi /* 28598066cSFelipe Balbi * linux/arch/arm/mach-omap2/irq.c 38598066cSFelipe Balbi * 48598066cSFelipe Balbi * Interrupt handler for OMAP2 boards. 58598066cSFelipe Balbi * 68598066cSFelipe Balbi * Copyright (C) 2005 Nokia Corporation 78598066cSFelipe Balbi * Author: Paul Mundt <paul.mundt@nokia.com> 88598066cSFelipe Balbi * 98598066cSFelipe Balbi * This file is subject to the terms and conditions of the GNU General Public 108598066cSFelipe Balbi * License. See the file "COPYING" in the main directory of this archive 118598066cSFelipe Balbi * for more details. 128598066cSFelipe Balbi */ 138598066cSFelipe Balbi #include <linux/kernel.h> 148598066cSFelipe Balbi #include <linux/module.h> 158598066cSFelipe Balbi #include <linux/init.h> 168598066cSFelipe Balbi #include <linux/interrupt.h> 178598066cSFelipe Balbi #include <linux/io.h> 188598066cSFelipe Balbi 198598066cSFelipe Balbi #include <asm/exception.h> 208598066cSFelipe Balbi #include <linux/irqdomain.h> 218598066cSFelipe Balbi #include <linux/of.h> 228598066cSFelipe Balbi #include <linux/of_address.h> 238598066cSFelipe Balbi #include <linux/of_irq.h> 248598066cSFelipe Balbi 258598066cSFelipe Balbi #include "irqchip.h" 268598066cSFelipe Balbi 278598066cSFelipe Balbi /* Define these here for now until we drop all board-files */ 288598066cSFelipe Balbi #define OMAP24XX_IC_BASE 0x480fe000 298598066cSFelipe Balbi #define OMAP34XX_IC_BASE 0x48200000 308598066cSFelipe Balbi 318598066cSFelipe Balbi /* selected INTC register offsets */ 328598066cSFelipe Balbi 338598066cSFelipe Balbi #define INTC_REVISION 0x0000 348598066cSFelipe Balbi #define INTC_SYSCONFIG 0x0010 358598066cSFelipe Balbi #define INTC_SYSSTATUS 0x0014 368598066cSFelipe Balbi #define INTC_SIR 0x0040 378598066cSFelipe Balbi #define INTC_CONTROL 0x0048 388598066cSFelipe Balbi #define INTC_PROTECTION 0x004C 398598066cSFelipe Balbi #define INTC_IDLE 0x0050 408598066cSFelipe Balbi #define INTC_THRESHOLD 0x0068 418598066cSFelipe Balbi #define INTC_MIR0 0x0084 428598066cSFelipe Balbi #define INTC_MIR_CLEAR0 0x0088 438598066cSFelipe Balbi #define INTC_MIR_SET0 0x008c 448598066cSFelipe Balbi #define INTC_PENDING_IRQ0 0x0098 458598066cSFelipe Balbi #define INTC_PENDING_IRQ1 0x00b8 468598066cSFelipe Balbi #define INTC_PENDING_IRQ2 0x00d8 478598066cSFelipe Balbi #define INTC_PENDING_IRQ3 0x00f8 488598066cSFelipe Balbi #define INTC_ILR0 0x0100 498598066cSFelipe Balbi 508598066cSFelipe Balbi #define ACTIVEIRQ_MASK 0x7f /* omap2/3 active interrupt bits */ 518598066cSFelipe Balbi #define INTCPS_NR_ILR_REGS 128 528598066cSFelipe Balbi #define INTCPS_NR_MIR_REGS 3 538598066cSFelipe Balbi 548598066cSFelipe Balbi /* 558598066cSFelipe Balbi * OMAP2 has a number of different interrupt controllers, each interrupt 568598066cSFelipe Balbi * controller is identified as its own "bank". Register definitions are 578598066cSFelipe Balbi * fairly consistent for each bank, but not all registers are implemented 588598066cSFelipe Balbi * for each bank.. when in doubt, consult the TRM. 598598066cSFelipe Balbi */ 608598066cSFelipe Balbi 618598066cSFelipe Balbi /* Structure to save interrupt controller context */ 628598066cSFelipe Balbi struct omap_intc_regs { 638598066cSFelipe Balbi u32 sysconfig; 648598066cSFelipe Balbi u32 protection; 658598066cSFelipe Balbi u32 idle; 668598066cSFelipe Balbi u32 threshold; 678598066cSFelipe Balbi u32 ilr[INTCPS_NR_ILR_REGS]; 688598066cSFelipe Balbi u32 mir[INTCPS_NR_MIR_REGS]; 698598066cSFelipe Balbi }; 708598066cSFelipe Balbi static struct omap_intc_regs intc_context; 718598066cSFelipe Balbi 728598066cSFelipe Balbi static struct irq_domain *domain; 738598066cSFelipe Balbi static void __iomem *omap_irq_base; 748598066cSFelipe Balbi static int omap_nr_pending = 3; 758598066cSFelipe Balbi static int omap_nr_irqs = 96; 768598066cSFelipe Balbi 778598066cSFelipe Balbi /* INTC bank register get/set */ 788598066cSFelipe Balbi static void intc_writel(u32 reg, u32 val) 798598066cSFelipe Balbi { 808598066cSFelipe Balbi writel_relaxed(val, omap_irq_base + reg); 818598066cSFelipe Balbi } 828598066cSFelipe Balbi 838598066cSFelipe Balbi static u32 intc_readl(u32 reg) 848598066cSFelipe Balbi { 858598066cSFelipe Balbi return readl_relaxed(omap_irq_base + reg); 868598066cSFelipe Balbi } 878598066cSFelipe Balbi 888598066cSFelipe Balbi void omap_intc_save_context(void) 898598066cSFelipe Balbi { 908598066cSFelipe Balbi int i; 918598066cSFelipe Balbi 928598066cSFelipe Balbi intc_context.sysconfig = 938598066cSFelipe Balbi intc_readl(INTC_SYSCONFIG); 948598066cSFelipe Balbi intc_context.protection = 958598066cSFelipe Balbi intc_readl(INTC_PROTECTION); 968598066cSFelipe Balbi intc_context.idle = 978598066cSFelipe Balbi intc_readl(INTC_IDLE); 988598066cSFelipe Balbi intc_context.threshold = 998598066cSFelipe Balbi intc_readl(INTC_THRESHOLD); 1008598066cSFelipe Balbi 1018598066cSFelipe Balbi for (i = 0; i < omap_nr_irqs; i++) 1028598066cSFelipe Balbi intc_context.ilr[i] = 1038598066cSFelipe Balbi intc_readl((INTC_ILR0 + 0x4 * i)); 1048598066cSFelipe Balbi for (i = 0; i < INTCPS_NR_MIR_REGS; i++) 1058598066cSFelipe Balbi intc_context.mir[i] = 1068598066cSFelipe Balbi intc_readl(INTC_MIR0 + (0x20 * i)); 1078598066cSFelipe Balbi } 1088598066cSFelipe Balbi 1098598066cSFelipe Balbi void omap_intc_restore_context(void) 1108598066cSFelipe Balbi { 1118598066cSFelipe Balbi int i; 1128598066cSFelipe Balbi 1138598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, intc_context.sysconfig); 1148598066cSFelipe Balbi intc_writel(INTC_PROTECTION, intc_context.protection); 1158598066cSFelipe Balbi intc_writel(INTC_IDLE, intc_context.idle); 1168598066cSFelipe Balbi intc_writel(INTC_THRESHOLD, intc_context.threshold); 1178598066cSFelipe Balbi 1188598066cSFelipe Balbi for (i = 0; i < omap_nr_irqs; i++) 1198598066cSFelipe Balbi intc_writel(INTC_ILR0 + 0x4 * i, 1208598066cSFelipe Balbi intc_context.ilr[i]); 1218598066cSFelipe Balbi 1228598066cSFelipe Balbi for (i = 0; i < INTCPS_NR_MIR_REGS; i++) 1238598066cSFelipe Balbi intc_writel(INTC_MIR0 + 0x20 * i, 1248598066cSFelipe Balbi intc_context.mir[i]); 1258598066cSFelipe Balbi /* MIRs are saved and restore with other PRCM registers */ 1268598066cSFelipe Balbi } 1278598066cSFelipe Balbi 1288598066cSFelipe Balbi void omap3_intc_prepare_idle(void) 1298598066cSFelipe Balbi { 1308598066cSFelipe Balbi /* 1318598066cSFelipe Balbi * Disable autoidle as it can stall interrupt controller, 1328598066cSFelipe Balbi * cf. errata ID i540 for 3430 (all revisions up to 3.1.x) 1338598066cSFelipe Balbi */ 1348598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 0); 1358598066cSFelipe Balbi } 1368598066cSFelipe Balbi 1378598066cSFelipe Balbi void omap3_intc_resume_idle(void) 1388598066cSFelipe Balbi { 1398598066cSFelipe Balbi /* Re-enable autoidle */ 1408598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 1); 1418598066cSFelipe Balbi } 1428598066cSFelipe Balbi 1438598066cSFelipe Balbi /* XXX: FIQ and additional INTC support (only MPU at the moment) */ 1448598066cSFelipe Balbi static void omap_ack_irq(struct irq_data *d) 1458598066cSFelipe Balbi { 1468598066cSFelipe Balbi intc_writel(INTC_CONTROL, 0x1); 1478598066cSFelipe Balbi } 1488598066cSFelipe Balbi 1498598066cSFelipe Balbi static void omap_mask_ack_irq(struct irq_data *d) 1508598066cSFelipe Balbi { 1518598066cSFelipe Balbi irq_gc_mask_disable_reg(d); 1528598066cSFelipe Balbi omap_ack_irq(d); 1538598066cSFelipe Balbi } 1548598066cSFelipe Balbi 1558598066cSFelipe Balbi static void __init omap_irq_soft_reset(void) 1568598066cSFelipe Balbi { 1578598066cSFelipe Balbi unsigned long tmp; 1588598066cSFelipe Balbi 1598598066cSFelipe Balbi tmp = intc_readl(INTC_REVISION) & 0xff; 1608598066cSFelipe Balbi 1618598066cSFelipe Balbi pr_info("IRQ: Found an INTC at 0x%p (revision %ld.%ld) with %d interrupts\n", 1628598066cSFelipe Balbi omap_irq_base, tmp >> 4, tmp & 0xf, omap_nr_irqs); 1638598066cSFelipe Balbi 1648598066cSFelipe Balbi tmp = intc_readl(INTC_SYSCONFIG); 1658598066cSFelipe Balbi tmp |= 1 << 1; /* soft reset */ 1668598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, tmp); 1678598066cSFelipe Balbi 1688598066cSFelipe Balbi while (!(intc_readl(INTC_SYSSTATUS) & 0x1)) 1698598066cSFelipe Balbi /* Wait for reset to complete */; 1708598066cSFelipe Balbi 1718598066cSFelipe Balbi /* Enable autoidle */ 1728598066cSFelipe Balbi intc_writel(INTC_SYSCONFIG, 1 << 0); 1738598066cSFelipe Balbi } 1748598066cSFelipe Balbi 1758598066cSFelipe Balbi int omap_irq_pending(void) 1768598066cSFelipe Balbi { 1776bd0f16eSFelipe Balbi int i; 1788598066cSFelipe Balbi 1796bd0f16eSFelipe Balbi for (i = 0; i < omap_nr_pending; i++) 1806bd0f16eSFelipe Balbi if (intc_readl(INTC_PENDING_IRQ0 + (0x20 * i))) 1818598066cSFelipe Balbi return 1; 1828598066cSFelipe Balbi return 0; 1838598066cSFelipe Balbi } 1848598066cSFelipe Balbi 1858598066cSFelipe Balbi void omap3_intc_suspend(void) 1868598066cSFelipe Balbi { 1878598066cSFelipe Balbi /* A pending interrupt would prevent OMAP from entering suspend */ 1888598066cSFelipe Balbi omap_ack_irq(NULL); 1898598066cSFelipe Balbi } 1908598066cSFelipe Balbi 1918598066cSFelipe Balbi static int __init omap_alloc_gc_of(struct irq_domain *d, void __iomem *base) 1928598066cSFelipe Balbi { 1938598066cSFelipe Balbi int ret; 1948598066cSFelipe Balbi int i; 1958598066cSFelipe Balbi 1968598066cSFelipe Balbi ret = irq_alloc_domain_generic_chips(d, 32, 1, "INTC", 1978598066cSFelipe Balbi handle_level_irq, IRQ_NOREQUEST | IRQ_NOPROBE, 1988598066cSFelipe Balbi IRQ_LEVEL, 0); 1998598066cSFelipe Balbi if (ret) { 2008598066cSFelipe Balbi pr_warn("Failed to allocate irq chips\n"); 2018598066cSFelipe Balbi return ret; 2028598066cSFelipe Balbi } 2038598066cSFelipe Balbi 2048598066cSFelipe Balbi for (i = 0; i < omap_nr_pending; i++) { 2058598066cSFelipe Balbi struct irq_chip_generic *gc; 2068598066cSFelipe Balbi struct irq_chip_type *ct; 2078598066cSFelipe Balbi 2088598066cSFelipe Balbi gc = irq_get_domain_generic_chip(d, 32 * i); 2098598066cSFelipe Balbi gc->reg_base = base; 2108598066cSFelipe Balbi ct = gc->chip_types; 2118598066cSFelipe Balbi 2128598066cSFelipe Balbi ct->type = IRQ_TYPE_LEVEL_MASK; 2138598066cSFelipe Balbi ct->handler = handle_level_irq; 2148598066cSFelipe Balbi 2158598066cSFelipe Balbi ct->chip.irq_ack = omap_mask_ack_irq; 2168598066cSFelipe Balbi ct->chip.irq_mask = irq_gc_mask_disable_reg; 2178598066cSFelipe Balbi ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 2188598066cSFelipe Balbi 2198598066cSFelipe Balbi ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; 2208598066cSFelipe Balbi 2218598066cSFelipe Balbi ct->regs.enable = INTC_MIR_CLEAR0 + 32 * i; 2228598066cSFelipe Balbi ct->regs.disable = INTC_MIR_SET0 + 32 * i; 2238598066cSFelipe Balbi } 2248598066cSFelipe Balbi 2258598066cSFelipe Balbi return 0; 2268598066cSFelipe Balbi } 2278598066cSFelipe Balbi 2288598066cSFelipe Balbi static void __init omap_alloc_gc_legacy(void __iomem *base, 2298598066cSFelipe Balbi unsigned int irq_start, unsigned int num) 2308598066cSFelipe Balbi { 2318598066cSFelipe Balbi struct irq_chip_generic *gc; 2328598066cSFelipe Balbi struct irq_chip_type *ct; 2338598066cSFelipe Balbi 2348598066cSFelipe Balbi gc = irq_alloc_generic_chip("INTC", 1, irq_start, base, 2358598066cSFelipe Balbi handle_level_irq); 2368598066cSFelipe Balbi ct = gc->chip_types; 2378598066cSFelipe Balbi ct->chip.irq_ack = omap_mask_ack_irq; 2388598066cSFelipe Balbi ct->chip.irq_mask = irq_gc_mask_disable_reg; 2398598066cSFelipe Balbi ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 2408598066cSFelipe Balbi ct->chip.flags |= IRQCHIP_SKIP_SET_WAKE; 2418598066cSFelipe Balbi 2428598066cSFelipe Balbi ct->regs.enable = INTC_MIR_CLEAR0; 2438598066cSFelipe Balbi ct->regs.disable = INTC_MIR_SET0; 2448598066cSFelipe Balbi irq_setup_generic_chip(gc, IRQ_MSK(num), IRQ_GC_INIT_MASK_CACHE, 2458598066cSFelipe Balbi IRQ_NOREQUEST | IRQ_NOPROBE, 0); 2468598066cSFelipe Balbi } 2478598066cSFelipe Balbi 2488598066cSFelipe Balbi static int __init omap_init_irq_of(struct device_node *node) 2498598066cSFelipe Balbi { 2508598066cSFelipe Balbi int ret; 2518598066cSFelipe Balbi 2528598066cSFelipe Balbi omap_irq_base = of_iomap(node, 0); 2538598066cSFelipe Balbi if (WARN_ON(!omap_irq_base)) 2548598066cSFelipe Balbi return -ENOMEM; 2558598066cSFelipe Balbi 2568598066cSFelipe Balbi domain = irq_domain_add_linear(node, omap_nr_irqs, 2578598066cSFelipe Balbi &irq_generic_chip_ops, NULL); 2588598066cSFelipe Balbi 2598598066cSFelipe Balbi omap_irq_soft_reset(); 2608598066cSFelipe Balbi 2618598066cSFelipe Balbi ret = omap_alloc_gc_of(domain, omap_irq_base); 2628598066cSFelipe Balbi if (ret < 0) 2638598066cSFelipe Balbi irq_domain_remove(domain); 2648598066cSFelipe Balbi 2658598066cSFelipe Balbi return ret; 2668598066cSFelipe Balbi } 2678598066cSFelipe Balbi 2688598066cSFelipe Balbi static int __init omap_init_irq_legacy(u32 base) 2698598066cSFelipe Balbi { 2708598066cSFelipe Balbi int j, irq_base; 2718598066cSFelipe Balbi 2728598066cSFelipe Balbi omap_irq_base = ioremap(base, SZ_4K); 2738598066cSFelipe Balbi if (WARN_ON(!omap_irq_base)) 2748598066cSFelipe Balbi return -ENOMEM; 2758598066cSFelipe Balbi 2768598066cSFelipe Balbi irq_base = irq_alloc_descs(-1, 0, omap_nr_irqs, 0); 2778598066cSFelipe Balbi if (irq_base < 0) { 2788598066cSFelipe Balbi pr_warn("Couldn't allocate IRQ numbers\n"); 2798598066cSFelipe Balbi irq_base = 0; 2808598066cSFelipe Balbi } 2818598066cSFelipe Balbi 2828598066cSFelipe Balbi domain = irq_domain_add_legacy(NULL, omap_nr_irqs, irq_base, 0, 2838598066cSFelipe Balbi &irq_domain_simple_ops, NULL); 2848598066cSFelipe Balbi 2858598066cSFelipe Balbi omap_irq_soft_reset(); 2868598066cSFelipe Balbi 2878598066cSFelipe Balbi for (j = 0; j < omap_nr_irqs; j += 32) 2888598066cSFelipe Balbi omap_alloc_gc_legacy(omap_irq_base + j, j + irq_base, 32); 2898598066cSFelipe Balbi 2908598066cSFelipe Balbi return 0; 2918598066cSFelipe Balbi } 2928598066cSFelipe Balbi 2938598066cSFelipe Balbi static int __init omap_init_irq(u32 base, struct device_node *node) 2948598066cSFelipe Balbi { 2958598066cSFelipe Balbi if (node) 2968598066cSFelipe Balbi return omap_init_irq_of(node); 2978598066cSFelipe Balbi else 2988598066cSFelipe Balbi return omap_init_irq_legacy(base); 2998598066cSFelipe Balbi } 3008598066cSFelipe Balbi 3018598066cSFelipe Balbi static asmlinkage void __exception_irq_entry 3028598066cSFelipe Balbi omap_intc_handle_irq(struct pt_regs *regs) 3038598066cSFelipe Balbi { 3048598066cSFelipe Balbi u32 irqnr = 0; 3058598066cSFelipe Balbi int handled_irq = 0; 3068598066cSFelipe Balbi int i; 3078598066cSFelipe Balbi 3088598066cSFelipe Balbi do { 3098598066cSFelipe Balbi for (i = 0; i < omap_nr_pending; i++) { 3108598066cSFelipe Balbi irqnr = intc_readl(INTC_PENDING_IRQ0 + (0x20 * i)); 3118598066cSFelipe Balbi if (irqnr) 3128598066cSFelipe Balbi goto out; 3138598066cSFelipe Balbi } 3148598066cSFelipe Balbi 3158598066cSFelipe Balbi out: 3168598066cSFelipe Balbi if (!irqnr) 3178598066cSFelipe Balbi break; 3188598066cSFelipe Balbi 3198598066cSFelipe Balbi irqnr = intc_readl(INTC_SIR); 3208598066cSFelipe Balbi irqnr &= ACTIVEIRQ_MASK; 3218598066cSFelipe Balbi 3228598066cSFelipe Balbi if (irqnr) { 3238598066cSFelipe Balbi irqnr = irq_find_mapping(domain, irqnr); 3248598066cSFelipe Balbi handle_IRQ(irqnr, regs); 3258598066cSFelipe Balbi handled_irq = 1; 3268598066cSFelipe Balbi } 3278598066cSFelipe Balbi } while (irqnr); 3288598066cSFelipe Balbi 329503b8d12SFelipe Balbi /* 330503b8d12SFelipe Balbi * If an irq is masked or deasserted while active, we will 3318598066cSFelipe Balbi * keep ending up here with no irq handled. So remove it from 332503b8d12SFelipe Balbi * the INTC with an ack. 333503b8d12SFelipe Balbi */ 3348598066cSFelipe Balbi if (!handled_irq) 3358598066cSFelipe Balbi omap_ack_irq(NULL); 3368598066cSFelipe Balbi } 3378598066cSFelipe Balbi 3388598066cSFelipe Balbi void __init omap2_init_irq(void) 3398598066cSFelipe Balbi { 3408598066cSFelipe Balbi omap_nr_irqs = 96; 3418598066cSFelipe Balbi omap_nr_pending = 3; 3428598066cSFelipe Balbi omap_init_irq(OMAP24XX_IC_BASE, NULL); 3438598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3448598066cSFelipe Balbi } 3458598066cSFelipe Balbi 3468598066cSFelipe Balbi void __init omap3_init_irq(void) 3478598066cSFelipe Balbi { 3488598066cSFelipe Balbi omap_nr_irqs = 96; 3498598066cSFelipe Balbi omap_nr_pending = 3; 3508598066cSFelipe Balbi omap_init_irq(OMAP34XX_IC_BASE, NULL); 3518598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3528598066cSFelipe Balbi } 3538598066cSFelipe Balbi 3548598066cSFelipe Balbi void __init ti81xx_init_irq(void) 3558598066cSFelipe Balbi { 3568598066cSFelipe Balbi omap_nr_irqs = 96; 3578598066cSFelipe Balbi omap_nr_pending = 4; 3588598066cSFelipe Balbi omap_init_irq(OMAP34XX_IC_BASE, NULL); 3598598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3608598066cSFelipe Balbi } 3618598066cSFelipe Balbi 3628598066cSFelipe Balbi static int __init intc_of_init(struct device_node *node, 3638598066cSFelipe Balbi struct device_node *parent) 3648598066cSFelipe Balbi { 3658598066cSFelipe Balbi struct resource res; 3668598066cSFelipe Balbi int ret; 3678598066cSFelipe Balbi 3688598066cSFelipe Balbi omap_nr_pending = 3; 3698598066cSFelipe Balbi omap_nr_irqs = 96; 3708598066cSFelipe Balbi 3718598066cSFelipe Balbi if (WARN_ON(!node)) 3728598066cSFelipe Balbi return -ENODEV; 3738598066cSFelipe Balbi 3748598066cSFelipe Balbi if (of_address_to_resource(node, 0, &res)) { 3758598066cSFelipe Balbi WARN(1, "unable to get intc registers\n"); 3768598066cSFelipe Balbi return -EINVAL; 3778598066cSFelipe Balbi } 3788598066cSFelipe Balbi 3798598066cSFelipe Balbi if (of_device_is_compatible(node, "ti,am33xx-intc")) { 3808598066cSFelipe Balbi omap_nr_irqs = 128; 3818598066cSFelipe Balbi omap_nr_pending = 4; 3828598066cSFelipe Balbi } 3838598066cSFelipe Balbi 3848598066cSFelipe Balbi ret = omap_init_irq(-1, of_node_get(node)); 3858598066cSFelipe Balbi if (ret < 0) 3868598066cSFelipe Balbi return ret; 3878598066cSFelipe Balbi 3888598066cSFelipe Balbi set_handle_irq(omap_intc_handle_irq); 3898598066cSFelipe Balbi 3908598066cSFelipe Balbi return 0; 3918598066cSFelipe Balbi } 3928598066cSFelipe Balbi 3938598066cSFelipe Balbi IRQCHIP_DECLARE(omap2_intc, "ti,omap2-intc", intc_of_init); 3948598066cSFelipe Balbi IRQCHIP_DECLARE(omap3_intc, "ti,omap3-intc", intc_of_init); 3958598066cSFelipe Balbi IRQCHIP_DECLARE(am33xx_intc, "ti,am33xx-intc", intc_of_init); 396