1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved. 4 * Copyright (C) 2014 Oleksij Rempel <linux@rempel-privat.de> 5 * Add Alphascale ASM9260 support. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/init.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqchip/mxs.h> 13 #include <linux/irqdomain.h> 14 #include <linux/io.h> 15 #include <linux/of.h> 16 #include <linux/of_address.h> 17 #include <linux/of_irq.h> 18 #include <linux/stmp_device.h> 19 #include <asm/exception.h> 20 21 #include "alphascale_asm9260-icoll.h" 22 23 /* 24 * this device provide 4 offsets for each register: 25 * 0x0 - plain read write mode 26 * 0x4 - set mode, OR logic. 27 * 0x8 - clr mode, XOR logic. 28 * 0xc - togle mode. 29 */ 30 #define SET_REG 4 31 #define CLR_REG 8 32 33 #define HW_ICOLL_VECTOR 0x0000 34 #define HW_ICOLL_LEVELACK 0x0010 35 #define HW_ICOLL_CTRL 0x0020 36 #define HW_ICOLL_STAT_OFFSET 0x0070 37 #define HW_ICOLL_INTERRUPT0 0x0120 38 #define HW_ICOLL_INTERRUPTn(n) ((n) * 0x10) 39 #define BM_ICOLL_INTR_ENABLE BIT(2) 40 #define BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 0x1 41 42 #define ICOLL_NUM_IRQS 128 43 44 enum icoll_type { 45 ICOLL, 46 ASM9260_ICOLL, 47 }; 48 49 struct icoll_priv { 50 void __iomem *vector; 51 void __iomem *levelack; 52 void __iomem *ctrl; 53 void __iomem *stat; 54 void __iomem *intr; 55 void __iomem *clear; 56 enum icoll_type type; 57 }; 58 59 static struct icoll_priv icoll_priv; 60 static struct irq_domain *icoll_domain; 61 62 /* calculate bit offset depending on number of interrupt per register */ 63 static u32 icoll_intr_bitshift(struct irq_data *d, u32 bit) 64 { 65 /* 66 * mask lower part of hwirq to convert it 67 * in 0, 1, 2 or 3 and then multiply it by 8 (or shift by 3) 68 */ 69 return bit << ((d->hwirq & 3) << 3); 70 } 71 72 /* calculate mem offset depending on number of interrupt per register */ 73 static void __iomem *icoll_intr_reg(struct irq_data *d) 74 { 75 /* offset = hwirq / intr_per_reg * 0x10 */ 76 return icoll_priv.intr + ((d->hwirq >> 2) * 0x10); 77 } 78 79 static void icoll_ack_irq(struct irq_data *d) 80 { 81 /* 82 * The Interrupt Collector is able to prioritize irqs. 83 * Currently only level 0 is used. So acking can use 84 * BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0 unconditionally. 85 */ 86 __raw_writel(BV_ICOLL_LEVELACK_IRQLEVELACK__LEVEL0, 87 icoll_priv.levelack); 88 } 89 90 static void icoll_mask_irq(struct irq_data *d) 91 { 92 __raw_writel(BM_ICOLL_INTR_ENABLE, 93 icoll_priv.intr + CLR_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); 94 } 95 96 static void icoll_unmask_irq(struct irq_data *d) 97 { 98 __raw_writel(BM_ICOLL_INTR_ENABLE, 99 icoll_priv.intr + SET_REG + HW_ICOLL_INTERRUPTn(d->hwirq)); 100 } 101 102 static void asm9260_mask_irq(struct irq_data *d) 103 { 104 __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE), 105 icoll_intr_reg(d) + CLR_REG); 106 } 107 108 static void asm9260_unmask_irq(struct irq_data *d) 109 { 110 __raw_writel(ASM9260_BM_CLEAR_BIT(d->hwirq), 111 icoll_priv.clear + 112 ASM9260_HW_ICOLL_CLEARn(d->hwirq)); 113 114 __raw_writel(icoll_intr_bitshift(d, BM_ICOLL_INTR_ENABLE), 115 icoll_intr_reg(d) + SET_REG); 116 } 117 118 static struct irq_chip mxs_icoll_chip = { 119 .irq_ack = icoll_ack_irq, 120 .irq_mask = icoll_mask_irq, 121 .irq_unmask = icoll_unmask_irq, 122 .flags = IRQCHIP_MASK_ON_SUSPEND | 123 IRQCHIP_SKIP_SET_WAKE, 124 }; 125 126 static struct irq_chip asm9260_icoll_chip = { 127 .irq_ack = icoll_ack_irq, 128 .irq_mask = asm9260_mask_irq, 129 .irq_unmask = asm9260_unmask_irq, 130 .flags = IRQCHIP_MASK_ON_SUSPEND | 131 IRQCHIP_SKIP_SET_WAKE, 132 }; 133 134 asmlinkage void __exception_irq_entry icoll_handle_irq(struct pt_regs *regs) 135 { 136 u32 irqnr; 137 138 irqnr = __raw_readl(icoll_priv.stat); 139 __raw_writel(irqnr, icoll_priv.vector); 140 generic_handle_domain_irq(icoll_domain, irqnr); 141 } 142 143 static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq, 144 irq_hw_number_t hw) 145 { 146 struct irq_chip *chip; 147 148 if (icoll_priv.type == ICOLL) 149 chip = &mxs_icoll_chip; 150 else 151 chip = &asm9260_icoll_chip; 152 153 irq_set_chip_and_handler(virq, chip, handle_level_irq); 154 155 return 0; 156 } 157 158 static const struct irq_domain_ops icoll_irq_domain_ops = { 159 .map = icoll_irq_domain_map, 160 .xlate = irq_domain_xlate_onecell, 161 }; 162 163 static void __init icoll_add_domain(struct device_node *np, 164 int num) 165 { 166 icoll_domain = irq_domain_add_linear(np, num, 167 &icoll_irq_domain_ops, NULL); 168 169 if (!icoll_domain) 170 panic("%pOF: unable to create irq domain", np); 171 } 172 173 static void __iomem * __init icoll_init_iobase(struct device_node *np) 174 { 175 void __iomem *icoll_base; 176 177 icoll_base = of_io_request_and_map(np, 0, np->name); 178 if (IS_ERR(icoll_base)) 179 panic("%pOF: unable to map resource", np); 180 return icoll_base; 181 } 182 183 static int __init icoll_of_init(struct device_node *np, 184 struct device_node *interrupt_parent) 185 { 186 void __iomem *icoll_base; 187 188 icoll_priv.type = ICOLL; 189 190 icoll_base = icoll_init_iobase(np); 191 icoll_priv.vector = icoll_base + HW_ICOLL_VECTOR; 192 icoll_priv.levelack = icoll_base + HW_ICOLL_LEVELACK; 193 icoll_priv.ctrl = icoll_base + HW_ICOLL_CTRL; 194 icoll_priv.stat = icoll_base + HW_ICOLL_STAT_OFFSET; 195 icoll_priv.intr = icoll_base + HW_ICOLL_INTERRUPT0; 196 icoll_priv.clear = NULL; 197 198 /* 199 * Interrupt Collector reset, which initializes the priority 200 * for each irq to level 0. 201 */ 202 stmp_reset_block(icoll_priv.ctrl); 203 204 icoll_add_domain(np, ICOLL_NUM_IRQS); 205 206 return 0; 207 } 208 IRQCHIP_DECLARE(mxs, "fsl,icoll", icoll_of_init); 209 210 static int __init asm9260_of_init(struct device_node *np, 211 struct device_node *interrupt_parent) 212 { 213 void __iomem *icoll_base; 214 int i; 215 216 icoll_priv.type = ASM9260_ICOLL; 217 218 icoll_base = icoll_init_iobase(np); 219 icoll_priv.vector = icoll_base + ASM9260_HW_ICOLL_VECTOR; 220 icoll_priv.levelack = icoll_base + ASM9260_HW_ICOLL_LEVELACK; 221 icoll_priv.ctrl = icoll_base + ASM9260_HW_ICOLL_CTRL; 222 icoll_priv.stat = icoll_base + ASM9260_HW_ICOLL_STAT_OFFSET; 223 icoll_priv.intr = icoll_base + ASM9260_HW_ICOLL_INTERRUPT0; 224 icoll_priv.clear = icoll_base + ASM9260_HW_ICOLL_CLEAR0; 225 226 writel_relaxed(ASM9260_BM_CTRL_IRQ_ENABLE, 227 icoll_priv.ctrl); 228 /* 229 * ASM9260 don't provide reset bit. So, we need to set level 0 230 * manually. 231 */ 232 for (i = 0; i < 16 * 0x10; i += 0x10) 233 writel(0, icoll_priv.intr + i); 234 235 icoll_add_domain(np, ASM9260_NUM_IRQS); 236 set_handle_irq(icoll_handle_irq); 237 238 return 0; 239 } 240 IRQCHIP_DECLARE(asm9260, "alphascale,asm9260-icoll", asm9260_of_init); 241