1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * linux/arch/arm/mach-mmp/irq.c 4 * 5 * Generic IRQ handling, GPIO IRQ demultiplexing, etc. 6 * Copyright (C) 2008 - 2012 Marvell Technology Group Ltd. 7 * 8 * Author: Bin Yang <bin.yang@marvell.com> 9 * Haojian Zhuang <haojian.zhuang@gmail.com> 10 */ 11 12 #include <linux/module.h> 13 #include <linux/init.h> 14 #include <linux/irq.h> 15 #include <linux/irqchip.h> 16 #include <linux/irqdomain.h> 17 #include <linux/io.h> 18 #include <linux/ioport.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 22 #include <asm/exception.h> 23 #include <asm/hardirq.h> 24 25 #define MAX_ICU_NR 16 26 27 #define PJ1_INT_SEL 0x10c 28 #define PJ4_INT_SEL 0x104 29 30 /* bit fields in PJ1_INT_SEL and PJ4_INT_SEL */ 31 #define SEL_INT_PENDING (1 << 6) 32 #define SEL_INT_NUM_MASK 0x3f 33 34 #define MMP2_ICU_INT_ROUTE_PJ4_IRQ (1 << 5) 35 #define MMP2_ICU_INT_ROUTE_PJ4_FIQ (1 << 6) 36 37 struct icu_chip_data { 38 int nr_irqs; 39 unsigned int virq_base; 40 unsigned int cascade_irq; 41 void __iomem *reg_status; 42 void __iomem *reg_mask; 43 unsigned int conf_enable; 44 unsigned int conf_disable; 45 unsigned int conf_mask; 46 unsigned int clr_mfp_irq_base; 47 unsigned int clr_mfp_hwirq; 48 struct irq_domain *domain; 49 }; 50 51 struct mmp_intc_conf { 52 unsigned int conf_enable; 53 unsigned int conf_disable; 54 unsigned int conf_mask; 55 }; 56 57 static void __iomem *mmp_icu_base; 58 static struct icu_chip_data icu_data[MAX_ICU_NR]; 59 static int max_icu_nr; 60 61 extern void mmp2_clear_pmic_int(void); 62 63 static void icu_mask_ack_irq(struct irq_data *d) 64 { 65 struct irq_domain *domain = d->domain; 66 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; 67 int hwirq; 68 u32 r; 69 70 hwirq = d->irq - data->virq_base; 71 if (data == &icu_data[0]) { 72 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); 73 r &= ~data->conf_mask; 74 r |= data->conf_disable; 75 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); 76 } else { 77 #ifdef CONFIG_CPU_MMP2 78 if ((data->virq_base == data->clr_mfp_irq_base) 79 && (hwirq == data->clr_mfp_hwirq)) 80 mmp2_clear_pmic_int(); 81 #endif 82 r = readl_relaxed(data->reg_mask) | (1 << hwirq); 83 writel_relaxed(r, data->reg_mask); 84 } 85 } 86 87 static void icu_mask_irq(struct irq_data *d) 88 { 89 struct irq_domain *domain = d->domain; 90 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; 91 int hwirq; 92 u32 r; 93 94 hwirq = d->irq - data->virq_base; 95 if (data == &icu_data[0]) { 96 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); 97 r &= ~data->conf_mask; 98 r |= data->conf_disable; 99 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); 100 } else { 101 r = readl_relaxed(data->reg_mask) | (1 << hwirq); 102 writel_relaxed(r, data->reg_mask); 103 } 104 } 105 106 static void icu_unmask_irq(struct irq_data *d) 107 { 108 struct irq_domain *domain = d->domain; 109 struct icu_chip_data *data = (struct icu_chip_data *)domain->host_data; 110 int hwirq; 111 u32 r; 112 113 hwirq = d->irq - data->virq_base; 114 if (data == &icu_data[0]) { 115 r = readl_relaxed(mmp_icu_base + (hwirq << 2)); 116 r &= ~data->conf_mask; 117 r |= data->conf_enable; 118 writel_relaxed(r, mmp_icu_base + (hwirq << 2)); 119 } else { 120 r = readl_relaxed(data->reg_mask) & ~(1 << hwirq); 121 writel_relaxed(r, data->reg_mask); 122 } 123 } 124 125 struct irq_chip icu_irq_chip = { 126 .name = "icu_irq", 127 .irq_mask = icu_mask_irq, 128 .irq_mask_ack = icu_mask_ack_irq, 129 .irq_unmask = icu_unmask_irq, 130 }; 131 132 static void icu_mux_irq_demux(struct irq_desc *desc) 133 { 134 unsigned int irq = irq_desc_get_irq(desc); 135 struct irq_domain *domain; 136 struct icu_chip_data *data; 137 int i; 138 unsigned long mask, status, n; 139 140 for (i = 1; i < max_icu_nr; i++) { 141 if (irq == icu_data[i].cascade_irq) { 142 domain = icu_data[i].domain; 143 data = (struct icu_chip_data *)domain->host_data; 144 break; 145 } 146 } 147 if (i >= max_icu_nr) { 148 pr_err("Spurious irq %d in MMP INTC\n", irq); 149 return; 150 } 151 152 mask = readl_relaxed(data->reg_mask); 153 while (1) { 154 status = readl_relaxed(data->reg_status) & ~mask; 155 if (status == 0) 156 break; 157 for_each_set_bit(n, &status, BITS_PER_LONG) { 158 generic_handle_irq(icu_data[i].virq_base + n); 159 } 160 } 161 } 162 163 static int mmp_irq_domain_map(struct irq_domain *d, unsigned int irq, 164 irq_hw_number_t hw) 165 { 166 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); 167 return 0; 168 } 169 170 static int mmp_irq_domain_xlate(struct irq_domain *d, struct device_node *node, 171 const u32 *intspec, unsigned int intsize, 172 unsigned long *out_hwirq, 173 unsigned int *out_type) 174 { 175 *out_hwirq = intspec[0]; 176 return 0; 177 } 178 179 static const struct irq_domain_ops mmp_irq_domain_ops = { 180 .map = mmp_irq_domain_map, 181 .xlate = mmp_irq_domain_xlate, 182 }; 183 184 static const struct mmp_intc_conf mmp_conf = { 185 .conf_enable = 0x51, 186 .conf_disable = 0x0, 187 .conf_mask = 0x7f, 188 }; 189 190 static const struct mmp_intc_conf mmp2_conf = { 191 .conf_enable = 0x20, 192 .conf_disable = 0x0, 193 .conf_mask = MMP2_ICU_INT_ROUTE_PJ4_IRQ | 194 MMP2_ICU_INT_ROUTE_PJ4_FIQ, 195 }; 196 197 static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs) 198 { 199 int hwirq; 200 201 hwirq = readl_relaxed(mmp_icu_base + PJ1_INT_SEL); 202 if (!(hwirq & SEL_INT_PENDING)) 203 return; 204 hwirq &= SEL_INT_NUM_MASK; 205 handle_domain_irq(icu_data[0].domain, hwirq, regs); 206 } 207 208 static void __exception_irq_entry mmp2_handle_irq(struct pt_regs *regs) 209 { 210 int hwirq; 211 212 hwirq = readl_relaxed(mmp_icu_base + PJ4_INT_SEL); 213 if (!(hwirq & SEL_INT_PENDING)) 214 return; 215 hwirq &= SEL_INT_NUM_MASK; 216 handle_domain_irq(icu_data[0].domain, hwirq, regs); 217 } 218 219 /* MMP (ARMv5) */ 220 void __init icu_init_irq(void) 221 { 222 int irq; 223 224 max_icu_nr = 1; 225 mmp_icu_base = ioremap(0xd4282000, 0x1000); 226 icu_data[0].conf_enable = mmp_conf.conf_enable; 227 icu_data[0].conf_disable = mmp_conf.conf_disable; 228 icu_data[0].conf_mask = mmp_conf.conf_mask; 229 icu_data[0].nr_irqs = 64; 230 icu_data[0].virq_base = 0; 231 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, 232 &irq_domain_simple_ops, 233 &icu_data[0]); 234 for (irq = 0; irq < 64; irq++) { 235 icu_mask_irq(irq_get_irq_data(irq)); 236 irq_set_chip_and_handler(irq, &icu_irq_chip, handle_level_irq); 237 } 238 irq_set_default_host(icu_data[0].domain); 239 set_handle_irq(mmp_handle_irq); 240 } 241 242 /* MMP2 (ARMv7) */ 243 void __init mmp2_init_icu(void) 244 { 245 int irq, end; 246 247 max_icu_nr = 8; 248 mmp_icu_base = ioremap(0xd4282000, 0x1000); 249 icu_data[0].conf_enable = mmp2_conf.conf_enable; 250 icu_data[0].conf_disable = mmp2_conf.conf_disable; 251 icu_data[0].conf_mask = mmp2_conf.conf_mask; 252 icu_data[0].nr_irqs = 64; 253 icu_data[0].virq_base = 0; 254 icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0, 255 &irq_domain_simple_ops, 256 &icu_data[0]); 257 icu_data[1].reg_status = mmp_icu_base + 0x150; 258 icu_data[1].reg_mask = mmp_icu_base + 0x168; 259 icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base + 260 icu_data[0].nr_irqs; 261 icu_data[1].clr_mfp_hwirq = 1; /* offset to IRQ_MMP2_PMIC_BASE */ 262 icu_data[1].nr_irqs = 2; 263 icu_data[1].cascade_irq = 4; 264 icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs; 265 icu_data[1].domain = irq_domain_add_legacy(NULL, icu_data[1].nr_irqs, 266 icu_data[1].virq_base, 0, 267 &irq_domain_simple_ops, 268 &icu_data[1]); 269 icu_data[2].reg_status = mmp_icu_base + 0x154; 270 icu_data[2].reg_mask = mmp_icu_base + 0x16c; 271 icu_data[2].nr_irqs = 2; 272 icu_data[2].cascade_irq = 5; 273 icu_data[2].virq_base = icu_data[1].virq_base + icu_data[1].nr_irqs; 274 icu_data[2].domain = irq_domain_add_legacy(NULL, icu_data[2].nr_irqs, 275 icu_data[2].virq_base, 0, 276 &irq_domain_simple_ops, 277 &icu_data[2]); 278 icu_data[3].reg_status = mmp_icu_base + 0x180; 279 icu_data[3].reg_mask = mmp_icu_base + 0x17c; 280 icu_data[3].nr_irqs = 3; 281 icu_data[3].cascade_irq = 9; 282 icu_data[3].virq_base = icu_data[2].virq_base + icu_data[2].nr_irqs; 283 icu_data[3].domain = irq_domain_add_legacy(NULL, icu_data[3].nr_irqs, 284 icu_data[3].virq_base, 0, 285 &irq_domain_simple_ops, 286 &icu_data[3]); 287 icu_data[4].reg_status = mmp_icu_base + 0x158; 288 icu_data[4].reg_mask = mmp_icu_base + 0x170; 289 icu_data[4].nr_irqs = 5; 290 icu_data[4].cascade_irq = 17; 291 icu_data[4].virq_base = icu_data[3].virq_base + icu_data[3].nr_irqs; 292 icu_data[4].domain = irq_domain_add_legacy(NULL, icu_data[4].nr_irqs, 293 icu_data[4].virq_base, 0, 294 &irq_domain_simple_ops, 295 &icu_data[4]); 296 icu_data[5].reg_status = mmp_icu_base + 0x15c; 297 icu_data[5].reg_mask = mmp_icu_base + 0x174; 298 icu_data[5].nr_irqs = 15; 299 icu_data[5].cascade_irq = 35; 300 icu_data[5].virq_base = icu_data[4].virq_base + icu_data[4].nr_irqs; 301 icu_data[5].domain = irq_domain_add_legacy(NULL, icu_data[5].nr_irqs, 302 icu_data[5].virq_base, 0, 303 &irq_domain_simple_ops, 304 &icu_data[5]); 305 icu_data[6].reg_status = mmp_icu_base + 0x160; 306 icu_data[6].reg_mask = mmp_icu_base + 0x178; 307 icu_data[6].nr_irqs = 2; 308 icu_data[6].cascade_irq = 51; 309 icu_data[6].virq_base = icu_data[5].virq_base + icu_data[5].nr_irqs; 310 icu_data[6].domain = irq_domain_add_legacy(NULL, icu_data[6].nr_irqs, 311 icu_data[6].virq_base, 0, 312 &irq_domain_simple_ops, 313 &icu_data[6]); 314 icu_data[7].reg_status = mmp_icu_base + 0x188; 315 icu_data[7].reg_mask = mmp_icu_base + 0x184; 316 icu_data[7].nr_irqs = 2; 317 icu_data[7].cascade_irq = 55; 318 icu_data[7].virq_base = icu_data[6].virq_base + icu_data[6].nr_irqs; 319 icu_data[7].domain = irq_domain_add_legacy(NULL, icu_data[7].nr_irqs, 320 icu_data[7].virq_base, 0, 321 &irq_domain_simple_ops, 322 &icu_data[7]); 323 end = icu_data[7].virq_base + icu_data[7].nr_irqs; 324 for (irq = 0; irq < end; irq++) { 325 icu_mask_irq(irq_get_irq_data(irq)); 326 if (irq == icu_data[1].cascade_irq || 327 irq == icu_data[2].cascade_irq || 328 irq == icu_data[3].cascade_irq || 329 irq == icu_data[4].cascade_irq || 330 irq == icu_data[5].cascade_irq || 331 irq == icu_data[6].cascade_irq || 332 irq == icu_data[7].cascade_irq) { 333 irq_set_chip(irq, &icu_irq_chip); 334 irq_set_chained_handler(irq, icu_mux_irq_demux); 335 } else { 336 irq_set_chip_and_handler(irq, &icu_irq_chip, 337 handle_level_irq); 338 } 339 } 340 irq_set_default_host(icu_data[0].domain); 341 set_handle_irq(mmp2_handle_irq); 342 } 343 344 #ifdef CONFIG_OF 345 static int __init mmp_init_bases(struct device_node *node) 346 { 347 int ret, nr_irqs, irq, i = 0; 348 349 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", &nr_irqs); 350 if (ret) { 351 pr_err("Not found mrvl,intc-nr-irqs property\n"); 352 return ret; 353 } 354 355 mmp_icu_base = of_iomap(node, 0); 356 if (!mmp_icu_base) { 357 pr_err("Failed to get interrupt controller register\n"); 358 return -ENOMEM; 359 } 360 361 icu_data[0].virq_base = 0; 362 icu_data[0].domain = irq_domain_add_linear(node, nr_irqs, 363 &mmp_irq_domain_ops, 364 &icu_data[0]); 365 for (irq = 0; irq < nr_irqs; irq++) { 366 ret = irq_create_mapping(icu_data[0].domain, irq); 367 if (!ret) { 368 pr_err("Failed to mapping hwirq\n"); 369 goto err; 370 } 371 if (!irq) 372 icu_data[0].virq_base = ret; 373 } 374 icu_data[0].nr_irqs = nr_irqs; 375 return 0; 376 err: 377 if (icu_data[0].virq_base) { 378 for (i = 0; i < irq; i++) 379 irq_dispose_mapping(icu_data[0].virq_base + i); 380 } 381 irq_domain_remove(icu_data[0].domain); 382 iounmap(mmp_icu_base); 383 return -EINVAL; 384 } 385 386 static int __init mmp_of_init(struct device_node *node, 387 struct device_node *parent) 388 { 389 int ret; 390 391 ret = mmp_init_bases(node); 392 if (ret < 0) 393 return ret; 394 395 icu_data[0].conf_enable = mmp_conf.conf_enable; 396 icu_data[0].conf_disable = mmp_conf.conf_disable; 397 icu_data[0].conf_mask = mmp_conf.conf_mask; 398 irq_set_default_host(icu_data[0].domain); 399 set_handle_irq(mmp_handle_irq); 400 max_icu_nr = 1; 401 return 0; 402 } 403 IRQCHIP_DECLARE(mmp_intc, "mrvl,mmp-intc", mmp_of_init); 404 405 static int __init mmp2_of_init(struct device_node *node, 406 struct device_node *parent) 407 { 408 int ret; 409 410 ret = mmp_init_bases(node); 411 if (ret < 0) 412 return ret; 413 414 icu_data[0].conf_enable = mmp2_conf.conf_enable; 415 icu_data[0].conf_disable = mmp2_conf.conf_disable; 416 icu_data[0].conf_mask = mmp2_conf.conf_mask; 417 irq_set_default_host(icu_data[0].domain); 418 set_handle_irq(mmp2_handle_irq); 419 max_icu_nr = 1; 420 return 0; 421 } 422 IRQCHIP_DECLARE(mmp2_intc, "mrvl,mmp2-intc", mmp2_of_init); 423 424 static int __init mmp2_mux_of_init(struct device_node *node, 425 struct device_node *parent) 426 { 427 struct resource res; 428 int i, ret, irq, j = 0; 429 u32 nr_irqs, mfp_irq; 430 431 if (!parent) 432 return -ENODEV; 433 434 i = max_icu_nr; 435 ret = of_property_read_u32(node, "mrvl,intc-nr-irqs", 436 &nr_irqs); 437 if (ret) { 438 pr_err("Not found mrvl,intc-nr-irqs property\n"); 439 return -EINVAL; 440 } 441 ret = of_address_to_resource(node, 0, &res); 442 if (ret < 0) { 443 pr_err("Not found reg property\n"); 444 return -EINVAL; 445 } 446 icu_data[i].reg_status = mmp_icu_base + res.start; 447 ret = of_address_to_resource(node, 1, &res); 448 if (ret < 0) { 449 pr_err("Not found reg property\n"); 450 return -EINVAL; 451 } 452 icu_data[i].reg_mask = mmp_icu_base + res.start; 453 icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0); 454 if (!icu_data[i].cascade_irq) 455 return -EINVAL; 456 457 icu_data[i].virq_base = 0; 458 icu_data[i].domain = irq_domain_add_linear(node, nr_irqs, 459 &mmp_irq_domain_ops, 460 &icu_data[i]); 461 for (irq = 0; irq < nr_irqs; irq++) { 462 ret = irq_create_mapping(icu_data[i].domain, irq); 463 if (!ret) { 464 pr_err("Failed to mapping hwirq\n"); 465 goto err; 466 } 467 if (!irq) 468 icu_data[i].virq_base = ret; 469 } 470 icu_data[i].nr_irqs = nr_irqs; 471 if (!of_property_read_u32(node, "mrvl,clr-mfp-irq", 472 &mfp_irq)) { 473 icu_data[i].clr_mfp_irq_base = icu_data[i].virq_base; 474 icu_data[i].clr_mfp_hwirq = mfp_irq; 475 } 476 irq_set_chained_handler(icu_data[i].cascade_irq, 477 icu_mux_irq_demux); 478 max_icu_nr++; 479 return 0; 480 err: 481 if (icu_data[i].virq_base) { 482 for (j = 0; j < irq; j++) 483 irq_dispose_mapping(icu_data[i].virq_base + j); 484 } 485 irq_domain_remove(icu_data[i].domain); 486 return -EINVAL; 487 } 488 IRQCHIP_DECLARE(mmp2_mux_intc, "mrvl,mmp2-mux-intc", mmp2_mux_of_init); 489 #endif 490