1 /* 2 * Copyright 2001 MontaVista Software Inc. 3 * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net 4 * 5 * Copyright (C) 2001 Ralf Baechle 6 * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved. 7 * Author: Maciej W. Rozycki <macro@mips.com> 8 * 9 * This file define the irq handler for MIPS CPU interrupts. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 */ 16 17 /* 18 * Almost all MIPS CPUs define 8 interrupt sources. They are typically 19 * level triggered (i.e., cannot be cleared from CPU; must be cleared from 20 * device). The first two are software interrupts which we don't really 21 * use or support. The last one is usually the CPU timer interrupt if 22 * counter register is present or, for CPUs with an external FPU, by 23 * convention it's the FPU exception interrupt. 24 * 25 * Don't even think about using this on SMP. You have been warned. 26 * 27 * This file exports one global function: 28 * void mips_cpu_irq_init(void); 29 */ 30 #include <linux/init.h> 31 #include <linux/interrupt.h> 32 #include <linux/kernel.h> 33 #include <linux/irq.h> 34 #include <linux/irqdomain.h> 35 36 #include <asm/irq_cpu.h> 37 #include <asm/mipsregs.h> 38 #include <asm/mipsmtregs.h> 39 #include <asm/setup.h> 40 41 #include "irqchip.h" 42 43 static inline void unmask_mips_irq(struct irq_data *d) 44 { 45 set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 46 irq_enable_hazard(); 47 } 48 49 static inline void mask_mips_irq(struct irq_data *d) 50 { 51 clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 52 irq_disable_hazard(); 53 } 54 55 static struct irq_chip mips_cpu_irq_controller = { 56 .name = "MIPS", 57 .irq_ack = mask_mips_irq, 58 .irq_mask = mask_mips_irq, 59 .irq_mask_ack = mask_mips_irq, 60 .irq_unmask = unmask_mips_irq, 61 .irq_eoi = unmask_mips_irq, 62 .irq_disable = mask_mips_irq, 63 .irq_enable = unmask_mips_irq, 64 }; 65 66 /* 67 * Basically the same as above but taking care of all the MT stuff 68 */ 69 70 static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d) 71 { 72 unsigned int vpflags = dvpe(); 73 74 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 75 evpe(vpflags); 76 unmask_mips_irq(d); 77 return 0; 78 } 79 80 /* 81 * While we ack the interrupt interrupts are disabled and thus we don't need 82 * to deal with concurrency issues. Same for mips_cpu_irq_end. 83 */ 84 static void mips_mt_cpu_irq_ack(struct irq_data *d) 85 { 86 unsigned int vpflags = dvpe(); 87 clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE)); 88 evpe(vpflags); 89 mask_mips_irq(d); 90 } 91 92 static struct irq_chip mips_mt_cpu_irq_controller = { 93 .name = "MIPS", 94 .irq_startup = mips_mt_cpu_irq_startup, 95 .irq_ack = mips_mt_cpu_irq_ack, 96 .irq_mask = mask_mips_irq, 97 .irq_mask_ack = mips_mt_cpu_irq_ack, 98 .irq_unmask = unmask_mips_irq, 99 .irq_eoi = unmask_mips_irq, 100 .irq_disable = mask_mips_irq, 101 .irq_enable = unmask_mips_irq, 102 }; 103 104 asmlinkage void __weak plat_irq_dispatch(void) 105 { 106 unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM; 107 int irq; 108 109 if (!pending) { 110 spurious_interrupt(); 111 return; 112 } 113 114 pending >>= CAUSEB_IP; 115 while (pending) { 116 irq = fls(pending) - 1; 117 do_IRQ(MIPS_CPU_IRQ_BASE + irq); 118 pending &= ~BIT(irq); 119 } 120 } 121 122 static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq, 123 irq_hw_number_t hw) 124 { 125 static struct irq_chip *chip; 126 127 if (hw < 2 && cpu_has_mipsmt) { 128 /* Software interrupts are used for MT/CMT IPI */ 129 chip = &mips_mt_cpu_irq_controller; 130 } else { 131 chip = &mips_cpu_irq_controller; 132 } 133 134 if (cpu_has_vint) 135 set_vi_handler(hw, plat_irq_dispatch); 136 137 irq_set_chip_and_handler(irq, chip, handle_percpu_irq); 138 139 return 0; 140 } 141 142 static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = { 143 .map = mips_cpu_intc_map, 144 .xlate = irq_domain_xlate_onecell, 145 }; 146 147 static void __init __mips_cpu_irq_init(struct device_node *of_node) 148 { 149 struct irq_domain *domain; 150 151 /* Mask interrupts. */ 152 clear_c0_status(ST0_IM); 153 clear_c0_cause(CAUSEF_IP); 154 155 domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0, 156 &mips_cpu_intc_irq_domain_ops, NULL); 157 if (!domain) 158 panic("Failed to add irqdomain for MIPS CPU"); 159 } 160 161 void __init mips_cpu_irq_init(void) 162 { 163 __mips_cpu_irq_init(NULL); 164 } 165 166 int __init mips_cpu_irq_of_init(struct device_node *of_node, 167 struct device_node *parent) 168 { 169 __mips_cpu_irq_init(of_node); 170 return 0; 171 } 172 IRQCHIP_DECLARE(cpu_intc, "mti,cpu-interrupt-controller", mips_cpu_irq_of_init); 173