1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 Endless Mobile, Inc.
4  * Author: Carlo Caione <carlo@endlessm.com>
5  * Copyright (c) 2016 BayLibre, SAS.
6  * Author: Jerome Brunet <jbrunet@baylibre.com>
7  */
8 
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/irq.h>
14 #include <linux/irqdomain.h>
15 #include <linux/irqchip.h>
16 #include <linux/of.h>
17 #include <linux/of_address.h>
18 
19 #define NUM_CHANNEL 8
20 #define MAX_INPUT_MUX 256
21 
22 #define REG_EDGE_POL	0x00
23 #define REG_PIN_03_SEL	0x04
24 #define REG_PIN_47_SEL	0x08
25 #define REG_FILTER_SEL	0x0c
26 
27 /* use for A1 like chips */
28 #define REG_PIN_A1_SEL	0x04
29 
30 /*
31  * Note: The S905X3 datasheet reports that BOTH_EDGE is controlled by
32  * bits 24 to 31. Tests on the actual HW show that these bits are
33  * stuck at 0. Bits 8 to 15 are responsive and have the expected
34  * effect.
35  */
36 #define REG_EDGE_POL_EDGE(params, x)	BIT((params)->edge_single_offset + (x))
37 #define REG_EDGE_POL_LOW(params, x)	BIT((params)->pol_low_offset + (x))
38 #define REG_BOTH_EDGE(params, x)	BIT((params)->edge_both_offset + (x))
39 #define REG_EDGE_POL_MASK(params, x)    (	\
40 		REG_EDGE_POL_EDGE(params, x) |	\
41 		REG_EDGE_POL_LOW(params, x)  |	\
42 		REG_BOTH_EDGE(params, x))
43 #define REG_PIN_SEL_SHIFT(x)	(((x) % 4) * 8)
44 #define REG_FILTER_SEL_SHIFT(x)	((x) * 4)
45 
46 struct meson_gpio_irq_controller;
47 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
48 				    unsigned int channel, unsigned long hwirq);
49 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl);
50 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
51 				      unsigned int channel,
52 				      unsigned long hwirq);
53 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl);
54 
55 struct irq_ctl_ops {
56 	void (*gpio_irq_sel_pin)(struct meson_gpio_irq_controller *ctl,
57 				 unsigned int channel, unsigned long hwirq);
58 	void (*gpio_irq_init)(struct meson_gpio_irq_controller *ctl);
59 };
60 
61 struct meson_gpio_irq_params {
62 	unsigned int nr_hwirq;
63 	bool support_edge_both;
64 	unsigned int edge_both_offset;
65 	unsigned int edge_single_offset;
66 	unsigned int pol_low_offset;
67 	unsigned int pin_sel_mask;
68 	struct irq_ctl_ops ops;
69 };
70 
71 #define INIT_MESON_COMMON(irqs, init, sel)			\
72 	.nr_hwirq = irqs,					\
73 	.ops = {						\
74 		.gpio_irq_init = init,				\
75 		.gpio_irq_sel_pin = sel,			\
76 	},
77 
78 #define INIT_MESON8_COMMON_DATA(irqs)				\
79 	INIT_MESON_COMMON(irqs, meson_gpio_irq_init_dummy,	\
80 			  meson8_gpio_irq_sel_pin)		\
81 	.edge_single_offset = 0,				\
82 	.pol_low_offset = 16,					\
83 	.pin_sel_mask = 0xff,					\
84 
85 #define INIT_MESON_A1_COMMON_DATA(irqs)				\
86 	INIT_MESON_COMMON(irqs, meson_a1_gpio_irq_init,		\
87 			  meson_a1_gpio_irq_sel_pin)		\
88 	.support_edge_both = true,				\
89 	.edge_both_offset = 16,					\
90 	.edge_single_offset = 8,				\
91 	.pol_low_offset = 0,					\
92 	.pin_sel_mask = 0x7f,					\
93 
94 static const struct meson_gpio_irq_params meson8_params = {
95 	INIT_MESON8_COMMON_DATA(134)
96 };
97 
98 static const struct meson_gpio_irq_params meson8b_params = {
99 	INIT_MESON8_COMMON_DATA(119)
100 };
101 
102 static const struct meson_gpio_irq_params gxbb_params = {
103 	INIT_MESON8_COMMON_DATA(133)
104 };
105 
106 static const struct meson_gpio_irq_params gxl_params = {
107 	INIT_MESON8_COMMON_DATA(110)
108 };
109 
110 static const struct meson_gpio_irq_params axg_params = {
111 	INIT_MESON8_COMMON_DATA(100)
112 };
113 
114 static const struct meson_gpio_irq_params sm1_params = {
115 	INIT_MESON8_COMMON_DATA(100)
116 	.support_edge_both = true,
117 	.edge_both_offset = 8,
118 };
119 
120 static const struct meson_gpio_irq_params a1_params = {
121 	INIT_MESON_A1_COMMON_DATA(62)
122 };
123 
124 static const struct of_device_id meson_irq_gpio_matches[] = {
125 	{ .compatible = "amlogic,meson8-gpio-intc", .data = &meson8_params },
126 	{ .compatible = "amlogic,meson8b-gpio-intc", .data = &meson8b_params },
127 	{ .compatible = "amlogic,meson-gxbb-gpio-intc", .data = &gxbb_params },
128 	{ .compatible = "amlogic,meson-gxl-gpio-intc", .data = &gxl_params },
129 	{ .compatible = "amlogic,meson-axg-gpio-intc", .data = &axg_params },
130 	{ .compatible = "amlogic,meson-g12a-gpio-intc", .data = &axg_params },
131 	{ .compatible = "amlogic,meson-sm1-gpio-intc", .data = &sm1_params },
132 	{ .compatible = "amlogic,meson-a1-gpio-intc", .data = &a1_params },
133 	{ }
134 };
135 
136 struct meson_gpio_irq_controller {
137 	const struct meson_gpio_irq_params *params;
138 	void __iomem *base;
139 	u32 channel_irqs[NUM_CHANNEL];
140 	DECLARE_BITMAP(channel_map, NUM_CHANNEL);
141 	spinlock_t lock;
142 };
143 
144 static void meson_gpio_irq_update_bits(struct meson_gpio_irq_controller *ctl,
145 				       unsigned int reg, u32 mask, u32 val)
146 {
147 	unsigned long flags;
148 	u32 tmp;
149 
150 	spin_lock_irqsave(&ctl->lock, flags);
151 
152 	tmp = readl_relaxed(ctl->base + reg);
153 	tmp &= ~mask;
154 	tmp |= val;
155 	writel_relaxed(tmp, ctl->base + reg);
156 
157 	spin_unlock_irqrestore(&ctl->lock, flags);
158 }
159 
160 static void meson_gpio_irq_init_dummy(struct meson_gpio_irq_controller *ctl)
161 {
162 }
163 
164 static void meson8_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
165 				    unsigned int channel, unsigned long hwirq)
166 {
167 	unsigned int reg_offset;
168 	unsigned int bit_offset;
169 
170 	reg_offset = (channel < 4) ? REG_PIN_03_SEL : REG_PIN_47_SEL;
171 	bit_offset = REG_PIN_SEL_SHIFT(channel);
172 
173 	meson_gpio_irq_update_bits(ctl, reg_offset,
174 				   ctl->params->pin_sel_mask << bit_offset,
175 				   hwirq << bit_offset);
176 }
177 
178 static void meson_a1_gpio_irq_sel_pin(struct meson_gpio_irq_controller *ctl,
179 				      unsigned int channel,
180 				      unsigned long hwirq)
181 {
182 	unsigned int reg_offset;
183 	unsigned int bit_offset;
184 
185 	bit_offset = ((channel % 2) == 0) ? 0 : 16;
186 	reg_offset = REG_PIN_A1_SEL + ((channel / 2) << 2);
187 
188 	meson_gpio_irq_update_bits(ctl, reg_offset,
189 				   ctl->params->pin_sel_mask << bit_offset,
190 				   hwirq << bit_offset);
191 }
192 
193 /* For a1 or later chips like a1 there is a switch to enable/disable irq */
194 static void meson_a1_gpio_irq_init(struct meson_gpio_irq_controller *ctl)
195 {
196 	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL, BIT(31), BIT(31));
197 }
198 
199 static int
200 meson_gpio_irq_request_channel(struct meson_gpio_irq_controller *ctl,
201 			       unsigned long  hwirq,
202 			       u32 **channel_hwirq)
203 {
204 	unsigned long flags;
205 	unsigned int idx;
206 
207 	spin_lock_irqsave(&ctl->lock, flags);
208 
209 	/* Find a free channel */
210 	idx = find_first_zero_bit(ctl->channel_map, NUM_CHANNEL);
211 	if (idx >= NUM_CHANNEL) {
212 		spin_unlock_irqrestore(&ctl->lock, flags);
213 		pr_err("No channel available\n");
214 		return -ENOSPC;
215 	}
216 
217 	/* Mark the channel as used */
218 	set_bit(idx, ctl->channel_map);
219 
220 	spin_unlock_irqrestore(&ctl->lock, flags);
221 
222 	/*
223 	 * Setup the mux of the channel to route the signal of the pad
224 	 * to the appropriate input of the GIC
225 	 */
226 	ctl->params->ops.gpio_irq_sel_pin(ctl, idx, hwirq);
227 
228 	/*
229 	 * Get the hwirq number assigned to this channel through
230 	 * a pointer the channel_irq table. The added benifit of this
231 	 * method is that we can also retrieve the channel index with
232 	 * it, using the table base.
233 	 */
234 	*channel_hwirq = &(ctl->channel_irqs[idx]);
235 
236 	pr_debug("hwirq %lu assigned to channel %d - irq %u\n",
237 		 hwirq, idx, **channel_hwirq);
238 
239 	return 0;
240 }
241 
242 static unsigned int
243 meson_gpio_irq_get_channel_idx(struct meson_gpio_irq_controller *ctl,
244 			       u32 *channel_hwirq)
245 {
246 	return channel_hwirq - ctl->channel_irqs;
247 }
248 
249 static void
250 meson_gpio_irq_release_channel(struct meson_gpio_irq_controller *ctl,
251 			       u32 *channel_hwirq)
252 {
253 	unsigned int idx;
254 
255 	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
256 	clear_bit(idx, ctl->channel_map);
257 }
258 
259 static int meson_gpio_irq_type_setup(struct meson_gpio_irq_controller *ctl,
260 				     unsigned int type,
261 				     u32 *channel_hwirq)
262 {
263 	u32 val = 0;
264 	unsigned int idx;
265 	const struct meson_gpio_irq_params *params;
266 
267 	params = ctl->params;
268 	idx = meson_gpio_irq_get_channel_idx(ctl, channel_hwirq);
269 
270 	/*
271 	 * The controller has a filter block to operate in either LEVEL or
272 	 * EDGE mode, then signal is sent to the GIC. To enable LEVEL_LOW and
273 	 * EDGE_FALLING support (which the GIC does not support), the filter
274 	 * block is also able to invert the input signal it gets before
275 	 * providing it to the GIC.
276 	 */
277 	type &= IRQ_TYPE_SENSE_MASK;
278 
279 	/*
280 	 * New controller support EDGE_BOTH trigger. This setting takes
281 	 * precedence over the other edge/polarity settings
282 	 */
283 	if (type == IRQ_TYPE_EDGE_BOTH) {
284 		if (!params->support_edge_both)
285 			return -EINVAL;
286 
287 		val |= REG_BOTH_EDGE(params, idx);
288 	} else {
289 		if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING))
290 			val |= REG_EDGE_POL_EDGE(params, idx);
291 
292 		if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING))
293 			val |= REG_EDGE_POL_LOW(params, idx);
294 	}
295 
296 	meson_gpio_irq_update_bits(ctl, REG_EDGE_POL,
297 				   REG_EDGE_POL_MASK(params, idx), val);
298 
299 	return 0;
300 }
301 
302 static unsigned int meson_gpio_irq_type_output(unsigned int type)
303 {
304 	unsigned int sense = type & IRQ_TYPE_SENSE_MASK;
305 
306 	type &= ~IRQ_TYPE_SENSE_MASK;
307 
308 	/*
309 	 * The polarity of the signal provided to the GIC should always
310 	 * be high.
311 	 */
312 	if (sense & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
313 		type |= IRQ_TYPE_LEVEL_HIGH;
314 	else
315 		type |= IRQ_TYPE_EDGE_RISING;
316 
317 	return type;
318 }
319 
320 static int meson_gpio_irq_set_type(struct irq_data *data, unsigned int type)
321 {
322 	struct meson_gpio_irq_controller *ctl = data->domain->host_data;
323 	u32 *channel_hwirq = irq_data_get_irq_chip_data(data);
324 	int ret;
325 
326 	ret = meson_gpio_irq_type_setup(ctl, type, channel_hwirq);
327 	if (ret)
328 		return ret;
329 
330 	return irq_chip_set_type_parent(data,
331 					meson_gpio_irq_type_output(type));
332 }
333 
334 static struct irq_chip meson_gpio_irq_chip = {
335 	.name			= "meson-gpio-irqchip",
336 	.irq_mask		= irq_chip_mask_parent,
337 	.irq_unmask		= irq_chip_unmask_parent,
338 	.irq_eoi		= irq_chip_eoi_parent,
339 	.irq_set_type		= meson_gpio_irq_set_type,
340 	.irq_retrigger		= irq_chip_retrigger_hierarchy,
341 #ifdef CONFIG_SMP
342 	.irq_set_affinity	= irq_chip_set_affinity_parent,
343 #endif
344 	.flags			= IRQCHIP_SET_TYPE_MASKED,
345 };
346 
347 static int meson_gpio_irq_domain_translate(struct irq_domain *domain,
348 					   struct irq_fwspec *fwspec,
349 					   unsigned long *hwirq,
350 					   unsigned int *type)
351 {
352 	if (is_of_node(fwspec->fwnode) && fwspec->param_count == 2) {
353 		*hwirq	= fwspec->param[0];
354 		*type	= fwspec->param[1];
355 		return 0;
356 	}
357 
358 	return -EINVAL;
359 }
360 
361 static int meson_gpio_irq_allocate_gic_irq(struct irq_domain *domain,
362 					   unsigned int virq,
363 					   u32 hwirq,
364 					   unsigned int type)
365 {
366 	struct irq_fwspec fwspec;
367 
368 	fwspec.fwnode = domain->parent->fwnode;
369 	fwspec.param_count = 3;
370 	fwspec.param[0] = 0;	/* SPI */
371 	fwspec.param[1] = hwirq;
372 	fwspec.param[2] = meson_gpio_irq_type_output(type);
373 
374 	return irq_domain_alloc_irqs_parent(domain, virq, 1, &fwspec);
375 }
376 
377 static int meson_gpio_irq_domain_alloc(struct irq_domain *domain,
378 				       unsigned int virq,
379 				       unsigned int nr_irqs,
380 				       void *data)
381 {
382 	struct irq_fwspec *fwspec = data;
383 	struct meson_gpio_irq_controller *ctl = domain->host_data;
384 	unsigned long hwirq;
385 	u32 *channel_hwirq;
386 	unsigned int type;
387 	int ret;
388 
389 	if (WARN_ON(nr_irqs != 1))
390 		return -EINVAL;
391 
392 	ret = meson_gpio_irq_domain_translate(domain, fwspec, &hwirq, &type);
393 	if (ret)
394 		return ret;
395 
396 	ret = meson_gpio_irq_request_channel(ctl, hwirq, &channel_hwirq);
397 	if (ret)
398 		return ret;
399 
400 	ret = meson_gpio_irq_allocate_gic_irq(domain, virq,
401 					      *channel_hwirq, type);
402 	if (ret < 0) {
403 		pr_err("failed to allocate gic irq %u\n", *channel_hwirq);
404 		meson_gpio_irq_release_channel(ctl, channel_hwirq);
405 		return ret;
406 	}
407 
408 	irq_domain_set_hwirq_and_chip(domain, virq, hwirq,
409 				      &meson_gpio_irq_chip, channel_hwirq);
410 
411 	return 0;
412 }
413 
414 static void meson_gpio_irq_domain_free(struct irq_domain *domain,
415 				       unsigned int virq,
416 				       unsigned int nr_irqs)
417 {
418 	struct meson_gpio_irq_controller *ctl = domain->host_data;
419 	struct irq_data *irq_data;
420 	u32 *channel_hwirq;
421 
422 	if (WARN_ON(nr_irqs != 1))
423 		return;
424 
425 	irq_domain_free_irqs_parent(domain, virq, 1);
426 
427 	irq_data = irq_domain_get_irq_data(domain, virq);
428 	channel_hwirq = irq_data_get_irq_chip_data(irq_data);
429 
430 	meson_gpio_irq_release_channel(ctl, channel_hwirq);
431 }
432 
433 static const struct irq_domain_ops meson_gpio_irq_domain_ops = {
434 	.alloc		= meson_gpio_irq_domain_alloc,
435 	.free		= meson_gpio_irq_domain_free,
436 	.translate	= meson_gpio_irq_domain_translate,
437 };
438 
439 static int __init meson_gpio_irq_parse_dt(struct device_node *node,
440 					  struct meson_gpio_irq_controller *ctl)
441 {
442 	const struct of_device_id *match;
443 	int ret;
444 
445 	match = of_match_node(meson_irq_gpio_matches, node);
446 	if (!match)
447 		return -ENODEV;
448 
449 	ctl->params = match->data;
450 
451 	ret = of_property_read_variable_u32_array(node,
452 						  "amlogic,channel-interrupts",
453 						  ctl->channel_irqs,
454 						  NUM_CHANNEL,
455 						  NUM_CHANNEL);
456 	if (ret < 0) {
457 		pr_err("can't get %d channel interrupts\n", NUM_CHANNEL);
458 		return ret;
459 	}
460 
461 	ctl->params->ops.gpio_irq_init(ctl);
462 
463 	return 0;
464 }
465 
466 static int __init meson_gpio_irq_of_init(struct device_node *node,
467 					 struct device_node *parent)
468 {
469 	struct irq_domain *domain, *parent_domain;
470 	struct meson_gpio_irq_controller *ctl;
471 	int ret;
472 
473 	if (!parent) {
474 		pr_err("missing parent interrupt node\n");
475 		return -ENODEV;
476 	}
477 
478 	parent_domain = irq_find_host(parent);
479 	if (!parent_domain) {
480 		pr_err("unable to obtain parent domain\n");
481 		return -ENXIO;
482 	}
483 
484 	ctl = kzalloc(sizeof(*ctl), GFP_KERNEL);
485 	if (!ctl)
486 		return -ENOMEM;
487 
488 	spin_lock_init(&ctl->lock);
489 
490 	ctl->base = of_iomap(node, 0);
491 	if (!ctl->base) {
492 		ret = -ENOMEM;
493 		goto free_ctl;
494 	}
495 
496 	ret = meson_gpio_irq_parse_dt(node, ctl);
497 	if (ret)
498 		goto free_channel_irqs;
499 
500 	domain = irq_domain_create_hierarchy(parent_domain, 0,
501 					     ctl->params->nr_hwirq,
502 					     of_node_to_fwnode(node),
503 					     &meson_gpio_irq_domain_ops,
504 					     ctl);
505 	if (!domain) {
506 		pr_err("failed to add domain\n");
507 		ret = -ENODEV;
508 		goto free_channel_irqs;
509 	}
510 
511 	pr_info("%d to %d gpio interrupt mux initialized\n",
512 		ctl->params->nr_hwirq, NUM_CHANNEL);
513 
514 	return 0;
515 
516 free_channel_irqs:
517 	iounmap(ctl->base);
518 free_ctl:
519 	kfree(ctl);
520 
521 	return ret;
522 }
523 
524 IRQCHIP_DECLARE(meson_gpio_intc, "amlogic,meson-gpio-intc",
525 		meson_gpio_irq_of_init);
526