xref: /openbmc/linux/drivers/irqchip/irq-mbigen.c (revision 80d0624d) 
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2015 HiSilicon Limited, All Rights Reserved.
4  * Author: Jun Ma <majun258@huawei.com>
5  * Author: Yun Wu <wuyun.wu@huawei.com>
6  */
7 
8 #include <linux/acpi.h>
9 #include <linux/interrupt.h>
10 #include <linux/irqchip.h>
11 #include <linux/module.h>
12 #include <linux/msi.h>
13 #include <linux/of_address.h>
14 #include <linux/of_irq.h>
15 #include <linux/of_platform.h>
16 #include <linux/platform_device.h>
17 #include <linux/slab.h>
18 
19 /* Interrupt numbers per mbigen node supported */
20 #define IRQS_PER_MBIGEN_NODE		128
21 
22 /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */
23 #define RESERVED_IRQ_PER_MBIGEN_CHIP	64
24 
25 /* The maximum IRQ pin number of mbigen chip(start from 0) */
26 #define MAXIMUM_IRQ_PIN_NUM		1407
27 
28 /*
29  * In mbigen vector register
30  * bit[21:12]:	event id value
31  * bit[11:0]:	device id
32  */
33 #define IRQ_EVENT_ID_SHIFT		12
34 #define IRQ_EVENT_ID_MASK		0x3ff
35 
36 /* register range of each mbigen node */
37 #define MBIGEN_NODE_OFFSET		0x1000
38 
39 /* offset of vector register in mbigen node */
40 #define REG_MBIGEN_VEC_OFFSET		0x200
41 
42 /*
43  * offset of clear register in mbigen node
44  * This register is used to clear the status
45  * of interrupt
46  */
47 #define REG_MBIGEN_CLEAR_OFFSET		0xa000
48 
49 /*
50  * offset of interrupt type register
51  * This register is used to configure interrupt
52  * trigger type
53  */
54 #define REG_MBIGEN_TYPE_OFFSET		0x0
55 
56 /**
57  * struct mbigen_device - holds the information of mbigen device.
58  *
59  * @pdev:		pointer to the platform device structure of mbigen chip.
60  * @base:		mapped address of this mbigen chip.
61  */
62 struct mbigen_device {
63 	struct platform_device	*pdev;
64 	void __iomem		*base;
65 };
66 
67 static inline unsigned int get_mbigen_node_offset(unsigned int nid)
68 {
69 	unsigned int offset = nid * MBIGEN_NODE_OFFSET;
70 
71 	/*
72 	 * To avoid touched clear register in unexpected way, we need to directly
73 	 * skip clear register when access to more than 10 mbigen nodes.
74 	 */
75 	if (nid >= (REG_MBIGEN_CLEAR_OFFSET / MBIGEN_NODE_OFFSET))
76 		offset += MBIGEN_NODE_OFFSET;
77 
78 	return offset;
79 }
80 
81 static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq)
82 {
83 	unsigned int nid, pin;
84 
85 	hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
86 	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
87 	pin = hwirq % IRQS_PER_MBIGEN_NODE;
88 
89 	return pin * 4 + get_mbigen_node_offset(nid) + REG_MBIGEN_VEC_OFFSET;
90 }
91 
92 static inline void get_mbigen_type_reg(irq_hw_number_t hwirq,
93 					u32 *mask, u32 *addr)
94 {
95 	unsigned int nid, irq_ofst, ofst;
96 
97 	hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP;
98 	nid = hwirq / IRQS_PER_MBIGEN_NODE + 1;
99 	irq_ofst = hwirq % IRQS_PER_MBIGEN_NODE;
100 
101 	*mask = 1 << (irq_ofst % 32);
102 	ofst = irq_ofst / 32 * 4;
103 
104 	*addr = ofst + get_mbigen_node_offset(nid) + REG_MBIGEN_TYPE_OFFSET;
105 }
106 
107 static inline void get_mbigen_clear_reg(irq_hw_number_t hwirq,
108 					u32 *mask, u32 *addr)
109 {
110 	unsigned int ofst = (hwirq / 32) * 4;
111 
112 	*mask = 1 << (hwirq % 32);
113 	*addr = ofst + REG_MBIGEN_CLEAR_OFFSET;
114 }
115 
116 static void mbigen_eoi_irq(struct irq_data *data)
117 {
118 	void __iomem *base = data->chip_data;
119 	u32 mask, addr;
120 
121 	get_mbigen_clear_reg(data->hwirq, &mask, &addr);
122 
123 	writel_relaxed(mask, base + addr);
124 
125 	irq_chip_eoi_parent(data);
126 }
127 
128 static int mbigen_set_type(struct irq_data *data, unsigned int type)
129 {
130 	void __iomem *base = data->chip_data;
131 	u32 mask, addr, val;
132 
133 	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
134 		return -EINVAL;
135 
136 	get_mbigen_type_reg(data->hwirq, &mask, &addr);
137 
138 	val = readl_relaxed(base + addr);
139 
140 	if (type == IRQ_TYPE_LEVEL_HIGH)
141 		val |= mask;
142 	else
143 		val &= ~mask;
144 
145 	writel_relaxed(val, base + addr);
146 
147 	return 0;
148 }
149 
150 static struct irq_chip mbigen_irq_chip = {
151 	.name =			"mbigen-v2",
152 	.irq_mask =		irq_chip_mask_parent,
153 	.irq_unmask =		irq_chip_unmask_parent,
154 	.irq_eoi =		mbigen_eoi_irq,
155 	.irq_set_type =		mbigen_set_type,
156 	.irq_set_affinity =	irq_chip_set_affinity_parent,
157 };
158 
159 static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg)
160 {
161 	struct irq_data *d = irq_get_irq_data(desc->irq);
162 	void __iomem *base = d->chip_data;
163 	u32 val;
164 
165 	if (!msg->address_lo && !msg->address_hi)
166 		return;
167 
168 	base += get_mbigen_vec_reg(d->hwirq);
169 	val = readl_relaxed(base);
170 
171 	val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT);
172 	val |= (msg->data << IRQ_EVENT_ID_SHIFT);
173 
174 	/* The address of doorbell is encoded in mbigen register by default
175 	 * So,we don't need to program the doorbell address at here
176 	 */
177 	writel_relaxed(val, base);
178 }
179 
180 static int mbigen_domain_translate(struct irq_domain *d,
181 				    struct irq_fwspec *fwspec,
182 				    unsigned long *hwirq,
183 				    unsigned int *type)
184 {
185 	if (is_of_node(fwspec->fwnode) || is_acpi_device_node(fwspec->fwnode)) {
186 		if (fwspec->param_count != 2)
187 			return -EINVAL;
188 
189 		if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) ||
190 			(fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP))
191 			return -EINVAL;
192 		else
193 			*hwirq = fwspec->param[0];
194 
195 		/* If there is no valid irq type, just use the default type */
196 		if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) ||
197 			(fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH))
198 			*type = fwspec->param[1];
199 		else
200 			return -EINVAL;
201 
202 		return 0;
203 	}
204 	return -EINVAL;
205 }
206 
207 static int mbigen_irq_domain_alloc(struct irq_domain *domain,
208 					unsigned int virq,
209 					unsigned int nr_irqs,
210 					void *args)
211 {
212 	struct irq_fwspec *fwspec = args;
213 	irq_hw_number_t hwirq;
214 	unsigned int type;
215 	struct mbigen_device *mgn_chip;
216 	int i, err;
217 
218 	err = mbigen_domain_translate(domain, fwspec, &hwirq, &type);
219 	if (err)
220 		return err;
221 
222 	err = platform_msi_device_domain_alloc(domain, virq, nr_irqs);
223 	if (err)
224 		return err;
225 
226 	mgn_chip = platform_msi_get_host_data(domain);
227 
228 	for (i = 0; i < nr_irqs; i++)
229 		irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i,
230 				      &mbigen_irq_chip, mgn_chip->base);
231 
232 	return 0;
233 }
234 
235 static void mbigen_irq_domain_free(struct irq_domain *domain, unsigned int virq,
236 				   unsigned int nr_irqs)
237 {
238 	platform_msi_device_domain_free(domain, virq, nr_irqs);
239 }
240 
241 static const struct irq_domain_ops mbigen_domain_ops = {
242 	.translate	= mbigen_domain_translate,
243 	.alloc		= mbigen_irq_domain_alloc,
244 	.free		= mbigen_irq_domain_free,
245 };
246 
247 static int mbigen_of_create_domain(struct platform_device *pdev,
248 				   struct mbigen_device *mgn_chip)
249 {
250 	struct platform_device *child;
251 	struct irq_domain *domain;
252 	struct device_node *np;
253 	u32 num_pins;
254 	int ret = 0;
255 
256 	for_each_child_of_node(pdev->dev.of_node, np) {
257 		if (!of_property_read_bool(np, "interrupt-controller"))
258 			continue;
259 
260 		child = of_platform_device_create(np, NULL, NULL);
261 		if (!child) {
262 			ret = -ENOMEM;
263 			break;
264 		}
265 
266 		if (of_property_read_u32(child->dev.of_node, "num-pins",
267 					 &num_pins) < 0) {
268 			dev_err(&pdev->dev, "No num-pins property\n");
269 			ret = -EINVAL;
270 			break;
271 		}
272 
273 		domain = platform_msi_create_device_domain(&child->dev, num_pins,
274 							   mbigen_write_msg,
275 							   &mbigen_domain_ops,
276 							   mgn_chip);
277 		if (!domain) {
278 			ret = -ENOMEM;
279 			break;
280 		}
281 	}
282 
283 	if (ret)
284 		of_node_put(np);
285 
286 	return ret;
287 }
288 
289 #ifdef CONFIG_ACPI
290 static const struct acpi_device_id mbigen_acpi_match[] = {
291 	{ "HISI0152", 0 },
292 	{}
293 };
294 MODULE_DEVICE_TABLE(acpi, mbigen_acpi_match);
295 
296 static int mbigen_acpi_create_domain(struct platform_device *pdev,
297 				     struct mbigen_device *mgn_chip)
298 {
299 	struct irq_domain *domain;
300 	u32 num_pins = 0;
301 	int ret;
302 
303 	/*
304 	 * "num-pins" is the total number of interrupt pins implemented in
305 	 * this mbigen instance, and mbigen is an interrupt controller
306 	 * connected to ITS  converting wired interrupts into MSI, so we
307 	 * use "num-pins" to alloc MSI vectors which are needed by client
308 	 * devices connected to it.
309 	 *
310 	 * Here is the DSDT device node used for mbigen in firmware:
311 	 *	Device(MBI0) {
312 	 *		Name(_HID, "HISI0152")
313 	 *		Name(_UID, Zero)
314 	 *		Name(_CRS, ResourceTemplate() {
315 	 *			Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
316 	 *		})
317 	 *
318 	 *		Name(_DSD, Package () {
319 	 *			ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
320 	 *			Package () {
321 	 *				Package () {"num-pins", 378}
322 	 *			}
323 	 *		})
324 	 *	}
325 	 */
326 	ret = device_property_read_u32(&pdev->dev, "num-pins", &num_pins);
327 	if (ret || num_pins == 0)
328 		return -EINVAL;
329 
330 	domain = platform_msi_create_device_domain(&pdev->dev, num_pins,
331 						   mbigen_write_msg,
332 						   &mbigen_domain_ops,
333 						   mgn_chip);
334 	if (!domain)
335 		return -ENOMEM;
336 
337 	return 0;
338 }
339 #else
340 static inline int mbigen_acpi_create_domain(struct platform_device *pdev,
341 					    struct mbigen_device *mgn_chip)
342 {
343 	return -ENODEV;
344 }
345 #endif
346 
347 static int mbigen_device_probe(struct platform_device *pdev)
348 {
349 	struct mbigen_device *mgn_chip;
350 	struct resource *res;
351 	int err;
352 
353 	mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL);
354 	if (!mgn_chip)
355 		return -ENOMEM;
356 
357 	mgn_chip->pdev = pdev;
358 
359 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
360 	if (!res)
361 		return -EINVAL;
362 
363 	mgn_chip->base = devm_ioremap(&pdev->dev, res->start,
364 				      resource_size(res));
365 	if (!mgn_chip->base) {
366 		dev_err(&pdev->dev, "failed to ioremap %pR\n", res);
367 		return -ENOMEM;
368 	}
369 
370 	if (IS_ENABLED(CONFIG_OF) && pdev->dev.of_node)
371 		err = mbigen_of_create_domain(pdev, mgn_chip);
372 	else if (ACPI_COMPANION(&pdev->dev))
373 		err = mbigen_acpi_create_domain(pdev, mgn_chip);
374 	else
375 		err = -EINVAL;
376 
377 	if (err) {
378 		dev_err(&pdev->dev, "Failed to create mbi-gen irqdomain\n");
379 		return err;
380 	}
381 
382 	platform_set_drvdata(pdev, mgn_chip);
383 	return 0;
384 }
385 
386 static const struct of_device_id mbigen_of_match[] = {
387 	{ .compatible = "hisilicon,mbigen-v2" },
388 	{ /* END */ }
389 };
390 MODULE_DEVICE_TABLE(of, mbigen_of_match);
391 
392 static struct platform_driver mbigen_platform_driver = {
393 	.driver = {
394 		.name		= "Hisilicon MBIGEN-V2",
395 		.of_match_table	= mbigen_of_match,
396 		.acpi_match_table = ACPI_PTR(mbigen_acpi_match),
397 		.suppress_bind_attrs = true,
398 	},
399 	.probe			= mbigen_device_probe,
400 };
401 
402 module_platform_driver(mbigen_platform_driver);
403 
404 MODULE_AUTHOR("Jun Ma <majun258@huawei.com>");
405 MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>");
406 MODULE_DESCRIPTION("HiSilicon MBI Generator driver");
407