1717c3dbcSMa Jun /* 2717c3dbcSMa Jun * Copyright (C) 2015 Hisilicon Limited, All Rights Reserved. 3717c3dbcSMa Jun * Author: Jun Ma <majun258@huawei.com> 4717c3dbcSMa Jun * Author: Yun Wu <wuyun.wu@huawei.com> 5717c3dbcSMa Jun * 6717c3dbcSMa Jun * This program is free software; you can redistribute it and/or modify 7717c3dbcSMa Jun * it under the terms of the GNU General Public License version 2 as 8717c3dbcSMa Jun * published by the Free Software Foundation. 9717c3dbcSMa Jun * 10717c3dbcSMa Jun * This program is distributed in the hope that it will be useful, 11717c3dbcSMa Jun * but WITHOUT ANY WARRANTY; without even the implied warranty of 12717c3dbcSMa Jun * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13717c3dbcSMa Jun * GNU General Public License for more details. 14717c3dbcSMa Jun * 15717c3dbcSMa Jun * You should have received a copy of the GNU General Public License 16717c3dbcSMa Jun * along with this program. If not, see <http://www.gnu.org/licenses/>. 17717c3dbcSMa Jun */ 18717c3dbcSMa Jun 199650c60eSMa Jun #include <linux/interrupt.h> 209650c60eSMa Jun #include <linux/irqchip.h> 21717c3dbcSMa Jun #include <linux/module.h> 229650c60eSMa Jun #include <linux/msi.h> 23717c3dbcSMa Jun #include <linux/of_address.h> 24717c3dbcSMa Jun #include <linux/of_irq.h> 25717c3dbcSMa Jun #include <linux/of_platform.h> 26717c3dbcSMa Jun #include <linux/platform_device.h> 27717c3dbcSMa Jun #include <linux/slab.h> 28717c3dbcSMa Jun 299650c60eSMa Jun /* Interrupt numbers per mbigen node supported */ 309650c60eSMa Jun #define IRQS_PER_MBIGEN_NODE 128 319650c60eSMa Jun 329650c60eSMa Jun /* 64 irqs (Pin0-pin63) are reserved for each mbigen chip */ 339650c60eSMa Jun #define RESERVED_IRQ_PER_MBIGEN_CHIP 64 349650c60eSMa Jun 359650c60eSMa Jun /* The maximum IRQ pin number of mbigen chip(start from 0) */ 369650c60eSMa Jun #define MAXIMUM_IRQ_PIN_NUM 1407 379650c60eSMa Jun 389650c60eSMa Jun /** 399650c60eSMa Jun * In mbigen vector register 409650c60eSMa Jun * bit[21:12]: event id value 419650c60eSMa Jun * bit[11:0]: device id 429650c60eSMa Jun */ 439650c60eSMa Jun #define IRQ_EVENT_ID_SHIFT 12 449650c60eSMa Jun #define IRQ_EVENT_ID_MASK 0x3ff 459650c60eSMa Jun 469650c60eSMa Jun /* register range of each mbigen node */ 479650c60eSMa Jun #define MBIGEN_NODE_OFFSET 0x1000 489650c60eSMa Jun 499650c60eSMa Jun /* offset of vector register in mbigen node */ 509650c60eSMa Jun #define REG_MBIGEN_VEC_OFFSET 0x200 519650c60eSMa Jun 52717c3dbcSMa Jun /** 53717c3dbcSMa Jun * struct mbigen_device - holds the information of mbigen device. 54717c3dbcSMa Jun * 55717c3dbcSMa Jun * @pdev: pointer to the platform device structure of mbigen chip. 56717c3dbcSMa Jun * @base: mapped address of this mbigen chip. 57717c3dbcSMa Jun */ 58717c3dbcSMa Jun struct mbigen_device { 59717c3dbcSMa Jun struct platform_device *pdev; 60717c3dbcSMa Jun void __iomem *base; 61717c3dbcSMa Jun }; 62717c3dbcSMa Jun 639650c60eSMa Jun static inline unsigned int get_mbigen_vec_reg(irq_hw_number_t hwirq) 649650c60eSMa Jun { 659650c60eSMa Jun unsigned int nid, pin; 669650c60eSMa Jun 679650c60eSMa Jun hwirq -= RESERVED_IRQ_PER_MBIGEN_CHIP; 689650c60eSMa Jun nid = hwirq / IRQS_PER_MBIGEN_NODE + 1; 699650c60eSMa Jun pin = hwirq % IRQS_PER_MBIGEN_NODE; 709650c60eSMa Jun 719650c60eSMa Jun return pin * 4 + nid * MBIGEN_NODE_OFFSET 729650c60eSMa Jun + REG_MBIGEN_VEC_OFFSET; 739650c60eSMa Jun } 749650c60eSMa Jun 759650c60eSMa Jun static struct irq_chip mbigen_irq_chip = { 769650c60eSMa Jun .name = "mbigen-v2", 779650c60eSMa Jun }; 789650c60eSMa Jun 799650c60eSMa Jun static void mbigen_write_msg(struct msi_desc *desc, struct msi_msg *msg) 809650c60eSMa Jun { 819650c60eSMa Jun struct irq_data *d = irq_get_irq_data(desc->irq); 829650c60eSMa Jun void __iomem *base = d->chip_data; 839650c60eSMa Jun u32 val; 849650c60eSMa Jun 859650c60eSMa Jun base += get_mbigen_vec_reg(d->hwirq); 869650c60eSMa Jun val = readl_relaxed(base); 879650c60eSMa Jun 889650c60eSMa Jun val &= ~(IRQ_EVENT_ID_MASK << IRQ_EVENT_ID_SHIFT); 899650c60eSMa Jun val |= (msg->data << IRQ_EVENT_ID_SHIFT); 909650c60eSMa Jun 919650c60eSMa Jun /* The address of doorbell is encoded in mbigen register by default 929650c60eSMa Jun * So,we don't need to program the doorbell address at here 939650c60eSMa Jun */ 949650c60eSMa Jun writel_relaxed(val, base); 959650c60eSMa Jun } 969650c60eSMa Jun 979650c60eSMa Jun static int mbigen_domain_translate(struct irq_domain *d, 989650c60eSMa Jun struct irq_fwspec *fwspec, 999650c60eSMa Jun unsigned long *hwirq, 1009650c60eSMa Jun unsigned int *type) 1019650c60eSMa Jun { 1029650c60eSMa Jun if (is_of_node(fwspec->fwnode)) { 1039650c60eSMa Jun if (fwspec->param_count != 2) 1049650c60eSMa Jun return -EINVAL; 1059650c60eSMa Jun 1069650c60eSMa Jun if ((fwspec->param[0] > MAXIMUM_IRQ_PIN_NUM) || 1079650c60eSMa Jun (fwspec->param[0] < RESERVED_IRQ_PER_MBIGEN_CHIP)) 1089650c60eSMa Jun return -EINVAL; 1099650c60eSMa Jun else 1109650c60eSMa Jun *hwirq = fwspec->param[0]; 1119650c60eSMa Jun 1129650c60eSMa Jun /* If there is no valid irq type, just use the default type */ 1139650c60eSMa Jun if ((fwspec->param[1] == IRQ_TYPE_EDGE_RISING) || 1149650c60eSMa Jun (fwspec->param[1] == IRQ_TYPE_LEVEL_HIGH)) 1159650c60eSMa Jun *type = fwspec->param[1]; 1169650c60eSMa Jun else 1179650c60eSMa Jun return -EINVAL; 1189650c60eSMa Jun 1199650c60eSMa Jun return 0; 1209650c60eSMa Jun } 1219650c60eSMa Jun return -EINVAL; 1229650c60eSMa Jun } 1239650c60eSMa Jun 1249650c60eSMa Jun static int mbigen_irq_domain_alloc(struct irq_domain *domain, 1259650c60eSMa Jun unsigned int virq, 1269650c60eSMa Jun unsigned int nr_irqs, 1279650c60eSMa Jun void *args) 1289650c60eSMa Jun { 1299650c60eSMa Jun struct irq_fwspec *fwspec = args; 1309650c60eSMa Jun irq_hw_number_t hwirq; 1319650c60eSMa Jun unsigned int type; 1329650c60eSMa Jun struct mbigen_device *mgn_chip; 1339650c60eSMa Jun int i, err; 1349650c60eSMa Jun 1359650c60eSMa Jun err = mbigen_domain_translate(domain, fwspec, &hwirq, &type); 1369650c60eSMa Jun if (err) 1379650c60eSMa Jun return err; 1389650c60eSMa Jun 1399650c60eSMa Jun err = platform_msi_domain_alloc(domain, virq, nr_irqs); 1409650c60eSMa Jun if (err) 1419650c60eSMa Jun return err; 1429650c60eSMa Jun 1439650c60eSMa Jun mgn_chip = platform_msi_get_host_data(domain); 1449650c60eSMa Jun 1459650c60eSMa Jun for (i = 0; i < nr_irqs; i++) 1469650c60eSMa Jun irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, 1479650c60eSMa Jun &mbigen_irq_chip, mgn_chip->base); 1489650c60eSMa Jun 1499650c60eSMa Jun return 0; 1509650c60eSMa Jun } 1519650c60eSMa Jun 1529650c60eSMa Jun static struct irq_domain_ops mbigen_domain_ops = { 1539650c60eSMa Jun .translate = mbigen_domain_translate, 1549650c60eSMa Jun .alloc = mbigen_irq_domain_alloc, 1559650c60eSMa Jun .free = irq_domain_free_irqs_common, 1569650c60eSMa Jun }; 1579650c60eSMa Jun 158717c3dbcSMa Jun static int mbigen_device_probe(struct platform_device *pdev) 159717c3dbcSMa Jun { 160717c3dbcSMa Jun struct mbigen_device *mgn_chip; 161717c3dbcSMa Jun struct resource *res; 1629650c60eSMa Jun struct irq_domain *domain; 1639650c60eSMa Jun u32 num_pins; 164717c3dbcSMa Jun 165717c3dbcSMa Jun mgn_chip = devm_kzalloc(&pdev->dev, sizeof(*mgn_chip), GFP_KERNEL); 166717c3dbcSMa Jun if (!mgn_chip) 167717c3dbcSMa Jun return -ENOMEM; 168717c3dbcSMa Jun 169717c3dbcSMa Jun mgn_chip->pdev = pdev; 170717c3dbcSMa Jun 171717c3dbcSMa Jun res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 172717c3dbcSMa Jun mgn_chip->base = devm_ioremap_resource(&pdev->dev, res); 173717c3dbcSMa Jun if (IS_ERR(mgn_chip->base)) 174717c3dbcSMa Jun return PTR_ERR(mgn_chip->base); 175717c3dbcSMa Jun 1769650c60eSMa Jun if (of_property_read_u32(pdev->dev.of_node, "num-pins", &num_pins) < 0) { 1779650c60eSMa Jun dev_err(&pdev->dev, "No num-pins property\n"); 1789650c60eSMa Jun return -EINVAL; 1799650c60eSMa Jun } 1809650c60eSMa Jun 1819650c60eSMa Jun domain = platform_msi_create_device_domain(&pdev->dev, num_pins, 1829650c60eSMa Jun mbigen_write_msg, 1839650c60eSMa Jun &mbigen_domain_ops, 1849650c60eSMa Jun mgn_chip); 1859650c60eSMa Jun 1869650c60eSMa Jun if (!domain) 1879650c60eSMa Jun return -ENOMEM; 1889650c60eSMa Jun 189717c3dbcSMa Jun platform_set_drvdata(pdev, mgn_chip); 190717c3dbcSMa Jun 1919650c60eSMa Jun dev_info(&pdev->dev, "Allocated %d MSIs\n", num_pins); 1929650c60eSMa Jun 193717c3dbcSMa Jun return 0; 194717c3dbcSMa Jun } 195717c3dbcSMa Jun 196717c3dbcSMa Jun static const struct of_device_id mbigen_of_match[] = { 197717c3dbcSMa Jun { .compatible = "hisilicon,mbigen-v2" }, 198717c3dbcSMa Jun { /* END */ } 199717c3dbcSMa Jun }; 200717c3dbcSMa Jun MODULE_DEVICE_TABLE(of, mbigen_of_match); 201717c3dbcSMa Jun 202717c3dbcSMa Jun static struct platform_driver mbigen_platform_driver = { 203717c3dbcSMa Jun .driver = { 204717c3dbcSMa Jun .name = "Hisilicon MBIGEN-V2", 205717c3dbcSMa Jun .owner = THIS_MODULE, 206717c3dbcSMa Jun .of_match_table = mbigen_of_match, 207717c3dbcSMa Jun }, 208717c3dbcSMa Jun .probe = mbigen_device_probe, 209717c3dbcSMa Jun }; 210717c3dbcSMa Jun 211717c3dbcSMa Jun module_platform_driver(mbigen_platform_driver); 212717c3dbcSMa Jun 213717c3dbcSMa Jun MODULE_AUTHOR("Jun Ma <majun258@huawei.com>"); 214717c3dbcSMa Jun MODULE_AUTHOR("Yun Wu <wuyun.wu@huawei.com>"); 215717c3dbcSMa Jun MODULE_LICENSE("GPL"); 216717c3dbcSMa Jun MODULE_DESCRIPTION("Hisilicon MBI Generator driver"); 217