1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Loongson Extend I/O Interrupt Controller support 4 * 5 * Copyright (C) 2020-2022 Loongson Technology Corporation Limited 6 */ 7 8 #define pr_fmt(fmt) "eiointc: " fmt 9 10 #include <linux/interrupt.h> 11 #include <linux/irq.h> 12 #include <linux/irqchip.h> 13 #include <linux/irqdomain.h> 14 #include <linux/irqchip/chained_irq.h> 15 #include <linux/kernel.h> 16 #include <linux/platform_device.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/of_platform.h> 20 21 #define EIOINTC_REG_NODEMAP 0x14a0 22 #define EIOINTC_REG_IPMAP 0x14c0 23 #define EIOINTC_REG_ENABLE 0x1600 24 #define EIOINTC_REG_BOUNCE 0x1680 25 #define EIOINTC_REG_ISR 0x1800 26 #define EIOINTC_REG_ROUTE 0x1c00 27 28 #define VEC_REG_COUNT 4 29 #define VEC_COUNT_PER_REG 64 30 #define VEC_COUNT (VEC_REG_COUNT * VEC_COUNT_PER_REG) 31 #define VEC_REG_IDX(irq_id) ((irq_id) / VEC_COUNT_PER_REG) 32 #define VEC_REG_BIT(irq_id) ((irq_id) % VEC_COUNT_PER_REG) 33 #define EIOINTC_ALL_ENABLE 0xffffffff 34 35 #define MAX_EIO_NODES (NR_CPUS / CORES_PER_EIO_NODE) 36 37 static int nr_pics; 38 39 struct eiointc_priv { 40 u32 node; 41 nodemask_t node_map; 42 cpumask_t cpuspan_map; 43 struct fwnode_handle *domain_handle; 44 struct irq_domain *eiointc_domain; 45 }; 46 47 static struct eiointc_priv *eiointc_priv[MAX_IO_PICS]; 48 49 static void eiointc_enable(void) 50 { 51 uint64_t misc; 52 53 misc = iocsr_read64(LOONGARCH_IOCSR_MISC_FUNC); 54 misc |= IOCSR_MISC_FUNC_EXT_IOI_EN; 55 iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC); 56 } 57 58 static int cpu_to_eio_node(int cpu) 59 { 60 return cpu_logical_map(cpu) / CORES_PER_EIO_NODE; 61 } 62 63 static void eiointc_set_irq_route(int pos, unsigned int cpu, unsigned int mnode, nodemask_t *node_map) 64 { 65 int i, node, cpu_node, route_node; 66 unsigned char coremap; 67 uint32_t pos_off, data, data_byte, data_mask; 68 69 pos_off = pos & ~3; 70 data_byte = pos & 3; 71 data_mask = ~BIT_MASK(data_byte) & 0xf; 72 73 /* Calculate node and coremap of target irq */ 74 cpu_node = cpu_logical_map(cpu) / CORES_PER_EIO_NODE; 75 coremap = BIT(cpu_logical_map(cpu) % CORES_PER_EIO_NODE); 76 77 for_each_online_cpu(i) { 78 node = cpu_to_eio_node(i); 79 if (!node_isset(node, *node_map)) 80 continue; 81 82 /* EIO node 0 is in charge of inter-node interrupt dispatch */ 83 route_node = (node == mnode) ? cpu_node : node; 84 data = ((coremap | (route_node << 4)) << (data_byte * 8)); 85 csr_any_send(EIOINTC_REG_ROUTE + pos_off, data, data_mask, node * CORES_PER_EIO_NODE); 86 } 87 } 88 89 static DEFINE_RAW_SPINLOCK(affinity_lock); 90 91 static int eiointc_set_irq_affinity(struct irq_data *d, const struct cpumask *affinity, bool force) 92 { 93 unsigned int cpu; 94 unsigned long flags; 95 uint32_t vector, regaddr; 96 struct cpumask intersect_affinity; 97 struct eiointc_priv *priv = d->domain->host_data; 98 99 raw_spin_lock_irqsave(&affinity_lock, flags); 100 101 cpumask_and(&intersect_affinity, affinity, cpu_online_mask); 102 cpumask_and(&intersect_affinity, &intersect_affinity, &priv->cpuspan_map); 103 104 if (cpumask_empty(&intersect_affinity)) { 105 raw_spin_unlock_irqrestore(&affinity_lock, flags); 106 return -EINVAL; 107 } 108 cpu = cpumask_first(&intersect_affinity); 109 110 vector = d->hwirq; 111 regaddr = EIOINTC_REG_ENABLE + ((vector >> 5) << 2); 112 113 /* Mask target vector */ 114 csr_any_send(regaddr, EIOINTC_ALL_ENABLE & (~BIT(vector & 0x1F)), 0x0, 0); 115 /* Set route for target vector */ 116 eiointc_set_irq_route(vector, cpu, priv->node, &priv->node_map); 117 /* Unmask target vector */ 118 csr_any_send(regaddr, EIOINTC_ALL_ENABLE, 0x0, 0); 119 120 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 121 122 raw_spin_unlock_irqrestore(&affinity_lock, flags); 123 124 return IRQ_SET_MASK_OK; 125 } 126 127 static int eiointc_index(int node) 128 { 129 int i; 130 131 for (i = 0; i < nr_pics; i++) { 132 if (node_isset(node, eiointc_priv[i]->node_map)) 133 return i; 134 } 135 136 return -1; 137 } 138 139 static int eiointc_router_init(unsigned int cpu) 140 { 141 int i, bit; 142 uint32_t data; 143 uint32_t node = cpu_to_eio_node(cpu); 144 uint32_t index = eiointc_index(node); 145 146 if (index < 0) { 147 pr_err("Error: invalid nodemap!\n"); 148 return -1; 149 } 150 151 if ((cpu_logical_map(cpu) % CORES_PER_EIO_NODE) == 0) { 152 eiointc_enable(); 153 154 for (i = 0; i < VEC_COUNT / 32; i++) { 155 data = (((1 << (i * 2 + 1)) << 16) | (1 << (i * 2))); 156 iocsr_write32(data, EIOINTC_REG_NODEMAP + i * 4); 157 } 158 159 for (i = 0; i < VEC_COUNT / 32 / 4; i++) { 160 bit = BIT(1 + index); /* Route to IP[1 + index] */ 161 data = bit | (bit << 8) | (bit << 16) | (bit << 24); 162 iocsr_write32(data, EIOINTC_REG_IPMAP + i * 4); 163 } 164 165 for (i = 0; i < VEC_COUNT / 4; i++) { 166 /* Route to Node-0 Core-0 */ 167 if (index == 0) 168 bit = BIT(cpu_logical_map(0)); 169 else 170 bit = (eiointc_priv[index]->node << 4) | 1; 171 172 data = bit | (bit << 8) | (bit << 16) | (bit << 24); 173 iocsr_write32(data, EIOINTC_REG_ROUTE + i * 4); 174 } 175 176 for (i = 0; i < VEC_COUNT / 32; i++) { 177 data = 0xffffffff; 178 iocsr_write32(data, EIOINTC_REG_ENABLE + i * 4); 179 iocsr_write32(data, EIOINTC_REG_BOUNCE + i * 4); 180 } 181 } 182 183 return 0; 184 } 185 186 static void eiointc_irq_dispatch(struct irq_desc *desc) 187 { 188 int i; 189 u64 pending; 190 bool handled = false; 191 struct irq_chip *chip = irq_desc_get_chip(desc); 192 struct eiointc_priv *priv = irq_desc_get_handler_data(desc); 193 194 chained_irq_enter(chip, desc); 195 196 for (i = 0; i < VEC_REG_COUNT; i++) { 197 pending = iocsr_read64(EIOINTC_REG_ISR + (i << 3)); 198 iocsr_write64(pending, EIOINTC_REG_ISR + (i << 3)); 199 while (pending) { 200 int bit = __ffs(pending); 201 int irq = bit + VEC_COUNT_PER_REG * i; 202 203 generic_handle_domain_irq(priv->eiointc_domain, irq); 204 pending &= ~BIT(bit); 205 handled = true; 206 } 207 } 208 209 if (!handled) 210 spurious_interrupt(); 211 212 chained_irq_exit(chip, desc); 213 } 214 215 static void eiointc_ack_irq(struct irq_data *d) 216 { 217 } 218 219 static void eiointc_mask_irq(struct irq_data *d) 220 { 221 } 222 223 static void eiointc_unmask_irq(struct irq_data *d) 224 { 225 } 226 227 static struct irq_chip eiointc_irq_chip = { 228 .name = "EIOINTC", 229 .irq_ack = eiointc_ack_irq, 230 .irq_mask = eiointc_mask_irq, 231 .irq_unmask = eiointc_unmask_irq, 232 .irq_set_affinity = eiointc_set_irq_affinity, 233 }; 234 235 static int eiointc_domain_alloc(struct irq_domain *domain, unsigned int virq, 236 unsigned int nr_irqs, void *arg) 237 { 238 int ret; 239 unsigned int i, type; 240 unsigned long hwirq = 0; 241 struct eiointc *priv = domain->host_data; 242 243 ret = irq_domain_translate_onecell(domain, arg, &hwirq, &type); 244 if (ret) 245 return ret; 246 247 for (i = 0; i < nr_irqs; i++) { 248 irq_domain_set_info(domain, virq + i, hwirq + i, &eiointc_irq_chip, 249 priv, handle_edge_irq, NULL, NULL); 250 } 251 252 return 0; 253 } 254 255 static void eiointc_domain_free(struct irq_domain *domain, unsigned int virq, 256 unsigned int nr_irqs) 257 { 258 int i; 259 260 for (i = 0; i < nr_irqs; i++) { 261 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 262 263 irq_set_handler(virq + i, NULL); 264 irq_domain_reset_irq_data(d); 265 } 266 } 267 268 static const struct irq_domain_ops eiointc_domain_ops = { 269 .translate = irq_domain_translate_onecell, 270 .alloc = eiointc_domain_alloc, 271 .free = eiointc_domain_free, 272 }; 273 274 static void acpi_set_vec_parent(int node, struct irq_domain *parent, struct acpi_vector_group *vec_group) 275 { 276 int i; 277 278 if (cpu_has_flatmode) 279 node = cpu_to_node(node * CORES_PER_EIO_NODE); 280 281 for (i = 0; i < MAX_IO_PICS; i++) { 282 if (node == vec_group[i].node) { 283 vec_group[i].parent = parent; 284 return; 285 } 286 } 287 } 288 289 struct irq_domain *acpi_get_vec_parent(int node, struct acpi_vector_group *vec_group) 290 { 291 int i; 292 293 for (i = 0; i < MAX_IO_PICS; i++) { 294 if (node == vec_group[i].node) 295 return vec_group[i].parent; 296 } 297 return NULL; 298 } 299 300 static int __init 301 pch_pic_parse_madt(union acpi_subtable_headers *header, 302 const unsigned long end) 303 { 304 struct acpi_madt_bio_pic *pchpic_entry = (struct acpi_madt_bio_pic *)header; 305 unsigned int node = (pchpic_entry->address >> 44) & 0xf; 306 struct irq_domain *parent = acpi_get_vec_parent(node, pch_group); 307 308 if (parent) 309 return pch_pic_acpi_init(parent, pchpic_entry); 310 311 return -EINVAL; 312 } 313 314 static int __init 315 pch_msi_parse_madt(union acpi_subtable_headers *header, 316 const unsigned long end) 317 { 318 struct acpi_madt_msi_pic *pchmsi_entry = (struct acpi_madt_msi_pic *)header; 319 struct irq_domain *parent = acpi_get_vec_parent(eiointc_priv[nr_pics - 1]->node, msi_group); 320 321 if (parent) 322 return pch_msi_acpi_init(parent, pchmsi_entry); 323 324 return -EINVAL; 325 } 326 327 static int __init acpi_cascade_irqdomain_init(void) 328 { 329 acpi_table_parse_madt(ACPI_MADT_TYPE_BIO_PIC, 330 pch_pic_parse_madt, 0); 331 acpi_table_parse_madt(ACPI_MADT_TYPE_MSI_PIC, 332 pch_msi_parse_madt, 1); 333 return 0; 334 } 335 336 int __init eiointc_acpi_init(struct irq_domain *parent, 337 struct acpi_madt_eio_pic *acpi_eiointc) 338 { 339 int i, parent_irq; 340 unsigned long node_map; 341 struct eiointc_priv *priv; 342 343 priv = kzalloc(sizeof(*priv), GFP_KERNEL); 344 if (!priv) 345 return -ENOMEM; 346 347 priv->domain_handle = irq_domain_alloc_fwnode((phys_addr_t *)acpi_eiointc); 348 if (!priv->domain_handle) { 349 pr_err("Unable to allocate domain handle\n"); 350 goto out_free_priv; 351 } 352 353 priv->node = acpi_eiointc->node; 354 node_map = acpi_eiointc->node_map ? : -1ULL; 355 356 for_each_possible_cpu(i) { 357 if (node_map & (1ULL << cpu_to_eio_node(i))) { 358 node_set(cpu_to_eio_node(i), priv->node_map); 359 cpumask_or(&priv->cpuspan_map, &priv->cpuspan_map, cpumask_of(i)); 360 } 361 } 362 363 /* Setup IRQ domain */ 364 priv->eiointc_domain = irq_domain_create_linear(priv->domain_handle, VEC_COUNT, 365 &eiointc_domain_ops, priv); 366 if (!priv->eiointc_domain) { 367 pr_err("loongson-eiointc: cannot add IRQ domain\n"); 368 goto out_free_handle; 369 } 370 371 eiointc_priv[nr_pics++] = priv; 372 373 eiointc_router_init(0); 374 375 parent_irq = irq_create_mapping(parent, acpi_eiointc->cascade); 376 irq_set_chained_handler_and_data(parent_irq, eiointc_irq_dispatch, priv); 377 378 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_LOONGARCH_STARTING, 379 "irqchip/loongarch/intc:starting", 380 eiointc_router_init, NULL); 381 382 acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, pch_group); 383 acpi_set_vec_parent(acpi_eiointc->node, priv->eiointc_domain, msi_group); 384 acpi_cascade_irqdomain_init(); 385 386 return 0; 387 388 out_free_handle: 389 irq_domain_free_fwnode(priv->domain_handle); 390 priv->domain_handle = NULL; 391 out_free_priv: 392 kfree(priv); 393 394 return -ENOMEM; 395 } 396