1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (C) 2020-2022 Loongson Technology Corporation Limited
4  */
5 
6 #include <linux/init.h>
7 #include <linux/kernel.h>
8 #include <linux/interrupt.h>
9 #include <linux/irq.h>
10 #include <linux/irqchip.h>
11 #include <linux/irqdomain.h>
12 
13 #include <asm/loongarch.h>
14 #include <asm/setup.h>
15 
16 static struct irq_domain *irq_domain;
17 struct fwnode_handle *cpuintc_handle;
18 
19 static u32 lpic_gsi_to_irq(u32 gsi)
20 {
21 	int irq = 0;
22 
23 	/* Only pch irqdomain transferring is required for LoongArch. */
24 	if (gsi >= GSI_MIN_PCH_IRQ && gsi <= GSI_MAX_PCH_IRQ)
25 		irq = acpi_register_gsi(NULL, gsi, ACPI_LEVEL_SENSITIVE, ACPI_ACTIVE_HIGH);
26 
27 	return (irq > 0) ? irq : 0;
28 }
29 
30 static struct fwnode_handle *lpic_get_gsi_domain_id(u32 gsi)
31 {
32 	int id;
33 	struct fwnode_handle *domain_handle = NULL;
34 
35 	switch (gsi) {
36 	case GSI_MIN_CPU_IRQ ... GSI_MAX_CPU_IRQ:
37 		if (liointc_handle)
38 			domain_handle = liointc_handle;
39 		break;
40 
41 	case GSI_MIN_LPC_IRQ ... GSI_MAX_LPC_IRQ:
42 		if (pch_lpc_handle)
43 			domain_handle = pch_lpc_handle;
44 		break;
45 
46 	case GSI_MIN_PCH_IRQ ... GSI_MAX_PCH_IRQ:
47 		id = find_pch_pic(gsi);
48 		if (id >= 0 && pch_pic_handle[id])
49 			domain_handle = pch_pic_handle[id];
50 		break;
51 	}
52 
53 	return domain_handle;
54 }
55 
56 static void mask_loongarch_irq(struct irq_data *d)
57 {
58 	clear_csr_ecfg(ECFGF(d->hwirq));
59 }
60 
61 static void unmask_loongarch_irq(struct irq_data *d)
62 {
63 	set_csr_ecfg(ECFGF(d->hwirq));
64 }
65 
66 static struct irq_chip cpu_irq_controller = {
67 	.name		= "CPUINTC",
68 	.irq_mask	= mask_loongarch_irq,
69 	.irq_unmask	= unmask_loongarch_irq,
70 };
71 
72 static void handle_cpu_irq(struct pt_regs *regs)
73 {
74 	int hwirq;
75 	unsigned int estat = read_csr_estat() & CSR_ESTAT_IS;
76 
77 	while ((hwirq = ffs(estat))) {
78 		estat &= ~BIT(hwirq - 1);
79 		generic_handle_domain_irq(irq_domain, hwirq - 1);
80 	}
81 }
82 
83 static int loongarch_cpu_intc_map(struct irq_domain *d, unsigned int irq,
84 			     irq_hw_number_t hwirq)
85 {
86 	irq_set_noprobe(irq);
87 	irq_set_chip_and_handler(irq, &cpu_irq_controller, handle_percpu_irq);
88 
89 	return 0;
90 }
91 
92 static const struct irq_domain_ops loongarch_cpu_intc_irq_domain_ops = {
93 	.map = loongarch_cpu_intc_map,
94 	.xlate = irq_domain_xlate_onecell,
95 };
96 
97 #ifdef CONFIG_OF
98 static int __init cpuintc_of_init(struct device_node *of_node,
99 				struct device_node *parent)
100 {
101 	cpuintc_handle = of_node_to_fwnode(of_node);
102 
103 	irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
104 				&loongarch_cpu_intc_irq_domain_ops, NULL);
105 	if (!irq_domain)
106 		panic("Failed to add irqdomain for loongarch CPU");
107 
108 	set_handle_irq(&handle_cpu_irq);
109 
110 	return 0;
111 }
112 IRQCHIP_DECLARE(cpu_intc, "loongson,cpu-interrupt-controller", cpuintc_of_init);
113 #endif
114 
115 static int __init liointc_parse_madt(union acpi_subtable_headers *header,
116 					const unsigned long end)
117 {
118 	struct acpi_madt_lio_pic *liointc_entry = (struct acpi_madt_lio_pic *)header;
119 
120 	return liointc_acpi_init(irq_domain, liointc_entry);
121 }
122 
123 static int __init eiointc_parse_madt(union acpi_subtable_headers *header,
124 					const unsigned long end)
125 {
126 	struct acpi_madt_eio_pic *eiointc_entry = (struct acpi_madt_eio_pic *)header;
127 
128 	return eiointc_acpi_init(irq_domain, eiointc_entry);
129 }
130 
131 static int __init acpi_cascade_irqdomain_init(void)
132 {
133 	int r;
134 
135 	r = acpi_table_parse_madt(ACPI_MADT_TYPE_LIO_PIC, liointc_parse_madt, 0);
136 	if (r < 0)
137 		return r;
138 
139 	r = acpi_table_parse_madt(ACPI_MADT_TYPE_EIO_PIC, eiointc_parse_madt, 0);
140 	if (r < 0)
141 		return r;
142 
143 	return 0;
144 }
145 
146 static int __init cpuintc_acpi_init(union acpi_subtable_headers *header,
147 				   const unsigned long end)
148 {
149 	int ret;
150 
151 	if (irq_domain)
152 		return 0;
153 
154 	/* Mask interrupts. */
155 	clear_csr_ecfg(ECFG0_IM);
156 	clear_csr_estat(ESTATF_IP);
157 
158 	cpuintc_handle = irq_domain_alloc_named_fwnode("CPUINTC");
159 	irq_domain = irq_domain_create_linear(cpuintc_handle, EXCCODE_INT_NUM,
160 					&loongarch_cpu_intc_irq_domain_ops, NULL);
161 
162 	if (!irq_domain)
163 		panic("Failed to add irqdomain for LoongArch CPU");
164 
165 	set_handle_irq(&handle_cpu_irq);
166 	acpi_set_irq_model(ACPI_IRQ_MODEL_LPIC, lpic_get_gsi_domain_id);
167 	acpi_set_gsi_to_irq_fallback(lpic_gsi_to_irq);
168 	ret = acpi_cascade_irqdomain_init();
169 
170 	return ret;
171 }
172 
173 IRQCHIP_ACPI_DECLARE(cpuintc_v1, ACPI_MADT_TYPE_CORE_PIC,
174 		NULL, ACPI_MADT_CORE_PIC_VERSION_V1, cpuintc_acpi_init);
175