1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 4 * JZ4740 platform IRQ support 5 */ 6 7 #include <linux/errno.h> 8 #include <linux/init.h> 9 #include <linux/types.h> 10 #include <linux/interrupt.h> 11 #include <linux/ioport.h> 12 #include <linux/irqchip.h> 13 #include <linux/irqchip/ingenic.h> 14 #include <linux/of_address.h> 15 #include <linux/of_irq.h> 16 #include <linux/timex.h> 17 #include <linux/slab.h> 18 #include <linux/delay.h> 19 20 #include <asm/io.h> 21 #include <asm/mach-jz4740/irq.h> 22 23 struct ingenic_intc_data { 24 void __iomem *base; 25 unsigned num_chips; 26 }; 27 28 #define JZ_REG_INTC_STATUS 0x00 29 #define JZ_REG_INTC_MASK 0x04 30 #define JZ_REG_INTC_SET_MASK 0x08 31 #define JZ_REG_INTC_CLEAR_MASK 0x0c 32 #define JZ_REG_INTC_PENDING 0x10 33 #define CHIP_SIZE 0x20 34 35 static irqreturn_t intc_cascade(int irq, void *data) 36 { 37 struct ingenic_intc_data *intc = irq_get_handler_data(irq); 38 uint32_t irq_reg; 39 unsigned i; 40 41 for (i = 0; i < intc->num_chips; i++) { 42 irq_reg = readl(intc->base + (i * CHIP_SIZE) + 43 JZ_REG_INTC_PENDING); 44 if (!irq_reg) 45 continue; 46 47 generic_handle_irq(__fls(irq_reg) + (i * 32) + JZ4740_IRQ_BASE); 48 } 49 50 return IRQ_HANDLED; 51 } 52 53 static void intc_irq_set_mask(struct irq_chip_generic *gc, uint32_t mask) 54 { 55 struct irq_chip_regs *regs = &gc->chip_types->regs; 56 57 writel(mask, gc->reg_base + regs->enable); 58 writel(~mask, gc->reg_base + regs->disable); 59 } 60 61 void ingenic_intc_irq_suspend(struct irq_data *data) 62 { 63 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 64 intc_irq_set_mask(gc, gc->wake_active); 65 } 66 67 void ingenic_intc_irq_resume(struct irq_data *data) 68 { 69 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data); 70 intc_irq_set_mask(gc, gc->mask_cache); 71 } 72 73 static struct irqaction intc_cascade_action = { 74 .handler = intc_cascade, 75 .name = "SoC intc cascade interrupt", 76 }; 77 78 static int __init ingenic_intc_of_init(struct device_node *node, 79 unsigned num_chips) 80 { 81 struct ingenic_intc_data *intc; 82 struct irq_chip_generic *gc; 83 struct irq_chip_type *ct; 84 struct irq_domain *domain; 85 int parent_irq, err = 0; 86 unsigned i; 87 88 intc = kzalloc(sizeof(*intc), GFP_KERNEL); 89 if (!intc) { 90 err = -ENOMEM; 91 goto out_err; 92 } 93 94 parent_irq = irq_of_parse_and_map(node, 0); 95 if (!parent_irq) { 96 err = -EINVAL; 97 goto out_free; 98 } 99 100 err = irq_set_handler_data(parent_irq, intc); 101 if (err) 102 goto out_unmap_irq; 103 104 intc->num_chips = num_chips; 105 intc->base = of_iomap(node, 0); 106 if (!intc->base) { 107 err = -ENODEV; 108 goto out_unmap_irq; 109 } 110 111 for (i = 0; i < num_chips; i++) { 112 /* Mask all irqs */ 113 writel(0xffffffff, intc->base + (i * CHIP_SIZE) + 114 JZ_REG_INTC_SET_MASK); 115 116 gc = irq_alloc_generic_chip("INTC", 1, 117 JZ4740_IRQ_BASE + (i * 32), 118 intc->base + (i * CHIP_SIZE), 119 handle_level_irq); 120 121 gc->wake_enabled = IRQ_MSK(32); 122 123 ct = gc->chip_types; 124 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; 125 ct->regs.disable = JZ_REG_INTC_SET_MASK; 126 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 127 ct->chip.irq_mask = irq_gc_mask_disable_reg; 128 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; 129 ct->chip.irq_set_wake = irq_gc_set_wake; 130 ct->chip.irq_suspend = ingenic_intc_irq_suspend; 131 ct->chip.irq_resume = ingenic_intc_irq_resume; 132 133 irq_setup_generic_chip(gc, IRQ_MSK(32), 0, 0, 134 IRQ_NOPROBE | IRQ_LEVEL); 135 } 136 137 domain = irq_domain_add_legacy(node, num_chips * 32, JZ4740_IRQ_BASE, 0, 138 &irq_domain_simple_ops, NULL); 139 if (!domain) 140 pr_warn("unable to register IRQ domain\n"); 141 142 setup_irq(parent_irq, &intc_cascade_action); 143 return 0; 144 145 out_unmap_irq: 146 irq_dispose_mapping(parent_irq); 147 out_free: 148 kfree(intc); 149 out_err: 150 return err; 151 } 152 153 static int __init intc_1chip_of_init(struct device_node *node, 154 struct device_node *parent) 155 { 156 return ingenic_intc_of_init(node, 1); 157 } 158 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init); 159 IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init); 160 161 static int __init intc_2chip_of_init(struct device_node *node, 162 struct device_node *parent) 163 { 164 return ingenic_intc_of_init(node, 2); 165 } 166 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); 167 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); 168 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); 169