1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de> 4 * Ingenic XBurst platform IRQ support 5 */ 6 7 #include <linux/errno.h> 8 #include <linux/init.h> 9 #include <linux/types.h> 10 #include <linux/interrupt.h> 11 #include <linux/ioport.h> 12 #include <linux/irqchip.h> 13 #include <linux/of_address.h> 14 #include <linux/of_irq.h> 15 #include <linux/timex.h> 16 #include <linux/slab.h> 17 #include <linux/delay.h> 18 19 #include <asm/io.h> 20 21 struct ingenic_intc_data { 22 void __iomem *base; 23 struct irq_domain *domain; 24 unsigned num_chips; 25 }; 26 27 #define JZ_REG_INTC_STATUS 0x00 28 #define JZ_REG_INTC_MASK 0x04 29 #define JZ_REG_INTC_SET_MASK 0x08 30 #define JZ_REG_INTC_CLEAR_MASK 0x0c 31 #define JZ_REG_INTC_PENDING 0x10 32 #define CHIP_SIZE 0x20 33 34 static irqreturn_t intc_cascade(int irq, void *data) 35 { 36 struct ingenic_intc_data *intc = irq_get_handler_data(irq); 37 struct irq_domain *domain = intc->domain; 38 struct irq_chip_generic *gc; 39 uint32_t pending; 40 unsigned i; 41 42 for (i = 0; i < intc->num_chips; i++) { 43 gc = irq_get_domain_generic_chip(domain, i * 32); 44 45 pending = irq_reg_readl(gc, JZ_REG_INTC_PENDING); 46 if (!pending) 47 continue; 48 49 while (pending) { 50 int bit = __fls(pending); 51 52 irq = irq_linear_revmap(domain, bit + (i * 32)); 53 generic_handle_irq(irq); 54 pending &= ~BIT(bit); 55 } 56 } 57 58 return IRQ_HANDLED; 59 } 60 61 static struct irqaction intc_cascade_action = { 62 .handler = intc_cascade, 63 .name = "SoC intc cascade interrupt", 64 }; 65 66 static int __init ingenic_intc_of_init(struct device_node *node, 67 unsigned num_chips) 68 { 69 struct ingenic_intc_data *intc; 70 struct irq_chip_generic *gc; 71 struct irq_chip_type *ct; 72 struct irq_domain *domain; 73 int parent_irq, err = 0; 74 unsigned i; 75 76 intc = kzalloc(sizeof(*intc), GFP_KERNEL); 77 if (!intc) { 78 err = -ENOMEM; 79 goto out_err; 80 } 81 82 parent_irq = irq_of_parse_and_map(node, 0); 83 if (!parent_irq) { 84 err = -EINVAL; 85 goto out_free; 86 } 87 88 err = irq_set_handler_data(parent_irq, intc); 89 if (err) 90 goto out_unmap_irq; 91 92 intc->num_chips = num_chips; 93 intc->base = of_iomap(node, 0); 94 if (!intc->base) { 95 err = -ENODEV; 96 goto out_unmap_irq; 97 } 98 99 domain = irq_domain_add_linear(node, num_chips * 32, 100 &irq_generic_chip_ops, NULL); 101 if (!domain) { 102 err = -ENOMEM; 103 goto out_unmap_base; 104 } 105 106 intc->domain = domain; 107 108 err = irq_alloc_domain_generic_chips(domain, 32, 1, "INTC", 109 handle_level_irq, 0, 110 IRQ_NOPROBE | IRQ_LEVEL, 0); 111 if (err) 112 goto out_domain_remove; 113 114 for (i = 0; i < num_chips; i++) { 115 gc = irq_get_domain_generic_chip(domain, i * 32); 116 117 gc->wake_enabled = IRQ_MSK(32); 118 gc->reg_base = intc->base + (i * CHIP_SIZE); 119 120 ct = gc->chip_types; 121 ct->regs.enable = JZ_REG_INTC_CLEAR_MASK; 122 ct->regs.disable = JZ_REG_INTC_SET_MASK; 123 ct->chip.irq_unmask = irq_gc_unmask_enable_reg; 124 ct->chip.irq_mask = irq_gc_mask_disable_reg; 125 ct->chip.irq_mask_ack = irq_gc_mask_disable_reg; 126 ct->chip.irq_set_wake = irq_gc_set_wake; 127 ct->chip.flags = IRQCHIP_MASK_ON_SUSPEND; 128 129 /* Mask all irqs */ 130 irq_reg_writel(gc, IRQ_MSK(32), JZ_REG_INTC_SET_MASK); 131 } 132 133 setup_irq(parent_irq, &intc_cascade_action); 134 return 0; 135 136 out_domain_remove: 137 irq_domain_remove(domain); 138 out_unmap_base: 139 iounmap(intc->base); 140 out_unmap_irq: 141 irq_dispose_mapping(parent_irq); 142 out_free: 143 kfree(intc); 144 out_err: 145 return err; 146 } 147 148 static int __init intc_1chip_of_init(struct device_node *node, 149 struct device_node *parent) 150 { 151 return ingenic_intc_of_init(node, 1); 152 } 153 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init); 154 IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init); 155 156 static int __init intc_2chip_of_init(struct device_node *node, 157 struct device_node *parent) 158 { 159 return ingenic_intc_of_init(node, 2); 160 } 161 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init); 162 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init); 163 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init); 164