170afdab9SFrank Li // SPDX-License-Identifier: GPL-2.0-only 270afdab9SFrank Li /* 370afdab9SFrank Li * Freescale MU used as MSI controller 470afdab9SFrank Li * 570afdab9SFrank Li * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> 670afdab9SFrank Li * Copyright 2022 NXP 770afdab9SFrank Li * Frank Li <Frank.Li@nxp.com> 870afdab9SFrank Li * Peng Fan <peng.fan@nxp.com> 970afdab9SFrank Li * 1070afdab9SFrank Li * Based on drivers/mailbox/imx-mailbox.c 1170afdab9SFrank Li */ 1270afdab9SFrank Li 1370afdab9SFrank Li #include <linux/clk.h> 1470afdab9SFrank Li #include <linux/irq.h> 1570afdab9SFrank Li #include <linux/irqchip.h> 1670afdab9SFrank Li #include <linux/irqchip/chained_irq.h> 1770afdab9SFrank Li #include <linux/irqdomain.h> 1870afdab9SFrank Li #include <linux/kernel.h> 1970afdab9SFrank Li #include <linux/module.h> 2070afdab9SFrank Li #include <linux/msi.h> 2170afdab9SFrank Li #include <linux/of_irq.h> 2270afdab9SFrank Li #include <linux/of_platform.h> 2370afdab9SFrank Li #include <linux/pm_runtime.h> 2470afdab9SFrank Li #include <linux/pm_domain.h> 2570afdab9SFrank Li #include <linux/spinlock.h> 2670afdab9SFrank Li 2770afdab9SFrank Li #define IMX_MU_CHANS 4 2870afdab9SFrank Li 2970afdab9SFrank Li enum imx_mu_xcr { 3070afdab9SFrank Li IMX_MU_GIER, 3170afdab9SFrank Li IMX_MU_GCR, 3270afdab9SFrank Li IMX_MU_TCR, 3370afdab9SFrank Li IMX_MU_RCR, 3470afdab9SFrank Li IMX_MU_xCR_MAX, 3570afdab9SFrank Li }; 3670afdab9SFrank Li 3770afdab9SFrank Li enum imx_mu_xsr { 3870afdab9SFrank Li IMX_MU_SR, 3970afdab9SFrank Li IMX_MU_GSR, 4070afdab9SFrank Li IMX_MU_TSR, 4170afdab9SFrank Li IMX_MU_RSR, 4270afdab9SFrank Li IMX_MU_xSR_MAX 4370afdab9SFrank Li }; 4470afdab9SFrank Li 4570afdab9SFrank Li enum imx_mu_type { 4670afdab9SFrank Li IMX_MU_V2 = BIT(1), 4770afdab9SFrank Li }; 4870afdab9SFrank Li 4970afdab9SFrank Li /* Receive Interrupt Enable */ 5070afdab9SFrank Li #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 5170afdab9SFrank Li #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 5270afdab9SFrank Li 5370afdab9SFrank Li struct imx_mu_dcfg { 5470afdab9SFrank Li enum imx_mu_type type; 5570afdab9SFrank Li u32 xTR; /* Transmit Register0 */ 5670afdab9SFrank Li u32 xRR; /* Receive Register0 */ 5770afdab9SFrank Li u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ 5870afdab9SFrank Li u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ 5970afdab9SFrank Li }; 6070afdab9SFrank Li 6170afdab9SFrank Li struct imx_mu_msi { 6270afdab9SFrank Li raw_spinlock_t lock; 6370afdab9SFrank Li struct irq_domain *msi_domain; 6470afdab9SFrank Li void __iomem *regs; 6570afdab9SFrank Li phys_addr_t msiir_addr; 6670afdab9SFrank Li const struct imx_mu_dcfg *cfg; 6770afdab9SFrank Li unsigned long used; 6870afdab9SFrank Li struct clk *clk; 6970afdab9SFrank Li }; 7070afdab9SFrank Li 7170afdab9SFrank Li static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs) 7270afdab9SFrank Li { 7370afdab9SFrank Li iowrite32(val, msi_data->regs + offs); 7470afdab9SFrank Li } 7570afdab9SFrank Li 7670afdab9SFrank Li static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs) 7770afdab9SFrank Li { 7870afdab9SFrank Li return ioread32(msi_data->regs + offs); 7970afdab9SFrank Li } 8070afdab9SFrank Li 8170afdab9SFrank Li static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr type, u32 set, u32 clr) 8270afdab9SFrank Li { 8370afdab9SFrank Li unsigned long flags; 8470afdab9SFrank Li u32 val; 8570afdab9SFrank Li 8670afdab9SFrank Li raw_spin_lock_irqsave(&msi_data->lock, flags); 8770afdab9SFrank Li val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); 8870afdab9SFrank Li val &= ~clr; 8970afdab9SFrank Li val |= set; 9070afdab9SFrank Li imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); 9170afdab9SFrank Li raw_spin_unlock_irqrestore(&msi_data->lock, flags); 9270afdab9SFrank Li 9370afdab9SFrank Li return val; 9470afdab9SFrank Li } 9570afdab9SFrank Li 9670afdab9SFrank Li static void imx_mu_msi_parent_mask_irq(struct irq_data *data) 9770afdab9SFrank Li { 9870afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 9970afdab9SFrank Li 10070afdab9SFrank Li imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq)); 10170afdab9SFrank Li } 10270afdab9SFrank Li 10370afdab9SFrank Li static void imx_mu_msi_parent_unmask_irq(struct irq_data *data) 10470afdab9SFrank Li { 10570afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 10670afdab9SFrank Li 10770afdab9SFrank Li imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0); 10870afdab9SFrank Li } 10970afdab9SFrank Li 11070afdab9SFrank Li static void imx_mu_msi_parent_ack_irq(struct irq_data *data) 11170afdab9SFrank Li { 11270afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 11370afdab9SFrank Li 11470afdab9SFrank Li imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4); 11570afdab9SFrank Li } 11670afdab9SFrank Li 11770afdab9SFrank Li static struct irq_chip imx_mu_msi_irq_chip = { 11870afdab9SFrank Li .name = "MU-MSI", 11970afdab9SFrank Li .irq_ack = irq_chip_ack_parent, 12070afdab9SFrank Li }; 12170afdab9SFrank Li 12270afdab9SFrank Li static struct msi_domain_ops imx_mu_msi_irq_ops = { 12370afdab9SFrank Li }; 12470afdab9SFrank Li 12570afdab9SFrank Li static struct msi_domain_info imx_mu_msi_domain_info = { 12670afdab9SFrank Li .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), 12770afdab9SFrank Li .ops = &imx_mu_msi_irq_ops, 12870afdab9SFrank Li .chip = &imx_mu_msi_irq_chip, 12970afdab9SFrank Li }; 13070afdab9SFrank Li 13170afdab9SFrank Li static void imx_mu_msi_parent_compose_msg(struct irq_data *data, 13270afdab9SFrank Li struct msi_msg *msg) 13370afdab9SFrank Li { 13470afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 13570afdab9SFrank Li u64 addr = msi_data->msiir_addr + 4 * data->hwirq; 13670afdab9SFrank Li 13770afdab9SFrank Li msg->address_hi = upper_32_bits(addr); 13870afdab9SFrank Li msg->address_lo = lower_32_bits(addr); 13970afdab9SFrank Li msg->data = data->hwirq; 14070afdab9SFrank Li } 14170afdab9SFrank Li 14270afdab9SFrank Li static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data, 14370afdab9SFrank Li const struct cpumask *mask, bool force) 14470afdab9SFrank Li { 14570afdab9SFrank Li return -EINVAL; 14670afdab9SFrank Li } 14770afdab9SFrank Li 14870afdab9SFrank Li static struct irq_chip imx_mu_msi_parent_chip = { 14970afdab9SFrank Li .name = "MU", 15070afdab9SFrank Li .irq_mask = imx_mu_msi_parent_mask_irq, 15170afdab9SFrank Li .irq_unmask = imx_mu_msi_parent_unmask_irq, 15270afdab9SFrank Li .irq_ack = imx_mu_msi_parent_ack_irq, 15370afdab9SFrank Li .irq_compose_msi_msg = imx_mu_msi_parent_compose_msg, 15470afdab9SFrank Li .irq_set_affinity = imx_mu_msi_parent_set_affinity, 15570afdab9SFrank Li }; 15670afdab9SFrank Li 15770afdab9SFrank Li static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain, 15870afdab9SFrank Li unsigned int virq, 15970afdab9SFrank Li unsigned int nr_irqs, 16070afdab9SFrank Li void *args) 16170afdab9SFrank Li { 16270afdab9SFrank Li struct imx_mu_msi *msi_data = domain->host_data; 16370afdab9SFrank Li unsigned long flags; 16470afdab9SFrank Li int pos, err = 0; 16570afdab9SFrank Li 16670afdab9SFrank Li WARN_ON(nr_irqs != 1); 16770afdab9SFrank Li 16870afdab9SFrank Li raw_spin_lock_irqsave(&msi_data->lock, flags); 16970afdab9SFrank Li pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS); 17070afdab9SFrank Li if (pos < IMX_MU_CHANS) 17170afdab9SFrank Li __set_bit(pos, &msi_data->used); 17270afdab9SFrank Li else 17370afdab9SFrank Li err = -ENOSPC; 17470afdab9SFrank Li raw_spin_unlock_irqrestore(&msi_data->lock, flags); 17570afdab9SFrank Li 17670afdab9SFrank Li if (err) 17770afdab9SFrank Li return err; 17870afdab9SFrank Li 17970afdab9SFrank Li irq_domain_set_info(domain, virq, pos, 18070afdab9SFrank Li &imx_mu_msi_parent_chip, msi_data, 18170afdab9SFrank Li handle_edge_irq, NULL, NULL); 18270afdab9SFrank Li return 0; 18370afdab9SFrank Li } 18470afdab9SFrank Li 18570afdab9SFrank Li static void imx_mu_msi_domain_irq_free(struct irq_domain *domain, 18670afdab9SFrank Li unsigned int virq, unsigned int nr_irqs) 18770afdab9SFrank Li { 18870afdab9SFrank Li struct irq_data *d = irq_domain_get_irq_data(domain, virq); 18970afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d); 19070afdab9SFrank Li unsigned long flags; 19170afdab9SFrank Li 19270afdab9SFrank Li raw_spin_lock_irqsave(&msi_data->lock, flags); 19370afdab9SFrank Li __clear_bit(d->hwirq, &msi_data->used); 19470afdab9SFrank Li raw_spin_unlock_irqrestore(&msi_data->lock, flags); 19570afdab9SFrank Li } 19670afdab9SFrank Li 19770afdab9SFrank Li static const struct irq_domain_ops imx_mu_msi_domain_ops = { 19870afdab9SFrank Li .alloc = imx_mu_msi_domain_irq_alloc, 19970afdab9SFrank Li .free = imx_mu_msi_domain_irq_free, 20070afdab9SFrank Li }; 20170afdab9SFrank Li 20270afdab9SFrank Li static void imx_mu_msi_irq_handler(struct irq_desc *desc) 20370afdab9SFrank Li { 20470afdab9SFrank Li struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc); 20570afdab9SFrank Li struct irq_chip *chip = irq_desc_get_chip(desc); 20670afdab9SFrank Li u32 status; 20770afdab9SFrank Li int i; 20870afdab9SFrank Li 20970afdab9SFrank Li status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]); 21070afdab9SFrank Li 21170afdab9SFrank Li chained_irq_enter(chip, desc); 21270afdab9SFrank Li for (i = 0; i < IMX_MU_CHANS; i++) { 21370afdab9SFrank Li if (status & IMX_MU_xSR_RFn(msi_data, i)) 21470afdab9SFrank Li generic_handle_domain_irq(msi_data->msi_domain, i); 21570afdab9SFrank Li } 21670afdab9SFrank Li chained_irq_exit(chip, desc); 21770afdab9SFrank Li } 21870afdab9SFrank Li 21970afdab9SFrank Li static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev) 22070afdab9SFrank Li { 22170afdab9SFrank Li struct fwnode_handle *fwnodes = dev_fwnode(dev); 22270afdab9SFrank Li struct irq_domain *parent; 22370afdab9SFrank Li 22470afdab9SFrank Li /* Initialize MSI domain parent */ 22570afdab9SFrank Li parent = irq_domain_create_linear(fwnodes, 22670afdab9SFrank Li IMX_MU_CHANS, 22770afdab9SFrank Li &imx_mu_msi_domain_ops, 22870afdab9SFrank Li msi_data); 22970afdab9SFrank Li if (!parent) { 23070afdab9SFrank Li dev_err(dev, "failed to create IRQ domain\n"); 23170afdab9SFrank Li return -ENOMEM; 23270afdab9SFrank Li } 23370afdab9SFrank Li 23470afdab9SFrank Li irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); 23570afdab9SFrank Li 23670afdab9SFrank Li msi_data->msi_domain = platform_msi_create_irq_domain(fwnodes, 23770afdab9SFrank Li &imx_mu_msi_domain_info, 23870afdab9SFrank Li parent); 23970afdab9SFrank Li 24070afdab9SFrank Li if (!msi_data->msi_domain) { 24170afdab9SFrank Li dev_err(dev, "failed to create MSI domain\n"); 24270afdab9SFrank Li irq_domain_remove(parent); 24370afdab9SFrank Li return -ENOMEM; 24470afdab9SFrank Li } 24570afdab9SFrank Li 24670afdab9SFrank Li irq_domain_set_pm_device(msi_data->msi_domain, dev); 24770afdab9SFrank Li 24870afdab9SFrank Li return 0; 24970afdab9SFrank Li } 25070afdab9SFrank Li 25170afdab9SFrank Li /* Register offset of different version MU IP */ 25270afdab9SFrank Li static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 25370afdab9SFrank Li .type = 0, 25470afdab9SFrank Li .xTR = 0x0, 25570afdab9SFrank Li .xRR = 0x10, 25670afdab9SFrank Li .xSR = { 25770afdab9SFrank Li [IMX_MU_SR] = 0x20, 25870afdab9SFrank Li [IMX_MU_GSR] = 0x20, 25970afdab9SFrank Li [IMX_MU_TSR] = 0x20, 26070afdab9SFrank Li [IMX_MU_RSR] = 0x20, 26170afdab9SFrank Li }, 26270afdab9SFrank Li .xCR = { 26370afdab9SFrank Li [IMX_MU_GIER] = 0x24, 26470afdab9SFrank Li [IMX_MU_GCR] = 0x24, 26570afdab9SFrank Li [IMX_MU_TCR] = 0x24, 26670afdab9SFrank Li [IMX_MU_RCR] = 0x24, 26770afdab9SFrank Li }, 26870afdab9SFrank Li }; 26970afdab9SFrank Li 27070afdab9SFrank Li static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 27170afdab9SFrank Li .type = 0, 27270afdab9SFrank Li .xTR = 0x20, 27370afdab9SFrank Li .xRR = 0x40, 27470afdab9SFrank Li .xSR = { 27570afdab9SFrank Li [IMX_MU_SR] = 0x60, 27670afdab9SFrank Li [IMX_MU_GSR] = 0x60, 27770afdab9SFrank Li [IMX_MU_TSR] = 0x60, 27870afdab9SFrank Li [IMX_MU_RSR] = 0x60, 27970afdab9SFrank Li }, 28070afdab9SFrank Li .xCR = { 28170afdab9SFrank Li [IMX_MU_GIER] = 0x64, 28270afdab9SFrank Li [IMX_MU_GCR] = 0x64, 28370afdab9SFrank Li [IMX_MU_TCR] = 0x64, 28470afdab9SFrank Li [IMX_MU_RCR] = 0x64, 28570afdab9SFrank Li }, 28670afdab9SFrank Li }; 28770afdab9SFrank Li 28870afdab9SFrank Li static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { 28970afdab9SFrank Li .type = IMX_MU_V2, 29070afdab9SFrank Li .xTR = 0x200, 29170afdab9SFrank Li .xRR = 0x280, 29270afdab9SFrank Li .xSR = { 29370afdab9SFrank Li [IMX_MU_SR] = 0xC, 29470afdab9SFrank Li [IMX_MU_GSR] = 0x118, 295*e4a7e67aSFrank Li [IMX_MU_TSR] = 0x124, 29670afdab9SFrank Li [IMX_MU_RSR] = 0x12C, 29770afdab9SFrank Li }, 29870afdab9SFrank Li .xCR = { 29970afdab9SFrank Li [IMX_MU_GIER] = 0x110, 30070afdab9SFrank Li [IMX_MU_GCR] = 0x114, 30170afdab9SFrank Li [IMX_MU_TCR] = 0x120, 30270afdab9SFrank Li [IMX_MU_RCR] = 0x128 30370afdab9SFrank Li }, 30470afdab9SFrank Li }; 30570afdab9SFrank Li 30670afdab9SFrank Li static int __init imx_mu_of_init(struct device_node *dn, 30770afdab9SFrank Li struct device_node *parent, 30870afdab9SFrank Li const struct imx_mu_dcfg *cfg) 30970afdab9SFrank Li { 31070afdab9SFrank Li struct platform_device *pdev = of_find_device_by_node(dn); 31170afdab9SFrank Li struct device_link *pd_link_a; 31270afdab9SFrank Li struct device_link *pd_link_b; 31370afdab9SFrank Li struct imx_mu_msi *msi_data; 31470afdab9SFrank Li struct resource *res; 31570afdab9SFrank Li struct device *pd_a; 31670afdab9SFrank Li struct device *pd_b; 31770afdab9SFrank Li struct device *dev; 31870afdab9SFrank Li int ret; 31970afdab9SFrank Li int irq; 32070afdab9SFrank Li 32170afdab9SFrank Li dev = &pdev->dev; 32270afdab9SFrank Li 32370afdab9SFrank Li msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); 32470afdab9SFrank Li if (!msi_data) 32570afdab9SFrank Li return -ENOMEM; 32670afdab9SFrank Li 32770afdab9SFrank Li msi_data->cfg = cfg; 32870afdab9SFrank Li 32970afdab9SFrank Li msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor-a-side"); 33070afdab9SFrank Li if (IS_ERR(msi_data->regs)) { 33170afdab9SFrank Li dev_err(&pdev->dev, "failed to initialize 'regs'\n"); 33270afdab9SFrank Li return PTR_ERR(msi_data->regs); 33370afdab9SFrank Li } 33470afdab9SFrank Li 33570afdab9SFrank Li res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor-b-side"); 33670afdab9SFrank Li if (!res) 33770afdab9SFrank Li return -EIO; 33870afdab9SFrank Li 33970afdab9SFrank Li msi_data->msiir_addr = res->start + msi_data->cfg->xTR; 34070afdab9SFrank Li 34170afdab9SFrank Li irq = platform_get_irq(pdev, 0); 34270afdab9SFrank Li if (irq <= 0) 34370afdab9SFrank Li return -ENODEV; 34470afdab9SFrank Li 34570afdab9SFrank Li platform_set_drvdata(pdev, msi_data); 34670afdab9SFrank Li 34770afdab9SFrank Li msi_data->clk = devm_clk_get(dev, NULL); 34870afdab9SFrank Li if (IS_ERR(msi_data->clk)) 34970afdab9SFrank Li return PTR_ERR(msi_data->clk); 35070afdab9SFrank Li 35170afdab9SFrank Li pd_a = dev_pm_domain_attach_by_name(dev, "processor-a-side"); 35270afdab9SFrank Li if (IS_ERR(pd_a)) 35370afdab9SFrank Li return PTR_ERR(pd_a); 35470afdab9SFrank Li 35570afdab9SFrank Li pd_b = dev_pm_domain_attach_by_name(dev, "processor-b-side"); 35670afdab9SFrank Li if (IS_ERR(pd_b)) 35770afdab9SFrank Li return PTR_ERR(pd_b); 35870afdab9SFrank Li 35970afdab9SFrank Li pd_link_a = device_link_add(dev, pd_a, 36070afdab9SFrank Li DL_FLAG_STATELESS | 36170afdab9SFrank Li DL_FLAG_PM_RUNTIME | 36270afdab9SFrank Li DL_FLAG_RPM_ACTIVE); 36370afdab9SFrank Li 36470afdab9SFrank Li if (!pd_link_a) { 36570afdab9SFrank Li dev_err(dev, "Failed to add device_link to mu a.\n"); 36670afdab9SFrank Li goto err_pd_a; 36770afdab9SFrank Li } 36870afdab9SFrank Li 36970afdab9SFrank Li pd_link_b = device_link_add(dev, pd_b, 37070afdab9SFrank Li DL_FLAG_STATELESS | 37170afdab9SFrank Li DL_FLAG_PM_RUNTIME | 37270afdab9SFrank Li DL_FLAG_RPM_ACTIVE); 37370afdab9SFrank Li 37470afdab9SFrank Li 37570afdab9SFrank Li if (!pd_link_b) { 37670afdab9SFrank Li dev_err(dev, "Failed to add device_link to mu a.\n"); 37770afdab9SFrank Li goto err_pd_b; 37870afdab9SFrank Li } 37970afdab9SFrank Li 38070afdab9SFrank Li ret = imx_mu_msi_domains_init(msi_data, dev); 38170afdab9SFrank Li if (ret) 38270afdab9SFrank Li goto err_dm_init; 38370afdab9SFrank Li 38470afdab9SFrank Li pm_runtime_enable(dev); 38570afdab9SFrank Li 38670afdab9SFrank Li irq_set_chained_handler_and_data(irq, 38770afdab9SFrank Li imx_mu_msi_irq_handler, 38870afdab9SFrank Li msi_data); 38970afdab9SFrank Li 39070afdab9SFrank Li return 0; 39170afdab9SFrank Li 39270afdab9SFrank Li err_dm_init: 39370afdab9SFrank Li device_link_remove(dev, pd_b); 39470afdab9SFrank Li err_pd_b: 39570afdab9SFrank Li device_link_remove(dev, pd_a); 39670afdab9SFrank Li err_pd_a: 39770afdab9SFrank Li return -EINVAL; 39870afdab9SFrank Li } 39970afdab9SFrank Li 40070afdab9SFrank Li static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) 40170afdab9SFrank Li { 40270afdab9SFrank Li struct imx_mu_msi *priv = dev_get_drvdata(dev); 40370afdab9SFrank Li 40470afdab9SFrank Li clk_disable_unprepare(priv->clk); 40570afdab9SFrank Li 40670afdab9SFrank Li return 0; 40770afdab9SFrank Li } 40870afdab9SFrank Li 40970afdab9SFrank Li static int __maybe_unused imx_mu_runtime_resume(struct device *dev) 41070afdab9SFrank Li { 41170afdab9SFrank Li struct imx_mu_msi *priv = dev_get_drvdata(dev); 41270afdab9SFrank Li int ret; 41370afdab9SFrank Li 41470afdab9SFrank Li ret = clk_prepare_enable(priv->clk); 41570afdab9SFrank Li if (ret) 41670afdab9SFrank Li dev_err(dev, "failed to enable clock\n"); 41770afdab9SFrank Li 41870afdab9SFrank Li return ret; 41970afdab9SFrank Li } 42070afdab9SFrank Li 42170afdab9SFrank Li static const struct dev_pm_ops imx_mu_pm_ops = { 42270afdab9SFrank Li SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, 42370afdab9SFrank Li imx_mu_runtime_resume, NULL) 42470afdab9SFrank Li }; 42570afdab9SFrank Li 42670afdab9SFrank Li static int __init imx_mu_imx7ulp_of_init(struct device_node *dn, 42770afdab9SFrank Li struct device_node *parent) 42870afdab9SFrank Li { 42970afdab9SFrank Li return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp); 43070afdab9SFrank Li } 43170afdab9SFrank Li 43270afdab9SFrank Li static int __init imx_mu_imx6sx_of_init(struct device_node *dn, 43370afdab9SFrank Li struct device_node *parent) 43470afdab9SFrank Li { 43570afdab9SFrank Li return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx); 43670afdab9SFrank Li } 43770afdab9SFrank Li 43870afdab9SFrank Li static int __init imx_mu_imx8ulp_of_init(struct device_node *dn, 43970afdab9SFrank Li struct device_node *parent) 44070afdab9SFrank Li { 44170afdab9SFrank Li return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp); 44270afdab9SFrank Li } 44370afdab9SFrank Li 44470afdab9SFrank Li IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi) 44570afdab9SFrank Li IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init) 44670afdab9SFrank Li IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init) 44770afdab9SFrank Li IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init) 44870afdab9SFrank Li IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm = &imx_mu_pm_ops) 44970afdab9SFrank Li 45070afdab9SFrank Li 45170afdab9SFrank Li MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>"); 45270afdab9SFrank Li MODULE_DESCRIPTION("Freescale MU MSI controller driver"); 45370afdab9SFrank Li MODULE_LICENSE("GPL"); 454