1*70afdab9SFrank Li // SPDX-License-Identifier: GPL-2.0-only 2*70afdab9SFrank Li /* 3*70afdab9SFrank Li * Freescale MU used as MSI controller 4*70afdab9SFrank Li * 5*70afdab9SFrank Li * Copyright (c) 2018 Pengutronix, Oleksij Rempel <o.rempel@pengutronix.de> 6*70afdab9SFrank Li * Copyright 2022 NXP 7*70afdab9SFrank Li * Frank Li <Frank.Li@nxp.com> 8*70afdab9SFrank Li * Peng Fan <peng.fan@nxp.com> 9*70afdab9SFrank Li * 10*70afdab9SFrank Li * Based on drivers/mailbox/imx-mailbox.c 11*70afdab9SFrank Li */ 12*70afdab9SFrank Li 13*70afdab9SFrank Li #include <linux/clk.h> 14*70afdab9SFrank Li #include <linux/irq.h> 15*70afdab9SFrank Li #include <linux/irqchip.h> 16*70afdab9SFrank Li #include <linux/irqchip/chained_irq.h> 17*70afdab9SFrank Li #include <linux/irqdomain.h> 18*70afdab9SFrank Li #include <linux/kernel.h> 19*70afdab9SFrank Li #include <linux/module.h> 20*70afdab9SFrank Li #include <linux/msi.h> 21*70afdab9SFrank Li #include <linux/of_irq.h> 22*70afdab9SFrank Li #include <linux/of_platform.h> 23*70afdab9SFrank Li #include <linux/pm_runtime.h> 24*70afdab9SFrank Li #include <linux/pm_domain.h> 25*70afdab9SFrank Li #include <linux/spinlock.h> 26*70afdab9SFrank Li 27*70afdab9SFrank Li #define IMX_MU_CHANS 4 28*70afdab9SFrank Li 29*70afdab9SFrank Li enum imx_mu_xcr { 30*70afdab9SFrank Li IMX_MU_GIER, 31*70afdab9SFrank Li IMX_MU_GCR, 32*70afdab9SFrank Li IMX_MU_TCR, 33*70afdab9SFrank Li IMX_MU_RCR, 34*70afdab9SFrank Li IMX_MU_xCR_MAX, 35*70afdab9SFrank Li }; 36*70afdab9SFrank Li 37*70afdab9SFrank Li enum imx_mu_xsr { 38*70afdab9SFrank Li IMX_MU_SR, 39*70afdab9SFrank Li IMX_MU_GSR, 40*70afdab9SFrank Li IMX_MU_TSR, 41*70afdab9SFrank Li IMX_MU_RSR, 42*70afdab9SFrank Li IMX_MU_xSR_MAX 43*70afdab9SFrank Li }; 44*70afdab9SFrank Li 45*70afdab9SFrank Li enum imx_mu_type { 46*70afdab9SFrank Li IMX_MU_V2 = BIT(1), 47*70afdab9SFrank Li }; 48*70afdab9SFrank Li 49*70afdab9SFrank Li /* Receive Interrupt Enable */ 50*70afdab9SFrank Li #define IMX_MU_xCR_RIEn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 51*70afdab9SFrank Li #define IMX_MU_xSR_RFn(data, x) ((data->cfg->type) & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x)))) 52*70afdab9SFrank Li 53*70afdab9SFrank Li struct imx_mu_dcfg { 54*70afdab9SFrank Li enum imx_mu_type type; 55*70afdab9SFrank Li u32 xTR; /* Transmit Register0 */ 56*70afdab9SFrank Li u32 xRR; /* Receive Register0 */ 57*70afdab9SFrank Li u32 xSR[IMX_MU_xSR_MAX]; /* Status Registers */ 58*70afdab9SFrank Li u32 xCR[IMX_MU_xCR_MAX]; /* Control Registers */ 59*70afdab9SFrank Li }; 60*70afdab9SFrank Li 61*70afdab9SFrank Li struct imx_mu_msi { 62*70afdab9SFrank Li raw_spinlock_t lock; 63*70afdab9SFrank Li struct irq_domain *msi_domain; 64*70afdab9SFrank Li void __iomem *regs; 65*70afdab9SFrank Li phys_addr_t msiir_addr; 66*70afdab9SFrank Li const struct imx_mu_dcfg *cfg; 67*70afdab9SFrank Li unsigned long used; 68*70afdab9SFrank Li struct clk *clk; 69*70afdab9SFrank Li }; 70*70afdab9SFrank Li 71*70afdab9SFrank Li static void imx_mu_write(struct imx_mu_msi *msi_data, u32 val, u32 offs) 72*70afdab9SFrank Li { 73*70afdab9SFrank Li iowrite32(val, msi_data->regs + offs); 74*70afdab9SFrank Li } 75*70afdab9SFrank Li 76*70afdab9SFrank Li static u32 imx_mu_read(struct imx_mu_msi *msi_data, u32 offs) 77*70afdab9SFrank Li { 78*70afdab9SFrank Li return ioread32(msi_data->regs + offs); 79*70afdab9SFrank Li } 80*70afdab9SFrank Li 81*70afdab9SFrank Li static u32 imx_mu_xcr_rmw(struct imx_mu_msi *msi_data, enum imx_mu_xcr type, u32 set, u32 clr) 82*70afdab9SFrank Li { 83*70afdab9SFrank Li unsigned long flags; 84*70afdab9SFrank Li u32 val; 85*70afdab9SFrank Li 86*70afdab9SFrank Li raw_spin_lock_irqsave(&msi_data->lock, flags); 87*70afdab9SFrank Li val = imx_mu_read(msi_data, msi_data->cfg->xCR[type]); 88*70afdab9SFrank Li val &= ~clr; 89*70afdab9SFrank Li val |= set; 90*70afdab9SFrank Li imx_mu_write(msi_data, val, msi_data->cfg->xCR[type]); 91*70afdab9SFrank Li raw_spin_unlock_irqrestore(&msi_data->lock, flags); 92*70afdab9SFrank Li 93*70afdab9SFrank Li return val; 94*70afdab9SFrank Li } 95*70afdab9SFrank Li 96*70afdab9SFrank Li static void imx_mu_msi_parent_mask_irq(struct irq_data *data) 97*70afdab9SFrank Li { 98*70afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 99*70afdab9SFrank Li 100*70afdab9SFrank Li imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(msi_data, data->hwirq)); 101*70afdab9SFrank Li } 102*70afdab9SFrank Li 103*70afdab9SFrank Li static void imx_mu_msi_parent_unmask_irq(struct irq_data *data) 104*70afdab9SFrank Li { 105*70afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 106*70afdab9SFrank Li 107*70afdab9SFrank Li imx_mu_xcr_rmw(msi_data, IMX_MU_RCR, IMX_MU_xCR_RIEn(msi_data, data->hwirq), 0); 108*70afdab9SFrank Li } 109*70afdab9SFrank Li 110*70afdab9SFrank Li static void imx_mu_msi_parent_ack_irq(struct irq_data *data) 111*70afdab9SFrank Li { 112*70afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 113*70afdab9SFrank Li 114*70afdab9SFrank Li imx_mu_read(msi_data, msi_data->cfg->xRR + data->hwirq * 4); 115*70afdab9SFrank Li } 116*70afdab9SFrank Li 117*70afdab9SFrank Li static struct irq_chip imx_mu_msi_irq_chip = { 118*70afdab9SFrank Li .name = "MU-MSI", 119*70afdab9SFrank Li .irq_ack = irq_chip_ack_parent, 120*70afdab9SFrank Li }; 121*70afdab9SFrank Li 122*70afdab9SFrank Li static struct msi_domain_ops imx_mu_msi_irq_ops = { 123*70afdab9SFrank Li }; 124*70afdab9SFrank Li 125*70afdab9SFrank Li static struct msi_domain_info imx_mu_msi_domain_info = { 126*70afdab9SFrank Li .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS), 127*70afdab9SFrank Li .ops = &imx_mu_msi_irq_ops, 128*70afdab9SFrank Li .chip = &imx_mu_msi_irq_chip, 129*70afdab9SFrank Li }; 130*70afdab9SFrank Li 131*70afdab9SFrank Li static void imx_mu_msi_parent_compose_msg(struct irq_data *data, 132*70afdab9SFrank Li struct msi_msg *msg) 133*70afdab9SFrank Li { 134*70afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(data); 135*70afdab9SFrank Li u64 addr = msi_data->msiir_addr + 4 * data->hwirq; 136*70afdab9SFrank Li 137*70afdab9SFrank Li msg->address_hi = upper_32_bits(addr); 138*70afdab9SFrank Li msg->address_lo = lower_32_bits(addr); 139*70afdab9SFrank Li msg->data = data->hwirq; 140*70afdab9SFrank Li } 141*70afdab9SFrank Li 142*70afdab9SFrank Li static int imx_mu_msi_parent_set_affinity(struct irq_data *irq_data, 143*70afdab9SFrank Li const struct cpumask *mask, bool force) 144*70afdab9SFrank Li { 145*70afdab9SFrank Li return -EINVAL; 146*70afdab9SFrank Li } 147*70afdab9SFrank Li 148*70afdab9SFrank Li static struct irq_chip imx_mu_msi_parent_chip = { 149*70afdab9SFrank Li .name = "MU", 150*70afdab9SFrank Li .irq_mask = imx_mu_msi_parent_mask_irq, 151*70afdab9SFrank Li .irq_unmask = imx_mu_msi_parent_unmask_irq, 152*70afdab9SFrank Li .irq_ack = imx_mu_msi_parent_ack_irq, 153*70afdab9SFrank Li .irq_compose_msi_msg = imx_mu_msi_parent_compose_msg, 154*70afdab9SFrank Li .irq_set_affinity = imx_mu_msi_parent_set_affinity, 155*70afdab9SFrank Li }; 156*70afdab9SFrank Li 157*70afdab9SFrank Li static int imx_mu_msi_domain_irq_alloc(struct irq_domain *domain, 158*70afdab9SFrank Li unsigned int virq, 159*70afdab9SFrank Li unsigned int nr_irqs, 160*70afdab9SFrank Li void *args) 161*70afdab9SFrank Li { 162*70afdab9SFrank Li struct imx_mu_msi *msi_data = domain->host_data; 163*70afdab9SFrank Li unsigned long flags; 164*70afdab9SFrank Li int pos, err = 0; 165*70afdab9SFrank Li 166*70afdab9SFrank Li WARN_ON(nr_irqs != 1); 167*70afdab9SFrank Li 168*70afdab9SFrank Li raw_spin_lock_irqsave(&msi_data->lock, flags); 169*70afdab9SFrank Li pos = find_first_zero_bit(&msi_data->used, IMX_MU_CHANS); 170*70afdab9SFrank Li if (pos < IMX_MU_CHANS) 171*70afdab9SFrank Li __set_bit(pos, &msi_data->used); 172*70afdab9SFrank Li else 173*70afdab9SFrank Li err = -ENOSPC; 174*70afdab9SFrank Li raw_spin_unlock_irqrestore(&msi_data->lock, flags); 175*70afdab9SFrank Li 176*70afdab9SFrank Li if (err) 177*70afdab9SFrank Li return err; 178*70afdab9SFrank Li 179*70afdab9SFrank Li irq_domain_set_info(domain, virq, pos, 180*70afdab9SFrank Li &imx_mu_msi_parent_chip, msi_data, 181*70afdab9SFrank Li handle_edge_irq, NULL, NULL); 182*70afdab9SFrank Li return 0; 183*70afdab9SFrank Li } 184*70afdab9SFrank Li 185*70afdab9SFrank Li static void imx_mu_msi_domain_irq_free(struct irq_domain *domain, 186*70afdab9SFrank Li unsigned int virq, unsigned int nr_irqs) 187*70afdab9SFrank Li { 188*70afdab9SFrank Li struct irq_data *d = irq_domain_get_irq_data(domain, virq); 189*70afdab9SFrank Li struct imx_mu_msi *msi_data = irq_data_get_irq_chip_data(d); 190*70afdab9SFrank Li unsigned long flags; 191*70afdab9SFrank Li 192*70afdab9SFrank Li raw_spin_lock_irqsave(&msi_data->lock, flags); 193*70afdab9SFrank Li __clear_bit(d->hwirq, &msi_data->used); 194*70afdab9SFrank Li raw_spin_unlock_irqrestore(&msi_data->lock, flags); 195*70afdab9SFrank Li } 196*70afdab9SFrank Li 197*70afdab9SFrank Li static const struct irq_domain_ops imx_mu_msi_domain_ops = { 198*70afdab9SFrank Li .alloc = imx_mu_msi_domain_irq_alloc, 199*70afdab9SFrank Li .free = imx_mu_msi_domain_irq_free, 200*70afdab9SFrank Li }; 201*70afdab9SFrank Li 202*70afdab9SFrank Li static void imx_mu_msi_irq_handler(struct irq_desc *desc) 203*70afdab9SFrank Li { 204*70afdab9SFrank Li struct imx_mu_msi *msi_data = irq_desc_get_handler_data(desc); 205*70afdab9SFrank Li struct irq_chip *chip = irq_desc_get_chip(desc); 206*70afdab9SFrank Li u32 status; 207*70afdab9SFrank Li int i; 208*70afdab9SFrank Li 209*70afdab9SFrank Li status = imx_mu_read(msi_data, msi_data->cfg->xSR[IMX_MU_RSR]); 210*70afdab9SFrank Li 211*70afdab9SFrank Li chained_irq_enter(chip, desc); 212*70afdab9SFrank Li for (i = 0; i < IMX_MU_CHANS; i++) { 213*70afdab9SFrank Li if (status & IMX_MU_xSR_RFn(msi_data, i)) 214*70afdab9SFrank Li generic_handle_domain_irq(msi_data->msi_domain, i); 215*70afdab9SFrank Li } 216*70afdab9SFrank Li chained_irq_exit(chip, desc); 217*70afdab9SFrank Li } 218*70afdab9SFrank Li 219*70afdab9SFrank Li static int imx_mu_msi_domains_init(struct imx_mu_msi *msi_data, struct device *dev) 220*70afdab9SFrank Li { 221*70afdab9SFrank Li struct fwnode_handle *fwnodes = dev_fwnode(dev); 222*70afdab9SFrank Li struct irq_domain *parent; 223*70afdab9SFrank Li 224*70afdab9SFrank Li /* Initialize MSI domain parent */ 225*70afdab9SFrank Li parent = irq_domain_create_linear(fwnodes, 226*70afdab9SFrank Li IMX_MU_CHANS, 227*70afdab9SFrank Li &imx_mu_msi_domain_ops, 228*70afdab9SFrank Li msi_data); 229*70afdab9SFrank Li if (!parent) { 230*70afdab9SFrank Li dev_err(dev, "failed to create IRQ domain\n"); 231*70afdab9SFrank Li return -ENOMEM; 232*70afdab9SFrank Li } 233*70afdab9SFrank Li 234*70afdab9SFrank Li irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); 235*70afdab9SFrank Li 236*70afdab9SFrank Li msi_data->msi_domain = platform_msi_create_irq_domain(fwnodes, 237*70afdab9SFrank Li &imx_mu_msi_domain_info, 238*70afdab9SFrank Li parent); 239*70afdab9SFrank Li 240*70afdab9SFrank Li if (!msi_data->msi_domain) { 241*70afdab9SFrank Li dev_err(dev, "failed to create MSI domain\n"); 242*70afdab9SFrank Li irq_domain_remove(parent); 243*70afdab9SFrank Li return -ENOMEM; 244*70afdab9SFrank Li } 245*70afdab9SFrank Li 246*70afdab9SFrank Li irq_domain_set_pm_device(msi_data->msi_domain, dev); 247*70afdab9SFrank Li 248*70afdab9SFrank Li return 0; 249*70afdab9SFrank Li } 250*70afdab9SFrank Li 251*70afdab9SFrank Li /* Register offset of different version MU IP */ 252*70afdab9SFrank Li static const struct imx_mu_dcfg imx_mu_cfg_imx6sx = { 253*70afdab9SFrank Li .type = 0, 254*70afdab9SFrank Li .xTR = 0x0, 255*70afdab9SFrank Li .xRR = 0x10, 256*70afdab9SFrank Li .xSR = { 257*70afdab9SFrank Li [IMX_MU_SR] = 0x20, 258*70afdab9SFrank Li [IMX_MU_GSR] = 0x20, 259*70afdab9SFrank Li [IMX_MU_TSR] = 0x20, 260*70afdab9SFrank Li [IMX_MU_RSR] = 0x20, 261*70afdab9SFrank Li }, 262*70afdab9SFrank Li .xCR = { 263*70afdab9SFrank Li [IMX_MU_GIER] = 0x24, 264*70afdab9SFrank Li [IMX_MU_GCR] = 0x24, 265*70afdab9SFrank Li [IMX_MU_TCR] = 0x24, 266*70afdab9SFrank Li [IMX_MU_RCR] = 0x24, 267*70afdab9SFrank Li }, 268*70afdab9SFrank Li }; 269*70afdab9SFrank Li 270*70afdab9SFrank Li static const struct imx_mu_dcfg imx_mu_cfg_imx7ulp = { 271*70afdab9SFrank Li .type = 0, 272*70afdab9SFrank Li .xTR = 0x20, 273*70afdab9SFrank Li .xRR = 0x40, 274*70afdab9SFrank Li .xSR = { 275*70afdab9SFrank Li [IMX_MU_SR] = 0x60, 276*70afdab9SFrank Li [IMX_MU_GSR] = 0x60, 277*70afdab9SFrank Li [IMX_MU_TSR] = 0x60, 278*70afdab9SFrank Li [IMX_MU_RSR] = 0x60, 279*70afdab9SFrank Li }, 280*70afdab9SFrank Li .xCR = { 281*70afdab9SFrank Li [IMX_MU_GIER] = 0x64, 282*70afdab9SFrank Li [IMX_MU_GCR] = 0x64, 283*70afdab9SFrank Li [IMX_MU_TCR] = 0x64, 284*70afdab9SFrank Li [IMX_MU_RCR] = 0x64, 285*70afdab9SFrank Li }, 286*70afdab9SFrank Li }; 287*70afdab9SFrank Li 288*70afdab9SFrank Li static const struct imx_mu_dcfg imx_mu_cfg_imx8ulp = { 289*70afdab9SFrank Li .type = IMX_MU_V2, 290*70afdab9SFrank Li .xTR = 0x200, 291*70afdab9SFrank Li .xRR = 0x280, 292*70afdab9SFrank Li .xSR = { 293*70afdab9SFrank Li [IMX_MU_SR] = 0xC, 294*70afdab9SFrank Li [IMX_MU_GSR] = 0x118, 295*70afdab9SFrank Li [IMX_MU_GSR] = 0x124, 296*70afdab9SFrank Li [IMX_MU_RSR] = 0x12C, 297*70afdab9SFrank Li }, 298*70afdab9SFrank Li .xCR = { 299*70afdab9SFrank Li [IMX_MU_GIER] = 0x110, 300*70afdab9SFrank Li [IMX_MU_GCR] = 0x114, 301*70afdab9SFrank Li [IMX_MU_TCR] = 0x120, 302*70afdab9SFrank Li [IMX_MU_RCR] = 0x128 303*70afdab9SFrank Li }, 304*70afdab9SFrank Li }; 305*70afdab9SFrank Li 306*70afdab9SFrank Li static int __init imx_mu_of_init(struct device_node *dn, 307*70afdab9SFrank Li struct device_node *parent, 308*70afdab9SFrank Li const struct imx_mu_dcfg *cfg) 309*70afdab9SFrank Li { 310*70afdab9SFrank Li struct platform_device *pdev = of_find_device_by_node(dn); 311*70afdab9SFrank Li struct device_link *pd_link_a; 312*70afdab9SFrank Li struct device_link *pd_link_b; 313*70afdab9SFrank Li struct imx_mu_msi *msi_data; 314*70afdab9SFrank Li struct resource *res; 315*70afdab9SFrank Li struct device *pd_a; 316*70afdab9SFrank Li struct device *pd_b; 317*70afdab9SFrank Li struct device *dev; 318*70afdab9SFrank Li int ret; 319*70afdab9SFrank Li int irq; 320*70afdab9SFrank Li 321*70afdab9SFrank Li dev = &pdev->dev; 322*70afdab9SFrank Li 323*70afdab9SFrank Li msi_data = devm_kzalloc(&pdev->dev, sizeof(*msi_data), GFP_KERNEL); 324*70afdab9SFrank Li if (!msi_data) 325*70afdab9SFrank Li return -ENOMEM; 326*70afdab9SFrank Li 327*70afdab9SFrank Li msi_data->cfg = cfg; 328*70afdab9SFrank Li 329*70afdab9SFrank Li msi_data->regs = devm_platform_ioremap_resource_byname(pdev, "processor-a-side"); 330*70afdab9SFrank Li if (IS_ERR(msi_data->regs)) { 331*70afdab9SFrank Li dev_err(&pdev->dev, "failed to initialize 'regs'\n"); 332*70afdab9SFrank Li return PTR_ERR(msi_data->regs); 333*70afdab9SFrank Li } 334*70afdab9SFrank Li 335*70afdab9SFrank Li res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "processor-b-side"); 336*70afdab9SFrank Li if (!res) 337*70afdab9SFrank Li return -EIO; 338*70afdab9SFrank Li 339*70afdab9SFrank Li msi_data->msiir_addr = res->start + msi_data->cfg->xTR; 340*70afdab9SFrank Li 341*70afdab9SFrank Li irq = platform_get_irq(pdev, 0); 342*70afdab9SFrank Li if (irq <= 0) 343*70afdab9SFrank Li return -ENODEV; 344*70afdab9SFrank Li 345*70afdab9SFrank Li platform_set_drvdata(pdev, msi_data); 346*70afdab9SFrank Li 347*70afdab9SFrank Li msi_data->clk = devm_clk_get(dev, NULL); 348*70afdab9SFrank Li if (IS_ERR(msi_data->clk)) 349*70afdab9SFrank Li return PTR_ERR(msi_data->clk); 350*70afdab9SFrank Li 351*70afdab9SFrank Li pd_a = dev_pm_domain_attach_by_name(dev, "processor-a-side"); 352*70afdab9SFrank Li if (IS_ERR(pd_a)) 353*70afdab9SFrank Li return PTR_ERR(pd_a); 354*70afdab9SFrank Li 355*70afdab9SFrank Li pd_b = dev_pm_domain_attach_by_name(dev, "processor-b-side"); 356*70afdab9SFrank Li if (IS_ERR(pd_b)) 357*70afdab9SFrank Li return PTR_ERR(pd_b); 358*70afdab9SFrank Li 359*70afdab9SFrank Li pd_link_a = device_link_add(dev, pd_a, 360*70afdab9SFrank Li DL_FLAG_STATELESS | 361*70afdab9SFrank Li DL_FLAG_PM_RUNTIME | 362*70afdab9SFrank Li DL_FLAG_RPM_ACTIVE); 363*70afdab9SFrank Li 364*70afdab9SFrank Li if (!pd_link_a) { 365*70afdab9SFrank Li dev_err(dev, "Failed to add device_link to mu a.\n"); 366*70afdab9SFrank Li goto err_pd_a; 367*70afdab9SFrank Li } 368*70afdab9SFrank Li 369*70afdab9SFrank Li pd_link_b = device_link_add(dev, pd_b, 370*70afdab9SFrank Li DL_FLAG_STATELESS | 371*70afdab9SFrank Li DL_FLAG_PM_RUNTIME | 372*70afdab9SFrank Li DL_FLAG_RPM_ACTIVE); 373*70afdab9SFrank Li 374*70afdab9SFrank Li 375*70afdab9SFrank Li if (!pd_link_b) { 376*70afdab9SFrank Li dev_err(dev, "Failed to add device_link to mu a.\n"); 377*70afdab9SFrank Li goto err_pd_b; 378*70afdab9SFrank Li } 379*70afdab9SFrank Li 380*70afdab9SFrank Li ret = imx_mu_msi_domains_init(msi_data, dev); 381*70afdab9SFrank Li if (ret) 382*70afdab9SFrank Li goto err_dm_init; 383*70afdab9SFrank Li 384*70afdab9SFrank Li pm_runtime_enable(dev); 385*70afdab9SFrank Li 386*70afdab9SFrank Li irq_set_chained_handler_and_data(irq, 387*70afdab9SFrank Li imx_mu_msi_irq_handler, 388*70afdab9SFrank Li msi_data); 389*70afdab9SFrank Li 390*70afdab9SFrank Li return 0; 391*70afdab9SFrank Li 392*70afdab9SFrank Li err_dm_init: 393*70afdab9SFrank Li device_link_remove(dev, pd_b); 394*70afdab9SFrank Li err_pd_b: 395*70afdab9SFrank Li device_link_remove(dev, pd_a); 396*70afdab9SFrank Li err_pd_a: 397*70afdab9SFrank Li return -EINVAL; 398*70afdab9SFrank Li } 399*70afdab9SFrank Li 400*70afdab9SFrank Li static int __maybe_unused imx_mu_runtime_suspend(struct device *dev) 401*70afdab9SFrank Li { 402*70afdab9SFrank Li struct imx_mu_msi *priv = dev_get_drvdata(dev); 403*70afdab9SFrank Li 404*70afdab9SFrank Li clk_disable_unprepare(priv->clk); 405*70afdab9SFrank Li 406*70afdab9SFrank Li return 0; 407*70afdab9SFrank Li } 408*70afdab9SFrank Li 409*70afdab9SFrank Li static int __maybe_unused imx_mu_runtime_resume(struct device *dev) 410*70afdab9SFrank Li { 411*70afdab9SFrank Li struct imx_mu_msi *priv = dev_get_drvdata(dev); 412*70afdab9SFrank Li int ret; 413*70afdab9SFrank Li 414*70afdab9SFrank Li ret = clk_prepare_enable(priv->clk); 415*70afdab9SFrank Li if (ret) 416*70afdab9SFrank Li dev_err(dev, "failed to enable clock\n"); 417*70afdab9SFrank Li 418*70afdab9SFrank Li return ret; 419*70afdab9SFrank Li } 420*70afdab9SFrank Li 421*70afdab9SFrank Li static const struct dev_pm_ops imx_mu_pm_ops = { 422*70afdab9SFrank Li SET_RUNTIME_PM_OPS(imx_mu_runtime_suspend, 423*70afdab9SFrank Li imx_mu_runtime_resume, NULL) 424*70afdab9SFrank Li }; 425*70afdab9SFrank Li 426*70afdab9SFrank Li static int __init imx_mu_imx7ulp_of_init(struct device_node *dn, 427*70afdab9SFrank Li struct device_node *parent) 428*70afdab9SFrank Li { 429*70afdab9SFrank Li return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx7ulp); 430*70afdab9SFrank Li } 431*70afdab9SFrank Li 432*70afdab9SFrank Li static int __init imx_mu_imx6sx_of_init(struct device_node *dn, 433*70afdab9SFrank Li struct device_node *parent) 434*70afdab9SFrank Li { 435*70afdab9SFrank Li return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx6sx); 436*70afdab9SFrank Li } 437*70afdab9SFrank Li 438*70afdab9SFrank Li static int __init imx_mu_imx8ulp_of_init(struct device_node *dn, 439*70afdab9SFrank Li struct device_node *parent) 440*70afdab9SFrank Li { 441*70afdab9SFrank Li return imx_mu_of_init(dn, parent, &imx_mu_cfg_imx8ulp); 442*70afdab9SFrank Li } 443*70afdab9SFrank Li 444*70afdab9SFrank Li IRQCHIP_PLATFORM_DRIVER_BEGIN(imx_mu_msi) 445*70afdab9SFrank Li IRQCHIP_MATCH("fsl,imx7ulp-mu-msi", imx_mu_imx7ulp_of_init) 446*70afdab9SFrank Li IRQCHIP_MATCH("fsl,imx6sx-mu-msi", imx_mu_imx6sx_of_init) 447*70afdab9SFrank Li IRQCHIP_MATCH("fsl,imx8ulp-mu-msi", imx_mu_imx8ulp_of_init) 448*70afdab9SFrank Li IRQCHIP_PLATFORM_DRIVER_END(imx_mu_msi, .pm = &imx_mu_pm_ops) 449*70afdab9SFrank Li 450*70afdab9SFrank Li 451*70afdab9SFrank Li MODULE_AUTHOR("Frank Li <Frank.Li@nxp.com>"); 452*70afdab9SFrank Li MODULE_DESCRIPTION("Freescale MU MSI controller driver"); 453*70afdab9SFrank Li MODULE_LICENSE("GPL"); 454