12fbb1396SJoakim Zhang // SPDX-License-Identifier: GPL-2.0
22fbb1396SJoakim Zhang // Copyright 2017 NXP
32fbb1396SJoakim Zhang
42fbb1396SJoakim Zhang /* INTMUX Block Diagram
52fbb1396SJoakim Zhang *
62fbb1396SJoakim Zhang * ________________
72fbb1396SJoakim Zhang * interrupt source # 0 +---->| |
82fbb1396SJoakim Zhang * | | |
92fbb1396SJoakim Zhang * interrupt source # 1 +++-->| |
102fbb1396SJoakim Zhang * ... | | | channel # 0 |--------->interrupt out # 0
112fbb1396SJoakim Zhang * ... | | | |
122fbb1396SJoakim Zhang * ... | | | |
132fbb1396SJoakim Zhang * interrupt source # X-1 +++-->|________________|
142fbb1396SJoakim Zhang * | | |
152fbb1396SJoakim Zhang * | | |
162fbb1396SJoakim Zhang * | | | ________________
172fbb1396SJoakim Zhang * +---->| |
182fbb1396SJoakim Zhang * | | | | |
192fbb1396SJoakim Zhang * | +-->| |
202fbb1396SJoakim Zhang * | | | | channel # 1 |--------->interrupt out # 1
212fbb1396SJoakim Zhang * | | +>| |
222fbb1396SJoakim Zhang * | | | | |
232fbb1396SJoakim Zhang * | | | |________________|
242fbb1396SJoakim Zhang * | | |
252fbb1396SJoakim Zhang * | | |
262fbb1396SJoakim Zhang * | | | ...
272fbb1396SJoakim Zhang * | | | ...
282fbb1396SJoakim Zhang * | | |
292fbb1396SJoakim Zhang * | | | ________________
302fbb1396SJoakim Zhang * +---->| |
312fbb1396SJoakim Zhang * | | | |
322fbb1396SJoakim Zhang * +-->| |
332fbb1396SJoakim Zhang * | | channel # N |--------->interrupt out # N
342fbb1396SJoakim Zhang * +>| |
352fbb1396SJoakim Zhang * | |
362fbb1396SJoakim Zhang * |________________|
372fbb1396SJoakim Zhang *
382fbb1396SJoakim Zhang *
392fbb1396SJoakim Zhang * N: Interrupt Channel Instance Number (N=7)
402fbb1396SJoakim Zhang * X: Interrupt Source Number for each channel (X=32)
412fbb1396SJoakim Zhang *
422fbb1396SJoakim Zhang * The INTMUX interrupt multiplexer has 8 channels, each channel receives 32
432fbb1396SJoakim Zhang * interrupt sources and generates 1 interrupt output.
442fbb1396SJoakim Zhang *
452fbb1396SJoakim Zhang */
462fbb1396SJoakim Zhang
472fbb1396SJoakim Zhang #include <linux/clk.h>
482fbb1396SJoakim Zhang #include <linux/interrupt.h>
492fbb1396SJoakim Zhang #include <linux/irq.h>
502fbb1396SJoakim Zhang #include <linux/irqchip/chained_irq.h>
512fbb1396SJoakim Zhang #include <linux/irqdomain.h>
522fbb1396SJoakim Zhang #include <linux/kernel.h>
53*ee076750SRob Herring #include <linux/mod_devicetable.h>
542fbb1396SJoakim Zhang #include <linux/of_irq.h>
55*ee076750SRob Herring #include <linux/platform_device.h>
562fbb1396SJoakim Zhang #include <linux/spinlock.h>
57bb403111SJoakim Zhang #include <linux/pm_runtime.h>
582fbb1396SJoakim Zhang
592fbb1396SJoakim Zhang #define CHANIER(n) (0x10 + (0x40 * n))
602fbb1396SJoakim Zhang #define CHANIPR(n) (0x20 + (0x40 * n))
612fbb1396SJoakim Zhang
622fbb1396SJoakim Zhang #define CHAN_MAX_NUM 0x8
632fbb1396SJoakim Zhang
642fbb1396SJoakim Zhang struct intmux_irqchip_data {
65bb403111SJoakim Zhang u32 saved_reg;
662fbb1396SJoakim Zhang int chanidx;
672fbb1396SJoakim Zhang int irq;
682fbb1396SJoakim Zhang struct irq_domain *domain;
692fbb1396SJoakim Zhang };
702fbb1396SJoakim Zhang
712fbb1396SJoakim Zhang struct intmux_data {
722fbb1396SJoakim Zhang raw_spinlock_t lock;
732fbb1396SJoakim Zhang void __iomem *regs;
742fbb1396SJoakim Zhang struct clk *ipg_clk;
752fbb1396SJoakim Zhang int channum;
762fbb1396SJoakim Zhang struct intmux_irqchip_data irqchip_data[];
772fbb1396SJoakim Zhang };
782fbb1396SJoakim Zhang
imx_intmux_irq_mask(struct irq_data * d)792fbb1396SJoakim Zhang static void imx_intmux_irq_mask(struct irq_data *d)
802fbb1396SJoakim Zhang {
812fbb1396SJoakim Zhang struct intmux_irqchip_data *irqchip_data = d->chip_data;
822fbb1396SJoakim Zhang int idx = irqchip_data->chanidx;
832fbb1396SJoakim Zhang struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
842fbb1396SJoakim Zhang irqchip_data[idx]);
852fbb1396SJoakim Zhang unsigned long flags;
862fbb1396SJoakim Zhang void __iomem *reg;
872fbb1396SJoakim Zhang u32 val;
882fbb1396SJoakim Zhang
892fbb1396SJoakim Zhang raw_spin_lock_irqsave(&data->lock, flags);
902fbb1396SJoakim Zhang reg = data->regs + CHANIER(idx);
912fbb1396SJoakim Zhang val = readl_relaxed(reg);
922fbb1396SJoakim Zhang /* disable the interrupt source of this channel */
932fbb1396SJoakim Zhang val &= ~BIT(d->hwirq);
942fbb1396SJoakim Zhang writel_relaxed(val, reg);
952fbb1396SJoakim Zhang raw_spin_unlock_irqrestore(&data->lock, flags);
962fbb1396SJoakim Zhang }
972fbb1396SJoakim Zhang
imx_intmux_irq_unmask(struct irq_data * d)982fbb1396SJoakim Zhang static void imx_intmux_irq_unmask(struct irq_data *d)
992fbb1396SJoakim Zhang {
1002fbb1396SJoakim Zhang struct intmux_irqchip_data *irqchip_data = d->chip_data;
1012fbb1396SJoakim Zhang int idx = irqchip_data->chanidx;
1022fbb1396SJoakim Zhang struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
1032fbb1396SJoakim Zhang irqchip_data[idx]);
1042fbb1396SJoakim Zhang unsigned long flags;
1052fbb1396SJoakim Zhang void __iomem *reg;
1062fbb1396SJoakim Zhang u32 val;
1072fbb1396SJoakim Zhang
1082fbb1396SJoakim Zhang raw_spin_lock_irqsave(&data->lock, flags);
1092fbb1396SJoakim Zhang reg = data->regs + CHANIER(idx);
1102fbb1396SJoakim Zhang val = readl_relaxed(reg);
1112fbb1396SJoakim Zhang /* enable the interrupt source of this channel */
1122fbb1396SJoakim Zhang val |= BIT(d->hwirq);
1132fbb1396SJoakim Zhang writel_relaxed(val, reg);
1142fbb1396SJoakim Zhang raw_spin_unlock_irqrestore(&data->lock, flags);
1152fbb1396SJoakim Zhang }
1162fbb1396SJoakim Zhang
117fb140b9cSMarc Zyngier static struct irq_chip imx_intmux_irq_chip __ro_after_init = {
1182fbb1396SJoakim Zhang .name = "intmux",
1192fbb1396SJoakim Zhang .irq_mask = imx_intmux_irq_mask,
1202fbb1396SJoakim Zhang .irq_unmask = imx_intmux_irq_unmask,
1212fbb1396SJoakim Zhang };
1222fbb1396SJoakim Zhang
imx_intmux_irq_map(struct irq_domain * h,unsigned int irq,irq_hw_number_t hwirq)1232fbb1396SJoakim Zhang static int imx_intmux_irq_map(struct irq_domain *h, unsigned int irq,
1242fbb1396SJoakim Zhang irq_hw_number_t hwirq)
1252fbb1396SJoakim Zhang {
126bb403111SJoakim Zhang struct intmux_irqchip_data *data = h->host_data;
127bb403111SJoakim Zhang
128bb403111SJoakim Zhang irq_set_chip_data(irq, data);
129fb140b9cSMarc Zyngier irq_set_chip_and_handler(irq, &imx_intmux_irq_chip, handle_level_irq);
1302fbb1396SJoakim Zhang
1312fbb1396SJoakim Zhang return 0;
1322fbb1396SJoakim Zhang }
1332fbb1396SJoakim Zhang
imx_intmux_irq_xlate(struct irq_domain * d,struct device_node * node,const u32 * intspec,unsigned int intsize,unsigned long * out_hwirq,unsigned int * out_type)1342fbb1396SJoakim Zhang static int imx_intmux_irq_xlate(struct irq_domain *d, struct device_node *node,
1352fbb1396SJoakim Zhang const u32 *intspec, unsigned int intsize,
1362fbb1396SJoakim Zhang unsigned long *out_hwirq, unsigned int *out_type)
1372fbb1396SJoakim Zhang {
1382fbb1396SJoakim Zhang struct intmux_irqchip_data *irqchip_data = d->host_data;
1392fbb1396SJoakim Zhang int idx = irqchip_data->chanidx;
1402fbb1396SJoakim Zhang struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
1412fbb1396SJoakim Zhang irqchip_data[idx]);
1422fbb1396SJoakim Zhang
1432fbb1396SJoakim Zhang /*
1442fbb1396SJoakim Zhang * two cells needed in interrupt specifier:
1452fbb1396SJoakim Zhang * the 1st cell: hw interrupt number
1462fbb1396SJoakim Zhang * the 2nd cell: channel index
1472fbb1396SJoakim Zhang */
1482fbb1396SJoakim Zhang if (WARN_ON(intsize != 2))
1492fbb1396SJoakim Zhang return -EINVAL;
1502fbb1396SJoakim Zhang
1512fbb1396SJoakim Zhang if (WARN_ON(intspec[1] >= data->channum))
1522fbb1396SJoakim Zhang return -EINVAL;
1532fbb1396SJoakim Zhang
1542fbb1396SJoakim Zhang *out_hwirq = intspec[0];
1552fbb1396SJoakim Zhang *out_type = IRQ_TYPE_LEVEL_HIGH;
1562fbb1396SJoakim Zhang
1572fbb1396SJoakim Zhang return 0;
1582fbb1396SJoakim Zhang }
1592fbb1396SJoakim Zhang
imx_intmux_irq_select(struct irq_domain * d,struct irq_fwspec * fwspec,enum irq_domain_bus_token bus_token)1602fbb1396SJoakim Zhang static int imx_intmux_irq_select(struct irq_domain *d, struct irq_fwspec *fwspec,
1612fbb1396SJoakim Zhang enum irq_domain_bus_token bus_token)
1622fbb1396SJoakim Zhang {
1632fbb1396SJoakim Zhang struct intmux_irqchip_data *irqchip_data = d->host_data;
1642fbb1396SJoakim Zhang
1652fbb1396SJoakim Zhang /* Not for us */
1662fbb1396SJoakim Zhang if (fwspec->fwnode != d->fwnode)
1672fbb1396SJoakim Zhang return false;
1682fbb1396SJoakim Zhang
1692fbb1396SJoakim Zhang return irqchip_data->chanidx == fwspec->param[1];
1702fbb1396SJoakim Zhang }
1712fbb1396SJoakim Zhang
1722fbb1396SJoakim Zhang static const struct irq_domain_ops imx_intmux_domain_ops = {
1732fbb1396SJoakim Zhang .map = imx_intmux_irq_map,
1742fbb1396SJoakim Zhang .xlate = imx_intmux_irq_xlate,
1752fbb1396SJoakim Zhang .select = imx_intmux_irq_select,
1762fbb1396SJoakim Zhang };
1772fbb1396SJoakim Zhang
imx_intmux_irq_handler(struct irq_desc * desc)1782fbb1396SJoakim Zhang static void imx_intmux_irq_handler(struct irq_desc *desc)
1792fbb1396SJoakim Zhang {
1802fbb1396SJoakim Zhang struct intmux_irqchip_data *irqchip_data = irq_desc_get_handler_data(desc);
1812fbb1396SJoakim Zhang int idx = irqchip_data->chanidx;
1822fbb1396SJoakim Zhang struct intmux_data *data = container_of(irqchip_data, struct intmux_data,
1832fbb1396SJoakim Zhang irqchip_data[idx]);
1842fbb1396SJoakim Zhang unsigned long irqstat;
185046a6ee2SMarc Zyngier int pos;
1862fbb1396SJoakim Zhang
1872fbb1396SJoakim Zhang chained_irq_enter(irq_desc_get_chip(desc), desc);
1882fbb1396SJoakim Zhang
1892fbb1396SJoakim Zhang /* read the interrupt source pending status of this channel */
1902fbb1396SJoakim Zhang irqstat = readl_relaxed(data->regs + CHANIPR(idx));
1912fbb1396SJoakim Zhang
192046a6ee2SMarc Zyngier for_each_set_bit(pos, &irqstat, 32)
193046a6ee2SMarc Zyngier generic_handle_domain_irq(irqchip_data->domain, pos);
1942fbb1396SJoakim Zhang
1952fbb1396SJoakim Zhang chained_irq_exit(irq_desc_get_chip(desc), desc);
1962fbb1396SJoakim Zhang }
1972fbb1396SJoakim Zhang
imx_intmux_probe(struct platform_device * pdev)1982fbb1396SJoakim Zhang static int imx_intmux_probe(struct platform_device *pdev)
1992fbb1396SJoakim Zhang {
2002fbb1396SJoakim Zhang struct device_node *np = pdev->dev.of_node;
2012fbb1396SJoakim Zhang struct irq_domain *domain;
2022fbb1396SJoakim Zhang struct intmux_data *data;
2032fbb1396SJoakim Zhang int channum;
2042fbb1396SJoakim Zhang int i, ret;
2052fbb1396SJoakim Zhang
2062fbb1396SJoakim Zhang channum = platform_irq_count(pdev);
2072fbb1396SJoakim Zhang if (channum == -EPROBE_DEFER) {
2082fbb1396SJoakim Zhang return -EPROBE_DEFER;
2092fbb1396SJoakim Zhang } else if (channum > CHAN_MAX_NUM) {
2102fbb1396SJoakim Zhang dev_err(&pdev->dev, "supports up to %d multiplex channels\n",
2112fbb1396SJoakim Zhang CHAN_MAX_NUM);
2122fbb1396SJoakim Zhang return -EINVAL;
2132fbb1396SJoakim Zhang }
2142fbb1396SJoakim Zhang
2152f7a9bdaSGustavo A. R. Silva data = devm_kzalloc(&pdev->dev, struct_size(data, irqchip_data, channum), GFP_KERNEL);
2162fbb1396SJoakim Zhang if (!data)
2172fbb1396SJoakim Zhang return -ENOMEM;
2182fbb1396SJoakim Zhang
2192fbb1396SJoakim Zhang data->regs = devm_platform_ioremap_resource(pdev, 0);
2202fbb1396SJoakim Zhang if (IS_ERR(data->regs)) {
2212fbb1396SJoakim Zhang dev_err(&pdev->dev, "failed to initialize reg\n");
2222fbb1396SJoakim Zhang return PTR_ERR(data->regs);
2232fbb1396SJoakim Zhang }
2242fbb1396SJoakim Zhang
2252fbb1396SJoakim Zhang data->ipg_clk = devm_clk_get(&pdev->dev, "ipg");
226c201f432SAnson Huang if (IS_ERR(data->ipg_clk))
227c201f432SAnson Huang return dev_err_probe(&pdev->dev, PTR_ERR(data->ipg_clk),
228c201f432SAnson Huang "failed to get ipg clk\n");
2292fbb1396SJoakim Zhang
2302fbb1396SJoakim Zhang data->channum = channum;
2312fbb1396SJoakim Zhang raw_spin_lock_init(&data->lock);
2322fbb1396SJoakim Zhang
233bb403111SJoakim Zhang pm_runtime_get_noresume(&pdev->dev);
234bb403111SJoakim Zhang pm_runtime_set_active(&pdev->dev);
235bb403111SJoakim Zhang pm_runtime_enable(&pdev->dev);
236bb403111SJoakim Zhang
2372fbb1396SJoakim Zhang ret = clk_prepare_enable(data->ipg_clk);
2382fbb1396SJoakim Zhang if (ret) {
2392fbb1396SJoakim Zhang dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2402fbb1396SJoakim Zhang return ret;
2412fbb1396SJoakim Zhang }
2422fbb1396SJoakim Zhang
2432fbb1396SJoakim Zhang for (i = 0; i < channum; i++) {
2442fbb1396SJoakim Zhang data->irqchip_data[i].chanidx = i;
2452fbb1396SJoakim Zhang
2462fbb1396SJoakim Zhang data->irqchip_data[i].irq = irq_of_parse_and_map(np, i);
2472fbb1396SJoakim Zhang if (data->irqchip_data[i].irq <= 0) {
2482fbb1396SJoakim Zhang ret = -EINVAL;
2492fbb1396SJoakim Zhang dev_err(&pdev->dev, "failed to get irq\n");
2502fbb1396SJoakim Zhang goto out;
2512fbb1396SJoakim Zhang }
2522fbb1396SJoakim Zhang
2532fbb1396SJoakim Zhang domain = irq_domain_add_linear(np, 32, &imx_intmux_domain_ops,
2542fbb1396SJoakim Zhang &data->irqchip_data[i]);
2552fbb1396SJoakim Zhang if (!domain) {
2562fbb1396SJoakim Zhang ret = -ENOMEM;
2572fbb1396SJoakim Zhang dev_err(&pdev->dev, "failed to create IRQ domain\n");
2582fbb1396SJoakim Zhang goto out;
2592fbb1396SJoakim Zhang }
2602fbb1396SJoakim Zhang data->irqchip_data[i].domain = domain;
261fb140b9cSMarc Zyngier irq_domain_set_pm_device(domain, &pdev->dev);
2622fbb1396SJoakim Zhang
2632fbb1396SJoakim Zhang /* disable all interrupt sources of this channel firstly */
2642fbb1396SJoakim Zhang writel_relaxed(0, data->regs + CHANIER(i));
2652fbb1396SJoakim Zhang
2662fbb1396SJoakim Zhang irq_set_chained_handler_and_data(data->irqchip_data[i].irq,
2672fbb1396SJoakim Zhang imx_intmux_irq_handler,
2682fbb1396SJoakim Zhang &data->irqchip_data[i]);
2692fbb1396SJoakim Zhang }
2702fbb1396SJoakim Zhang
2712fbb1396SJoakim Zhang platform_set_drvdata(pdev, data);
2722fbb1396SJoakim Zhang
273bb403111SJoakim Zhang /*
274bb403111SJoakim Zhang * Let pm_runtime_put() disable clock.
275bb403111SJoakim Zhang * If CONFIG_PM is not enabled, the clock will stay powered.
276bb403111SJoakim Zhang */
277bb403111SJoakim Zhang pm_runtime_put(&pdev->dev);
278bb403111SJoakim Zhang
2792fbb1396SJoakim Zhang return 0;
2802fbb1396SJoakim Zhang out:
2812fbb1396SJoakim Zhang clk_disable_unprepare(data->ipg_clk);
2822fbb1396SJoakim Zhang return ret;
2832fbb1396SJoakim Zhang }
2842fbb1396SJoakim Zhang
imx_intmux_remove(struct platform_device * pdev)2852fbb1396SJoakim Zhang static int imx_intmux_remove(struct platform_device *pdev)
2862fbb1396SJoakim Zhang {
2872fbb1396SJoakim Zhang struct intmux_data *data = platform_get_drvdata(pdev);
2882fbb1396SJoakim Zhang int i;
2892fbb1396SJoakim Zhang
2902fbb1396SJoakim Zhang for (i = 0; i < data->channum; i++) {
2912fbb1396SJoakim Zhang /* disable all interrupt sources of this channel */
2922fbb1396SJoakim Zhang writel_relaxed(0, data->regs + CHANIER(i));
2932fbb1396SJoakim Zhang
2942fbb1396SJoakim Zhang irq_set_chained_handler_and_data(data->irqchip_data[i].irq,
2952fbb1396SJoakim Zhang NULL, NULL);
2962fbb1396SJoakim Zhang
2972fbb1396SJoakim Zhang irq_domain_remove(data->irqchip_data[i].domain);
2982fbb1396SJoakim Zhang }
2992fbb1396SJoakim Zhang
300bb403111SJoakim Zhang pm_runtime_disable(&pdev->dev);
301bb403111SJoakim Zhang
302bb403111SJoakim Zhang return 0;
303bb403111SJoakim Zhang }
304bb403111SJoakim Zhang
305bb403111SJoakim Zhang #ifdef CONFIG_PM
imx_intmux_runtime_suspend(struct device * dev)306bb403111SJoakim Zhang static int imx_intmux_runtime_suspend(struct device *dev)
307bb403111SJoakim Zhang {
308bb403111SJoakim Zhang struct intmux_data *data = dev_get_drvdata(dev);
3095b6570bbSWei Yongjun struct intmux_irqchip_data *irqchip_data;
310bb403111SJoakim Zhang int i;
311bb403111SJoakim Zhang
312bb403111SJoakim Zhang for (i = 0; i < data->channum; i++) {
3135b6570bbSWei Yongjun irqchip_data = &data->irqchip_data[i];
3145b6570bbSWei Yongjun irqchip_data->saved_reg = readl_relaxed(data->regs + CHANIER(i));
315bb403111SJoakim Zhang }
316bb403111SJoakim Zhang
3172fbb1396SJoakim Zhang clk_disable_unprepare(data->ipg_clk);
3182fbb1396SJoakim Zhang
3192fbb1396SJoakim Zhang return 0;
3202fbb1396SJoakim Zhang }
3212fbb1396SJoakim Zhang
imx_intmux_runtime_resume(struct device * dev)322bb403111SJoakim Zhang static int imx_intmux_runtime_resume(struct device *dev)
323bb403111SJoakim Zhang {
324bb403111SJoakim Zhang struct intmux_data *data = dev_get_drvdata(dev);
3255b6570bbSWei Yongjun struct intmux_irqchip_data *irqchip_data;
326bb403111SJoakim Zhang int ret, i;
327bb403111SJoakim Zhang
328bb403111SJoakim Zhang ret = clk_prepare_enable(data->ipg_clk);
329bb403111SJoakim Zhang if (ret) {
330bb403111SJoakim Zhang dev_err(dev, "failed to enable ipg clk: %d\n", ret);
331bb403111SJoakim Zhang return ret;
332bb403111SJoakim Zhang }
333bb403111SJoakim Zhang
334bb403111SJoakim Zhang for (i = 0; i < data->channum; i++) {
3355b6570bbSWei Yongjun irqchip_data = &data->irqchip_data[i];
3365b6570bbSWei Yongjun writel_relaxed(irqchip_data->saved_reg, data->regs + CHANIER(i));
337bb403111SJoakim Zhang }
338bb403111SJoakim Zhang
339bb403111SJoakim Zhang return 0;
340bb403111SJoakim Zhang }
341bb403111SJoakim Zhang #endif
342bb403111SJoakim Zhang
343bb403111SJoakim Zhang static const struct dev_pm_ops imx_intmux_pm_ops = {
344bb403111SJoakim Zhang SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
345bb403111SJoakim Zhang pm_runtime_force_resume)
346bb403111SJoakim Zhang SET_RUNTIME_PM_OPS(imx_intmux_runtime_suspend,
347bb403111SJoakim Zhang imx_intmux_runtime_resume, NULL)
348bb403111SJoakim Zhang };
349bb403111SJoakim Zhang
3502fbb1396SJoakim Zhang static const struct of_device_id imx_intmux_id[] = {
3512fbb1396SJoakim Zhang { .compatible = "fsl,imx-intmux", },
3522fbb1396SJoakim Zhang { /* sentinel */ },
3532fbb1396SJoakim Zhang };
3542fbb1396SJoakim Zhang
3552fbb1396SJoakim Zhang static struct platform_driver imx_intmux_driver = {
3562fbb1396SJoakim Zhang .driver = {
3572fbb1396SJoakim Zhang .name = "imx-intmux",
3582fbb1396SJoakim Zhang .of_match_table = imx_intmux_id,
359bb403111SJoakim Zhang .pm = &imx_intmux_pm_ops,
3602fbb1396SJoakim Zhang },
3612fbb1396SJoakim Zhang .probe = imx_intmux_probe,
3622fbb1396SJoakim Zhang .remove = imx_intmux_remove,
3632fbb1396SJoakim Zhang };
3642fbb1396SJoakim Zhang builtin_platform_driver(imx_intmux_driver);
365