1 /* 2 * Copyright (C) 2015 Freescale Semiconductor, Inc. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/of_address.h> 10 #include <linux/of_irq.h> 11 #include <linux/slab.h> 12 #include <linux/irqchip.h> 13 #include <linux/syscore_ops.h> 14 15 #define IMR_NUM 4 16 #define GPC_MAX_IRQS (IMR_NUM * 32) 17 18 #define GPC_IMR1_CORE0 0x30 19 #define GPC_IMR1_CORE1 0x40 20 21 struct gpcv2_irqchip_data { 22 struct raw_spinlock rlock; 23 void __iomem *gpc_base; 24 u32 wakeup_sources[IMR_NUM]; 25 u32 saved_irq_mask[IMR_NUM]; 26 u32 cpu2wakeup; 27 }; 28 29 static struct gpcv2_irqchip_data *imx_gpcv2_instance; 30 31 /* 32 * Interface for the low level wakeup code. 33 */ 34 u32 imx_gpcv2_get_wakeup_source(u32 **sources) 35 { 36 if (!imx_gpcv2_instance) 37 return 0; 38 39 if (sources) 40 *sources = imx_gpcv2_instance->wakeup_sources; 41 42 return IMR_NUM; 43 } 44 45 static int gpcv2_wakeup_source_save(void) 46 { 47 struct gpcv2_irqchip_data *cd; 48 void __iomem *reg; 49 int i; 50 51 cd = imx_gpcv2_instance; 52 if (!cd) 53 return 0; 54 55 for (i = 0; i < IMR_NUM; i++) { 56 reg = cd->gpc_base + cd->cpu2wakeup + i * 4; 57 cd->saved_irq_mask[i] = readl_relaxed(reg); 58 writel_relaxed(cd->wakeup_sources[i], reg); 59 } 60 61 return 0; 62 } 63 64 static void gpcv2_wakeup_source_restore(void) 65 { 66 struct gpcv2_irqchip_data *cd; 67 void __iomem *reg; 68 int i; 69 70 cd = imx_gpcv2_instance; 71 if (!cd) 72 return; 73 74 for (i = 0; i < IMR_NUM; i++) { 75 reg = cd->gpc_base + cd->cpu2wakeup + i * 4; 76 writel_relaxed(cd->saved_irq_mask[i], reg); 77 } 78 } 79 80 static struct syscore_ops imx_gpcv2_syscore_ops = { 81 .suspend = gpcv2_wakeup_source_save, 82 .resume = gpcv2_wakeup_source_restore, 83 }; 84 85 static int imx_gpcv2_irq_set_wake(struct irq_data *d, unsigned int on) 86 { 87 struct gpcv2_irqchip_data *cd = d->chip_data; 88 unsigned int idx = d->hwirq / 32; 89 unsigned long flags; 90 void __iomem *reg; 91 u32 mask, val; 92 93 raw_spin_lock_irqsave(&cd->rlock, flags); 94 reg = cd->gpc_base + cd->cpu2wakeup + idx * 4; 95 mask = 1 << d->hwirq % 32; 96 val = cd->wakeup_sources[idx]; 97 98 cd->wakeup_sources[idx] = on ? (val & ~mask) : (val | mask); 99 raw_spin_unlock_irqrestore(&cd->rlock, flags); 100 101 /* 102 * Do *not* call into the parent, as the GIC doesn't have any 103 * wake-up facility... 104 */ 105 106 return 0; 107 } 108 109 static void imx_gpcv2_irq_unmask(struct irq_data *d) 110 { 111 struct gpcv2_irqchip_data *cd = d->chip_data; 112 void __iomem *reg; 113 u32 val; 114 115 raw_spin_lock(&cd->rlock); 116 reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; 117 val = readl_relaxed(reg); 118 val &= ~(1 << d->hwirq % 32); 119 writel_relaxed(val, reg); 120 raw_spin_unlock(&cd->rlock); 121 122 irq_chip_unmask_parent(d); 123 } 124 125 static void imx_gpcv2_irq_mask(struct irq_data *d) 126 { 127 struct gpcv2_irqchip_data *cd = d->chip_data; 128 void __iomem *reg; 129 u32 val; 130 131 raw_spin_lock(&cd->rlock); 132 reg = cd->gpc_base + cd->cpu2wakeup + d->hwirq / 32 * 4; 133 val = readl_relaxed(reg); 134 val |= 1 << (d->hwirq % 32); 135 writel_relaxed(val, reg); 136 raw_spin_unlock(&cd->rlock); 137 138 irq_chip_mask_parent(d); 139 } 140 141 static struct irq_chip gpcv2_irqchip_data_chip = { 142 .name = "GPCv2", 143 .irq_eoi = irq_chip_eoi_parent, 144 .irq_mask = imx_gpcv2_irq_mask, 145 .irq_unmask = imx_gpcv2_irq_unmask, 146 .irq_set_wake = imx_gpcv2_irq_set_wake, 147 .irq_retrigger = irq_chip_retrigger_hierarchy, 148 #ifdef CONFIG_SMP 149 .irq_set_affinity = irq_chip_set_affinity_parent, 150 #endif 151 }; 152 153 static int imx_gpcv2_domain_xlate(struct irq_domain *domain, 154 struct device_node *controller, 155 const u32 *intspec, 156 unsigned int intsize, 157 unsigned long *out_hwirq, 158 unsigned int *out_type) 159 { 160 /* Shouldn't happen, really... */ 161 if (domain->of_node != controller) 162 return -EINVAL; 163 164 /* Not GIC compliant */ 165 if (intsize != 3) 166 return -EINVAL; 167 168 /* No PPI should point to this domain */ 169 if (intspec[0] != 0) 170 return -EINVAL; 171 172 *out_hwirq = intspec[1]; 173 *out_type = intspec[2]; 174 return 0; 175 } 176 177 static int imx_gpcv2_domain_alloc(struct irq_domain *domain, 178 unsigned int irq, unsigned int nr_irqs, 179 void *data) 180 { 181 struct of_phandle_args *args = data; 182 struct of_phandle_args parent_args; 183 irq_hw_number_t hwirq; 184 int i; 185 186 /* Not GIC compliant */ 187 if (args->args_count != 3) 188 return -EINVAL; 189 190 /* No PPI should point to this domain */ 191 if (args->args[0] != 0) 192 return -EINVAL; 193 194 /* Can't deal with this */ 195 hwirq = args->args[1]; 196 if (hwirq >= GPC_MAX_IRQS) 197 return -EINVAL; 198 199 for (i = 0; i < nr_irqs; i++) { 200 irq_domain_set_hwirq_and_chip(domain, irq + i, hwirq + i, 201 &gpcv2_irqchip_data_chip, domain->host_data); 202 } 203 204 parent_args = *args; 205 parent_args.np = domain->parent->of_node; 206 return irq_domain_alloc_irqs_parent(domain, irq, nr_irqs, &parent_args); 207 } 208 209 static struct irq_domain_ops gpcv2_irqchip_data_domain_ops = { 210 .xlate = imx_gpcv2_domain_xlate, 211 .alloc = imx_gpcv2_domain_alloc, 212 .free = irq_domain_free_irqs_common, 213 }; 214 215 static int __init imx_gpcv2_irqchip_init(struct device_node *node, 216 struct device_node *parent) 217 { 218 struct irq_domain *parent_domain, *domain; 219 struct gpcv2_irqchip_data *cd; 220 int i; 221 222 if (!parent) { 223 pr_err("%s: no parent, giving up\n", node->full_name); 224 return -ENODEV; 225 } 226 227 parent_domain = irq_find_host(parent); 228 if (!parent_domain) { 229 pr_err("%s: unable to get parent domain\n", node->full_name); 230 return -ENXIO; 231 } 232 233 cd = kzalloc(sizeof(struct gpcv2_irqchip_data), GFP_KERNEL); 234 if (!cd) { 235 pr_err("kzalloc failed!\n"); 236 return -ENOMEM; 237 } 238 239 cd->gpc_base = of_iomap(node, 0); 240 if (!cd->gpc_base) { 241 pr_err("fsl-gpcv2: unable to map gpc registers\n"); 242 kfree(cd); 243 return -ENOMEM; 244 } 245 246 domain = irq_domain_add_hierarchy(parent_domain, 0, GPC_MAX_IRQS, 247 node, &gpcv2_irqchip_data_domain_ops, cd); 248 if (!domain) { 249 iounmap(cd->gpc_base); 250 kfree(cd); 251 return -ENOMEM; 252 } 253 irq_set_default_host(domain); 254 255 /* Initially mask all interrupts */ 256 for (i = 0; i < IMR_NUM; i++) { 257 writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE0 + i * 4); 258 writel_relaxed(~0, cd->gpc_base + GPC_IMR1_CORE1 + i * 4); 259 cd->wakeup_sources[i] = ~0; 260 } 261 262 /* Let CORE0 as the default CPU to wake up by GPC */ 263 cd->cpu2wakeup = GPC_IMR1_CORE0; 264 265 /* 266 * Due to hardware design failure, need to make sure GPR 267 * interrupt(#32) is unmasked during RUN mode to avoid entering 268 * DSM by mistake. 269 */ 270 writel_relaxed(~0x1, cd->gpc_base + cd->cpu2wakeup); 271 272 imx_gpcv2_instance = cd; 273 register_syscore_ops(&imx_gpcv2_syscore_ops); 274 275 return 0; 276 } 277 278 IRQCHIP_DECLARE(imx_gpcv2, "fsl,imx7d-gpc", imx_gpcv2_irqchip_init); 279