1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Hisilicon HiP04 INTC 4 * 5 * Copyright (C) 2002-2014 ARM Limited. 6 * Copyright (c) 2013-2014 Hisilicon Ltd. 7 * Copyright (c) 2013-2014 Linaro Ltd. 8 * 9 * Interrupt architecture for the HIP04 INTC: 10 * 11 * o There is one Interrupt Distributor, which receives interrupts 12 * from system devices and sends them to the Interrupt Controllers. 13 * 14 * o There is one CPU Interface per CPU, which sends interrupts sent 15 * by the Distributor, and interrupts generated locally, to the 16 * associated CPU. The base address of the CPU interface is usually 17 * aliased so that the same address points to different chips depending 18 * on the CPU it is accessed from. 19 * 20 * Note that IRQs 0-31 are special - they are local to each CPU. 21 * As such, the enable set/clear, pending set/clear and active bit 22 * registers are banked per-cpu for these sources. 23 */ 24 25 #include <linux/init.h> 26 #include <linux/kernel.h> 27 #include <linux/err.h> 28 #include <linux/module.h> 29 #include <linux/list.h> 30 #include <linux/smp.h> 31 #include <linux/cpu.h> 32 #include <linux/cpu_pm.h> 33 #include <linux/cpumask.h> 34 #include <linux/io.h> 35 #include <linux/of.h> 36 #include <linux/of_address.h> 37 #include <linux/of_irq.h> 38 #include <linux/irqdomain.h> 39 #include <linux/interrupt.h> 40 #include <linux/slab.h> 41 #include <linux/irqchip.h> 42 #include <linux/irqchip/arm-gic.h> 43 44 #include <asm/irq.h> 45 #include <asm/exception.h> 46 #include <asm/smp_plat.h> 47 48 #include "irq-gic-common.h" 49 50 #define HIP04_MAX_IRQS 510 51 52 struct hip04_irq_data { 53 void __iomem *dist_base; 54 void __iomem *cpu_base; 55 struct irq_domain *domain; 56 unsigned int nr_irqs; 57 }; 58 59 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 60 61 /* 62 * The GIC mapping of CPU interfaces does not necessarily match 63 * the logical CPU numbering. Let's use a mapping as returned 64 * by the GIC itself. 65 */ 66 #define NR_HIP04_CPU_IF 16 67 static u16 hip04_cpu_map[NR_HIP04_CPU_IF] __read_mostly; 68 69 static struct hip04_irq_data hip04_data __read_mostly; 70 71 static inline void __iomem *hip04_dist_base(struct irq_data *d) 72 { 73 struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d); 74 return hip04_data->dist_base; 75 } 76 77 static inline void __iomem *hip04_cpu_base(struct irq_data *d) 78 { 79 struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d); 80 return hip04_data->cpu_base; 81 } 82 83 static inline unsigned int hip04_irq(struct irq_data *d) 84 { 85 return d->hwirq; 86 } 87 88 /* 89 * Routines to acknowledge, disable and enable interrupts 90 */ 91 static void hip04_mask_irq(struct irq_data *d) 92 { 93 u32 mask = 1 << (hip04_irq(d) % 32); 94 95 raw_spin_lock(&irq_controller_lock); 96 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR + 97 (hip04_irq(d) / 32) * 4); 98 raw_spin_unlock(&irq_controller_lock); 99 } 100 101 static void hip04_unmask_irq(struct irq_data *d) 102 { 103 u32 mask = 1 << (hip04_irq(d) % 32); 104 105 raw_spin_lock(&irq_controller_lock); 106 writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET + 107 (hip04_irq(d) / 32) * 4); 108 raw_spin_unlock(&irq_controller_lock); 109 } 110 111 static void hip04_eoi_irq(struct irq_data *d) 112 { 113 writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI); 114 } 115 116 static int hip04_irq_set_type(struct irq_data *d, unsigned int type) 117 { 118 void __iomem *base = hip04_dist_base(d); 119 unsigned int irq = hip04_irq(d); 120 int ret; 121 122 /* Interrupt configuration for SGIs can't be changed */ 123 if (irq < 16) 124 return -EINVAL; 125 126 /* SPIs have restrictions on the supported types */ 127 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 128 type != IRQ_TYPE_EDGE_RISING) 129 return -EINVAL; 130 131 raw_spin_lock(&irq_controller_lock); 132 133 ret = gic_configure_irq(irq, type, base, NULL); 134 135 raw_spin_unlock(&irq_controller_lock); 136 137 return ret; 138 } 139 140 #ifdef CONFIG_SMP 141 static int hip04_irq_set_affinity(struct irq_data *d, 142 const struct cpumask *mask_val, 143 bool force) 144 { 145 void __iomem *reg; 146 unsigned int cpu, shift = (hip04_irq(d) % 2) * 16; 147 u32 val, mask, bit; 148 149 if (!force) 150 cpu = cpumask_any_and(mask_val, cpu_online_mask); 151 else 152 cpu = cpumask_first(mask_val); 153 154 if (cpu >= NR_HIP04_CPU_IF || cpu >= nr_cpu_ids) 155 return -EINVAL; 156 157 raw_spin_lock(&irq_controller_lock); 158 reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3); 159 mask = 0xffff << shift; 160 bit = hip04_cpu_map[cpu] << shift; 161 val = readl_relaxed(reg) & ~mask; 162 writel_relaxed(val | bit, reg); 163 raw_spin_unlock(&irq_controller_lock); 164 165 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 166 167 return IRQ_SET_MASK_OK; 168 } 169 #endif 170 171 static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs) 172 { 173 u32 irqstat, irqnr; 174 void __iomem *cpu_base = hip04_data.cpu_base; 175 176 do { 177 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 178 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 179 180 if (likely(irqnr > 15 && irqnr <= HIP04_MAX_IRQS)) { 181 handle_domain_irq(hip04_data.domain, irqnr, regs); 182 continue; 183 } 184 if (irqnr < 16) { 185 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 186 #ifdef CONFIG_SMP 187 handle_IPI(irqnr, regs); 188 #endif 189 continue; 190 } 191 break; 192 } while (1); 193 } 194 195 static struct irq_chip hip04_irq_chip = { 196 .name = "HIP04 INTC", 197 .irq_mask = hip04_mask_irq, 198 .irq_unmask = hip04_unmask_irq, 199 .irq_eoi = hip04_eoi_irq, 200 .irq_set_type = hip04_irq_set_type, 201 #ifdef CONFIG_SMP 202 .irq_set_affinity = hip04_irq_set_affinity, 203 #endif 204 .flags = IRQCHIP_SET_TYPE_MASKED | 205 IRQCHIP_SKIP_SET_WAKE | 206 IRQCHIP_MASK_ON_SUSPEND, 207 }; 208 209 static u16 hip04_get_cpumask(struct hip04_irq_data *intc) 210 { 211 void __iomem *base = intc->dist_base; 212 u32 mask, i; 213 214 for (i = mask = 0; i < 32; i += 2) { 215 mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2); 216 mask |= mask >> 16; 217 if (mask) 218 break; 219 } 220 221 if (!mask) 222 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 223 224 return mask; 225 } 226 227 static void __init hip04_irq_dist_init(struct hip04_irq_data *intc) 228 { 229 unsigned int i; 230 u32 cpumask; 231 unsigned int nr_irqs = intc->nr_irqs; 232 void __iomem *base = intc->dist_base; 233 234 writel_relaxed(0, base + GIC_DIST_CTRL); 235 236 /* 237 * Set all global interrupts to this CPU only. 238 */ 239 cpumask = hip04_get_cpumask(intc); 240 cpumask |= cpumask << 16; 241 for (i = 32; i < nr_irqs; i += 2) 242 writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3)); 243 244 gic_dist_config(base, nr_irqs, NULL); 245 246 writel_relaxed(1, base + GIC_DIST_CTRL); 247 } 248 249 static void hip04_irq_cpu_init(struct hip04_irq_data *intc) 250 { 251 void __iomem *dist_base = intc->dist_base; 252 void __iomem *base = intc->cpu_base; 253 unsigned int cpu_mask, cpu = smp_processor_id(); 254 int i; 255 256 /* 257 * Get what the GIC says our CPU mask is. 258 */ 259 BUG_ON(cpu >= NR_HIP04_CPU_IF); 260 cpu_mask = hip04_get_cpumask(intc); 261 hip04_cpu_map[cpu] = cpu_mask; 262 263 /* 264 * Clear our mask from the other map entries in case they're 265 * still undefined. 266 */ 267 for (i = 0; i < NR_HIP04_CPU_IF; i++) 268 if (i != cpu) 269 hip04_cpu_map[i] &= ~cpu_mask; 270 271 gic_cpu_config(dist_base, NULL); 272 273 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); 274 writel_relaxed(1, base + GIC_CPU_CTRL); 275 } 276 277 #ifdef CONFIG_SMP 278 static void hip04_raise_softirq(const struct cpumask *mask, unsigned int irq) 279 { 280 int cpu; 281 unsigned long flags, map = 0; 282 283 raw_spin_lock_irqsave(&irq_controller_lock, flags); 284 285 /* Convert our logical CPU mask into a physical one. */ 286 for_each_cpu(cpu, mask) 287 map |= hip04_cpu_map[cpu]; 288 289 /* 290 * Ensure that stores to Normal memory are visible to the 291 * other CPUs before they observe us issuing the IPI. 292 */ 293 dmb(ishst); 294 295 /* this always happens on GIC0 */ 296 writel_relaxed(map << 8 | irq, hip04_data.dist_base + GIC_DIST_SOFTINT); 297 298 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 299 } 300 #endif 301 302 static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq, 303 irq_hw_number_t hw) 304 { 305 if (hw < 32) { 306 irq_set_percpu_devid(irq); 307 irq_set_chip_and_handler(irq, &hip04_irq_chip, 308 handle_percpu_devid_irq); 309 irq_set_status_flags(irq, IRQ_NOAUTOEN); 310 } else { 311 irq_set_chip_and_handler(irq, &hip04_irq_chip, 312 handle_fasteoi_irq); 313 irq_set_probe(irq); 314 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 315 } 316 irq_set_chip_data(irq, d->host_data); 317 return 0; 318 } 319 320 static int hip04_irq_domain_xlate(struct irq_domain *d, 321 struct device_node *controller, 322 const u32 *intspec, unsigned int intsize, 323 unsigned long *out_hwirq, 324 unsigned int *out_type) 325 { 326 unsigned long ret = 0; 327 328 if (irq_domain_get_of_node(d) != controller) 329 return -EINVAL; 330 if (intsize < 3) 331 return -EINVAL; 332 333 /* Get the interrupt number and add 16 to skip over SGIs */ 334 *out_hwirq = intspec[1] + 16; 335 336 /* For SPIs, we need to add 16 more to get the irq ID number */ 337 if (!intspec[0]) 338 *out_hwirq += 16; 339 340 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 341 342 return ret; 343 } 344 345 static int hip04_irq_starting_cpu(unsigned int cpu) 346 { 347 hip04_irq_cpu_init(&hip04_data); 348 return 0; 349 } 350 351 static const struct irq_domain_ops hip04_irq_domain_ops = { 352 .map = hip04_irq_domain_map, 353 .xlate = hip04_irq_domain_xlate, 354 }; 355 356 static int __init 357 hip04_of_init(struct device_node *node, struct device_node *parent) 358 { 359 irq_hw_number_t hwirq_base = 16; 360 int nr_irqs, irq_base, i; 361 362 if (WARN_ON(!node)) 363 return -ENODEV; 364 365 hip04_data.dist_base = of_iomap(node, 0); 366 WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n"); 367 368 hip04_data.cpu_base = of_iomap(node, 1); 369 WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n"); 370 371 /* 372 * Initialize the CPU interface map to all CPUs. 373 * It will be refined as each CPU probes its ID. 374 */ 375 for (i = 0; i < NR_HIP04_CPU_IF; i++) 376 hip04_cpu_map[i] = 0xffff; 377 378 /* 379 * Find out how many interrupts are supported. 380 * The HIP04 INTC only supports up to 510 interrupt sources. 381 */ 382 nr_irqs = readl_relaxed(hip04_data.dist_base + GIC_DIST_CTR) & 0x1f; 383 nr_irqs = (nr_irqs + 1) * 32; 384 if (nr_irqs > HIP04_MAX_IRQS) 385 nr_irqs = HIP04_MAX_IRQS; 386 hip04_data.nr_irqs = nr_irqs; 387 388 nr_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 389 390 irq_base = irq_alloc_descs(-1, hwirq_base, nr_irqs, numa_node_id()); 391 if (irq_base < 0) { 392 pr_err("failed to allocate IRQ numbers\n"); 393 return -EINVAL; 394 } 395 396 hip04_data.domain = irq_domain_add_legacy(node, nr_irqs, irq_base, 397 hwirq_base, 398 &hip04_irq_domain_ops, 399 &hip04_data); 400 401 if (WARN_ON(!hip04_data.domain)) 402 return -EINVAL; 403 404 #ifdef CONFIG_SMP 405 set_smp_cross_call(hip04_raise_softirq); 406 #endif 407 set_handle_irq(hip04_handle_irq); 408 409 hip04_irq_dist_init(&hip04_data); 410 cpuhp_setup_state(CPUHP_AP_IRQ_HIP04_STARTING, "irqchip/hip04:starting", 411 hip04_irq_starting_cpu, NULL); 412 return 0; 413 } 414 IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init); 415