xref: /openbmc/linux/drivers/irqchip/irq-hip04.c (revision 4949009e)
1 /*
2  * Hisilicon HiP04 INTC
3  *
4  * Copyright (C) 2002-2014 ARM Limited.
5  * Copyright (c) 2013-2014 Hisilicon Ltd.
6  * Copyright (c) 2013-2014 Linaro Ltd.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License version 2 as
10  * published by the Free Software Foundation.
11  *
12  * Interrupt architecture for the HIP04 INTC:
13  *
14  * o There is one Interrupt Distributor, which receives interrupts
15  *   from system devices and sends them to the Interrupt Controllers.
16  *
17  * o There is one CPU Interface per CPU, which sends interrupts sent
18  *   by the Distributor, and interrupts generated locally, to the
19  *   associated CPU. The base address of the CPU interface is usually
20  *   aliased so that the same address points to different chips depending
21  *   on the CPU it is accessed from.
22  *
23  * Note that IRQs 0-31 are special - they are local to each CPU.
24  * As such, the enable set/clear, pending set/clear and active bit
25  * registers are banked per-cpu for these sources.
26  */
27 
28 #include <linux/init.h>
29 #include <linux/kernel.h>
30 #include <linux/err.h>
31 #include <linux/module.h>
32 #include <linux/list.h>
33 #include <linux/smp.h>
34 #include <linux/cpu.h>
35 #include <linux/cpu_pm.h>
36 #include <linux/cpumask.h>
37 #include <linux/io.h>
38 #include <linux/of.h>
39 #include <linux/of_address.h>
40 #include <linux/of_irq.h>
41 #include <linux/irqdomain.h>
42 #include <linux/interrupt.h>
43 #include <linux/slab.h>
44 #include <linux/irqchip/arm-gic.h>
45 
46 #include <asm/irq.h>
47 #include <asm/exception.h>
48 #include <asm/smp_plat.h>
49 
50 #include "irq-gic-common.h"
51 #include "irqchip.h"
52 
53 #define HIP04_MAX_IRQS		510
54 
55 struct hip04_irq_data {
56 	void __iomem *dist_base;
57 	void __iomem *cpu_base;
58 	struct irq_domain *domain;
59 	unsigned int nr_irqs;
60 };
61 
62 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
63 
64 /*
65  * The GIC mapping of CPU interfaces does not necessarily match
66  * the logical CPU numbering.  Let's use a mapping as returned
67  * by the GIC itself.
68  */
69 #define NR_HIP04_CPU_IF 16
70 static u16 hip04_cpu_map[NR_HIP04_CPU_IF] __read_mostly;
71 
72 static struct hip04_irq_data hip04_data __read_mostly;
73 
74 static inline void __iomem *hip04_dist_base(struct irq_data *d)
75 {
76 	struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d);
77 	return hip04_data->dist_base;
78 }
79 
80 static inline void __iomem *hip04_cpu_base(struct irq_data *d)
81 {
82 	struct hip04_irq_data *hip04_data = irq_data_get_irq_chip_data(d);
83 	return hip04_data->cpu_base;
84 }
85 
86 static inline unsigned int hip04_irq(struct irq_data *d)
87 {
88 	return d->hwirq;
89 }
90 
91 /*
92  * Routines to acknowledge, disable and enable interrupts
93  */
94 static void hip04_mask_irq(struct irq_data *d)
95 {
96 	u32 mask = 1 << (hip04_irq(d) % 32);
97 
98 	raw_spin_lock(&irq_controller_lock);
99 	writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_CLEAR +
100 		       (hip04_irq(d) / 32) * 4);
101 	raw_spin_unlock(&irq_controller_lock);
102 }
103 
104 static void hip04_unmask_irq(struct irq_data *d)
105 {
106 	u32 mask = 1 << (hip04_irq(d) % 32);
107 
108 	raw_spin_lock(&irq_controller_lock);
109 	writel_relaxed(mask, hip04_dist_base(d) + GIC_DIST_ENABLE_SET +
110 		       (hip04_irq(d) / 32) * 4);
111 	raw_spin_unlock(&irq_controller_lock);
112 }
113 
114 static void hip04_eoi_irq(struct irq_data *d)
115 {
116 	writel_relaxed(hip04_irq(d), hip04_cpu_base(d) + GIC_CPU_EOI);
117 }
118 
119 static int hip04_irq_set_type(struct irq_data *d, unsigned int type)
120 {
121 	void __iomem *base = hip04_dist_base(d);
122 	unsigned int irq = hip04_irq(d);
123 
124 	/* Interrupt configuration for SGIs can't be changed */
125 	if (irq < 16)
126 		return -EINVAL;
127 
128 	if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING)
129 		return -EINVAL;
130 
131 	raw_spin_lock(&irq_controller_lock);
132 
133 	gic_configure_irq(irq, type, base, NULL);
134 
135 	raw_spin_unlock(&irq_controller_lock);
136 
137 	return 0;
138 }
139 
140 #ifdef CONFIG_SMP
141 static int hip04_irq_set_affinity(struct irq_data *d,
142 				  const struct cpumask *mask_val,
143 				  bool force)
144 {
145 	void __iomem *reg;
146 	unsigned int cpu, shift = (hip04_irq(d) % 2) * 16;
147 	u32 val, mask, bit;
148 
149 	if (!force)
150 		cpu = cpumask_any_and(mask_val, cpu_online_mask);
151 	else
152 		cpu = cpumask_first(mask_val);
153 
154 	if (cpu >= NR_HIP04_CPU_IF || cpu >= nr_cpu_ids)
155 		return -EINVAL;
156 
157 	raw_spin_lock(&irq_controller_lock);
158 	reg = hip04_dist_base(d) + GIC_DIST_TARGET + ((hip04_irq(d) * 2) & ~3);
159 	mask = 0xffff << shift;
160 	bit = hip04_cpu_map[cpu] << shift;
161 	val = readl_relaxed(reg) & ~mask;
162 	writel_relaxed(val | bit, reg);
163 	raw_spin_unlock(&irq_controller_lock);
164 
165 	return IRQ_SET_MASK_OK;
166 }
167 #endif
168 
169 static void __exception_irq_entry hip04_handle_irq(struct pt_regs *regs)
170 {
171 	u32 irqstat, irqnr;
172 	void __iomem *cpu_base = hip04_data.cpu_base;
173 
174 	do {
175 		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
176 		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
177 
178 		if (likely(irqnr > 15 && irqnr <= HIP04_MAX_IRQS)) {
179 			handle_domain_irq(hip04_data.domain, irqnr, regs);
180 			continue;
181 		}
182 		if (irqnr < 16) {
183 			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
184 #ifdef CONFIG_SMP
185 			handle_IPI(irqnr, regs);
186 #endif
187 			continue;
188 		}
189 		break;
190 	} while (1);
191 }
192 
193 static struct irq_chip hip04_irq_chip = {
194 	.name			= "HIP04 INTC",
195 	.irq_mask		= hip04_mask_irq,
196 	.irq_unmask		= hip04_unmask_irq,
197 	.irq_eoi		= hip04_eoi_irq,
198 	.irq_set_type		= hip04_irq_set_type,
199 #ifdef CONFIG_SMP
200 	.irq_set_affinity	= hip04_irq_set_affinity,
201 #endif
202 };
203 
204 static u16 hip04_get_cpumask(struct hip04_irq_data *intc)
205 {
206 	void __iomem *base = intc->dist_base;
207 	u32 mask, i;
208 
209 	for (i = mask = 0; i < 32; i += 2) {
210 		mask = readl_relaxed(base + GIC_DIST_TARGET + i * 2);
211 		mask |= mask >> 16;
212 		if (mask)
213 			break;
214 	}
215 
216 	if (!mask)
217 		pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
218 
219 	return mask;
220 }
221 
222 static void __init hip04_irq_dist_init(struct hip04_irq_data *intc)
223 {
224 	unsigned int i;
225 	u32 cpumask;
226 	unsigned int nr_irqs = intc->nr_irqs;
227 	void __iomem *base = intc->dist_base;
228 
229 	writel_relaxed(0, base + GIC_DIST_CTRL);
230 
231 	/*
232 	 * Set all global interrupts to this CPU only.
233 	 */
234 	cpumask = hip04_get_cpumask(intc);
235 	cpumask |= cpumask << 16;
236 	for (i = 32; i < nr_irqs; i += 2)
237 		writel_relaxed(cpumask, base + GIC_DIST_TARGET + ((i * 2) & ~3));
238 
239 	gic_dist_config(base, nr_irqs, NULL);
240 
241 	writel_relaxed(1, base + GIC_DIST_CTRL);
242 }
243 
244 static void hip04_irq_cpu_init(struct hip04_irq_data *intc)
245 {
246 	void __iomem *dist_base = intc->dist_base;
247 	void __iomem *base = intc->cpu_base;
248 	unsigned int cpu_mask, cpu = smp_processor_id();
249 	int i;
250 
251 	/*
252 	 * Get what the GIC says our CPU mask is.
253 	 */
254 	BUG_ON(cpu >= NR_HIP04_CPU_IF);
255 	cpu_mask = hip04_get_cpumask(intc);
256 	hip04_cpu_map[cpu] = cpu_mask;
257 
258 	/*
259 	 * Clear our mask from the other map entries in case they're
260 	 * still undefined.
261 	 */
262 	for (i = 0; i < NR_HIP04_CPU_IF; i++)
263 		if (i != cpu)
264 			hip04_cpu_map[i] &= ~cpu_mask;
265 
266 	gic_cpu_config(dist_base, NULL);
267 
268 	writel_relaxed(0xf0, base + GIC_CPU_PRIMASK);
269 	writel_relaxed(1, base + GIC_CPU_CTRL);
270 }
271 
272 #ifdef CONFIG_SMP
273 static void hip04_raise_softirq(const struct cpumask *mask, unsigned int irq)
274 {
275 	int cpu;
276 	unsigned long flags, map = 0;
277 
278 	raw_spin_lock_irqsave(&irq_controller_lock, flags);
279 
280 	/* Convert our logical CPU mask into a physical one. */
281 	for_each_cpu(cpu, mask)
282 		map |= hip04_cpu_map[cpu];
283 
284 	/*
285 	 * Ensure that stores to Normal memory are visible to the
286 	 * other CPUs before they observe us issuing the IPI.
287 	 */
288 	dmb(ishst);
289 
290 	/* this always happens on GIC0 */
291 	writel_relaxed(map << 8 | irq, hip04_data.dist_base + GIC_DIST_SOFTINT);
292 
293 	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
294 }
295 #endif
296 
297 static int hip04_irq_domain_map(struct irq_domain *d, unsigned int irq,
298 				irq_hw_number_t hw)
299 {
300 	if (hw < 32) {
301 		irq_set_percpu_devid(irq);
302 		irq_set_chip_and_handler(irq, &hip04_irq_chip,
303 					 handle_percpu_devid_irq);
304 		set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
305 	} else {
306 		irq_set_chip_and_handler(irq, &hip04_irq_chip,
307 					 handle_fasteoi_irq);
308 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
309 	}
310 	irq_set_chip_data(irq, d->host_data);
311 	return 0;
312 }
313 
314 static int hip04_irq_domain_xlate(struct irq_domain *d,
315 				  struct device_node *controller,
316 				  const u32 *intspec, unsigned int intsize,
317 				  unsigned long *out_hwirq,
318 				  unsigned int *out_type)
319 {
320 	unsigned long ret = 0;
321 
322 	if (d->of_node != controller)
323 		return -EINVAL;
324 	if (intsize < 3)
325 		return -EINVAL;
326 
327 	/* Get the interrupt number and add 16 to skip over SGIs */
328 	*out_hwirq = intspec[1] + 16;
329 
330 	/* For SPIs, we need to add 16 more to get the irq ID number */
331 	if (!intspec[0])
332 		*out_hwirq += 16;
333 
334 	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
335 
336 	return ret;
337 }
338 
339 #ifdef CONFIG_SMP
340 static int hip04_irq_secondary_init(struct notifier_block *nfb,
341 				    unsigned long action,
342 				    void *hcpu)
343 {
344 	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
345 		hip04_irq_cpu_init(&hip04_data);
346 	return NOTIFY_OK;
347 }
348 
349 /*
350  * Notifier for enabling the INTC CPU interface. Set an arbitrarily high
351  * priority because the GIC needs to be up before the ARM generic timers.
352  */
353 static struct notifier_block hip04_irq_cpu_notifier = {
354 	.notifier_call	= hip04_irq_secondary_init,
355 	.priority	= 100,
356 };
357 #endif
358 
359 static const struct irq_domain_ops hip04_irq_domain_ops = {
360 	.map	= hip04_irq_domain_map,
361 	.xlate	= hip04_irq_domain_xlate,
362 };
363 
364 static int __init
365 hip04_of_init(struct device_node *node, struct device_node *parent)
366 {
367 	irq_hw_number_t hwirq_base = 16;
368 	int nr_irqs, irq_base, i;
369 
370 	if (WARN_ON(!node))
371 		return -ENODEV;
372 
373 	hip04_data.dist_base = of_iomap(node, 0);
374 	WARN(!hip04_data.dist_base, "fail to map hip04 intc dist registers\n");
375 
376 	hip04_data.cpu_base = of_iomap(node, 1);
377 	WARN(!hip04_data.cpu_base, "unable to map hip04 intc cpu registers\n");
378 
379 	/*
380 	 * Initialize the CPU interface map to all CPUs.
381 	 * It will be refined as each CPU probes its ID.
382 	 */
383 	for (i = 0; i < NR_HIP04_CPU_IF; i++)
384 		hip04_cpu_map[i] = 0xffff;
385 
386 	/*
387 	 * Find out how many interrupts are supported.
388 	 * The HIP04 INTC only supports up to 510 interrupt sources.
389 	 */
390 	nr_irqs = readl_relaxed(hip04_data.dist_base + GIC_DIST_CTR) & 0x1f;
391 	nr_irqs = (nr_irqs + 1) * 32;
392 	if (nr_irqs > HIP04_MAX_IRQS)
393 		nr_irqs = HIP04_MAX_IRQS;
394 	hip04_data.nr_irqs = nr_irqs;
395 
396 	nr_irqs -= hwirq_base; /* calculate # of irqs to allocate */
397 
398 	irq_base = irq_alloc_descs(-1, hwirq_base, nr_irqs, numa_node_id());
399 	if (IS_ERR_VALUE(irq_base)) {
400 		pr_err("failed to allocate IRQ numbers\n");
401 		return -EINVAL;
402 	}
403 
404 	hip04_data.domain = irq_domain_add_legacy(node, nr_irqs, irq_base,
405 						  hwirq_base,
406 						  &hip04_irq_domain_ops,
407 						  &hip04_data);
408 
409 	if (WARN_ON(!hip04_data.domain))
410 		return -EINVAL;
411 
412 #ifdef CONFIG_SMP
413 	set_smp_cross_call(hip04_raise_softirq);
414 	register_cpu_notifier(&hip04_irq_cpu_notifier);
415 #endif
416 	set_handle_irq(hip04_handle_irq);
417 
418 	hip04_irq_dist_init(&hip04_data);
419 	hip04_irq_cpu_init(&hip04_data);
420 
421 	return 0;
422 }
423 IRQCHIP_DECLARE(hip04_intc, "hisilicon,hip04-intc", hip04_of_init);
424