1 /* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Interrupt architecture for the GIC: 9 * 10 * o There is one Interrupt Distributor, which receives interrupts 11 * from system devices and sends them to the Interrupt Controllers. 12 * 13 * o There is one CPU Interface per CPU, which sends interrupts sent 14 * by the Distributor, and interrupts generated locally, to the 15 * associated CPU. The base address of the CPU interface is usually 16 * aliased so that the same address points to different chips depending 17 * on the CPU it is accessed from. 18 * 19 * Note that IRQs 0-31 are special - they are local to each CPU. 20 * As such, the enable set/clear, pending set/clear and active bit 21 * registers are banked per-cpu for these sources. 22 */ 23 #include <linux/init.h> 24 #include <linux/kernel.h> 25 #include <linux/err.h> 26 #include <linux/module.h> 27 #include <linux/list.h> 28 #include <linux/smp.h> 29 #include <linux/cpu.h> 30 #include <linux/cpu_pm.h> 31 #include <linux/cpumask.h> 32 #include <linux/io.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/acpi.h> 37 #include <linux/irqdomain.h> 38 #include <linux/interrupt.h> 39 #include <linux/percpu.h> 40 #include <linux/slab.h> 41 #include <linux/irqchip/chained_irq.h> 42 #include <linux/irqchip/arm-gic.h> 43 #include <linux/irqchip/arm-gic-acpi.h> 44 45 #include <asm/cputype.h> 46 #include <asm/irq.h> 47 #include <asm/exception.h> 48 #include <asm/smp_plat.h> 49 50 #include "irq-gic-common.h" 51 #include "irqchip.h" 52 53 union gic_base { 54 void __iomem *common_base; 55 void __percpu * __iomem *percpu_base; 56 }; 57 58 struct gic_chip_data { 59 union gic_base dist_base; 60 union gic_base cpu_base; 61 #ifdef CONFIG_CPU_PM 62 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 63 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 64 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 65 u32 __percpu *saved_ppi_enable; 66 u32 __percpu *saved_ppi_conf; 67 #endif 68 struct irq_domain *domain; 69 unsigned int gic_irqs; 70 #ifdef CONFIG_GIC_NON_BANKED 71 void __iomem *(*get_base)(union gic_base *); 72 #endif 73 }; 74 75 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 76 77 /* 78 * The GIC mapping of CPU interfaces does not necessarily match 79 * the logical CPU numbering. Let's use a mapping as returned 80 * by the GIC itself. 81 */ 82 #define NR_GIC_CPU_IF 8 83 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 84 85 #ifndef MAX_GIC_NR 86 #define MAX_GIC_NR 1 87 #endif 88 89 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; 90 91 #ifdef CONFIG_GIC_NON_BANKED 92 static void __iomem *gic_get_percpu_base(union gic_base *base) 93 { 94 return raw_cpu_read(*base->percpu_base); 95 } 96 97 static void __iomem *gic_get_common_base(union gic_base *base) 98 { 99 return base->common_base; 100 } 101 102 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 103 { 104 return data->get_base(&data->dist_base); 105 } 106 107 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 108 { 109 return data->get_base(&data->cpu_base); 110 } 111 112 static inline void gic_set_base_accessor(struct gic_chip_data *data, 113 void __iomem *(*f)(union gic_base *)) 114 { 115 data->get_base = f; 116 } 117 #else 118 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 119 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 120 #define gic_set_base_accessor(d, f) 121 #endif 122 123 static inline void __iomem *gic_dist_base(struct irq_data *d) 124 { 125 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 126 return gic_data_dist_base(gic_data); 127 } 128 129 static inline void __iomem *gic_cpu_base(struct irq_data *d) 130 { 131 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 132 return gic_data_cpu_base(gic_data); 133 } 134 135 static inline unsigned int gic_irq(struct irq_data *d) 136 { 137 return d->hwirq; 138 } 139 140 /* 141 * Routines to acknowledge, disable and enable interrupts 142 */ 143 static void gic_poke_irq(struct irq_data *d, u32 offset) 144 { 145 u32 mask = 1 << (gic_irq(d) % 32); 146 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 147 } 148 149 static int gic_peek_irq(struct irq_data *d, u32 offset) 150 { 151 u32 mask = 1 << (gic_irq(d) % 32); 152 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 153 } 154 155 static void gic_mask_irq(struct irq_data *d) 156 { 157 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 158 } 159 160 static void gic_unmask_irq(struct irq_data *d) 161 { 162 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 163 } 164 165 static void gic_eoi_irq(struct irq_data *d) 166 { 167 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 168 } 169 170 static int gic_irq_set_irqchip_state(struct irq_data *d, 171 enum irqchip_irq_state which, bool val) 172 { 173 u32 reg; 174 175 switch (which) { 176 case IRQCHIP_STATE_PENDING: 177 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 178 break; 179 180 case IRQCHIP_STATE_ACTIVE: 181 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 182 break; 183 184 case IRQCHIP_STATE_MASKED: 185 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 186 break; 187 188 default: 189 return -EINVAL; 190 } 191 192 gic_poke_irq(d, reg); 193 return 0; 194 } 195 196 static int gic_irq_get_irqchip_state(struct irq_data *d, 197 enum irqchip_irq_state which, bool *val) 198 { 199 switch (which) { 200 case IRQCHIP_STATE_PENDING: 201 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 202 break; 203 204 case IRQCHIP_STATE_ACTIVE: 205 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 206 break; 207 208 case IRQCHIP_STATE_MASKED: 209 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 210 break; 211 212 default: 213 return -EINVAL; 214 } 215 216 return 0; 217 } 218 219 static int gic_set_type(struct irq_data *d, unsigned int type) 220 { 221 void __iomem *base = gic_dist_base(d); 222 unsigned int gicirq = gic_irq(d); 223 224 /* Interrupt configuration for SGIs can't be changed */ 225 if (gicirq < 16) 226 return -EINVAL; 227 228 /* SPIs have restrictions on the supported types */ 229 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 230 type != IRQ_TYPE_EDGE_RISING) 231 return -EINVAL; 232 233 return gic_configure_irq(gicirq, type, base, NULL); 234 } 235 236 #ifdef CONFIG_SMP 237 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 238 bool force) 239 { 240 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 241 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 242 u32 val, mask, bit; 243 unsigned long flags; 244 245 if (!force) 246 cpu = cpumask_any_and(mask_val, cpu_online_mask); 247 else 248 cpu = cpumask_first(mask_val); 249 250 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 251 return -EINVAL; 252 253 raw_spin_lock_irqsave(&irq_controller_lock, flags); 254 mask = 0xff << shift; 255 bit = gic_cpu_map[cpu] << shift; 256 val = readl_relaxed(reg) & ~mask; 257 writel_relaxed(val | bit, reg); 258 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 259 260 return IRQ_SET_MASK_OK; 261 } 262 #endif 263 264 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 265 { 266 u32 irqstat, irqnr; 267 struct gic_chip_data *gic = &gic_data[0]; 268 void __iomem *cpu_base = gic_data_cpu_base(gic); 269 270 do { 271 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 272 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 273 274 if (likely(irqnr > 15 && irqnr < 1021)) { 275 handle_domain_irq(gic->domain, irqnr, regs); 276 continue; 277 } 278 if (irqnr < 16) { 279 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 280 #ifdef CONFIG_SMP 281 handle_IPI(irqnr, regs); 282 #endif 283 continue; 284 } 285 break; 286 } while (1); 287 } 288 289 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 290 { 291 struct gic_chip_data *chip_data = irq_get_handler_data(irq); 292 struct irq_chip *chip = irq_get_chip(irq); 293 unsigned int cascade_irq, gic_irq; 294 unsigned long status; 295 296 chained_irq_enter(chip, desc); 297 298 raw_spin_lock(&irq_controller_lock); 299 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 300 raw_spin_unlock(&irq_controller_lock); 301 302 gic_irq = (status & GICC_IAR_INT_ID_MASK); 303 if (gic_irq == GICC_INT_SPURIOUS) 304 goto out; 305 306 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 307 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 308 handle_bad_irq(cascade_irq, desc); 309 else 310 generic_handle_irq(cascade_irq); 311 312 out: 313 chained_irq_exit(chip, desc); 314 } 315 316 static struct irq_chip gic_chip = { 317 .name = "GIC", 318 .irq_mask = gic_mask_irq, 319 .irq_unmask = gic_unmask_irq, 320 .irq_eoi = gic_eoi_irq, 321 .irq_set_type = gic_set_type, 322 #ifdef CONFIG_SMP 323 .irq_set_affinity = gic_set_affinity, 324 #endif 325 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 326 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 327 .flags = IRQCHIP_SET_TYPE_MASKED, 328 }; 329 330 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 331 { 332 if (gic_nr >= MAX_GIC_NR) 333 BUG(); 334 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) 335 BUG(); 336 irq_set_chained_handler(irq, gic_handle_cascade_irq); 337 } 338 339 static u8 gic_get_cpumask(struct gic_chip_data *gic) 340 { 341 void __iomem *base = gic_data_dist_base(gic); 342 u32 mask, i; 343 344 for (i = mask = 0; i < 32; i += 4) { 345 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 346 mask |= mask >> 16; 347 mask |= mask >> 8; 348 if (mask) 349 break; 350 } 351 352 if (!mask && num_possible_cpus() > 1) 353 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 354 355 return mask; 356 } 357 358 static void gic_cpu_if_up(void) 359 { 360 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 361 u32 bypass = 0; 362 363 /* 364 * Preserve bypass disable bits to be written back later 365 */ 366 bypass = readl(cpu_base + GIC_CPU_CTRL); 367 bypass &= GICC_DIS_BYPASS_MASK; 368 369 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 370 } 371 372 373 static void __init gic_dist_init(struct gic_chip_data *gic) 374 { 375 unsigned int i; 376 u32 cpumask; 377 unsigned int gic_irqs = gic->gic_irqs; 378 void __iomem *base = gic_data_dist_base(gic); 379 380 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 381 382 /* 383 * Set all global interrupts to this CPU only. 384 */ 385 cpumask = gic_get_cpumask(gic); 386 cpumask |= cpumask << 8; 387 cpumask |= cpumask << 16; 388 for (i = 32; i < gic_irqs; i += 4) 389 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 390 391 gic_dist_config(base, gic_irqs, NULL); 392 393 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 394 } 395 396 static void gic_cpu_init(struct gic_chip_data *gic) 397 { 398 void __iomem *dist_base = gic_data_dist_base(gic); 399 void __iomem *base = gic_data_cpu_base(gic); 400 unsigned int cpu_mask, cpu = smp_processor_id(); 401 int i; 402 403 /* 404 * Get what the GIC says our CPU mask is. 405 */ 406 BUG_ON(cpu >= NR_GIC_CPU_IF); 407 cpu_mask = gic_get_cpumask(gic); 408 gic_cpu_map[cpu] = cpu_mask; 409 410 /* 411 * Clear our mask from the other map entries in case they're 412 * still undefined. 413 */ 414 for (i = 0; i < NR_GIC_CPU_IF; i++) 415 if (i != cpu) 416 gic_cpu_map[i] &= ~cpu_mask; 417 418 gic_cpu_config(dist_base, NULL); 419 420 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 421 gic_cpu_if_up(); 422 } 423 424 void gic_cpu_if_down(void) 425 { 426 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 427 u32 val = 0; 428 429 val = readl(cpu_base + GIC_CPU_CTRL); 430 val &= ~GICC_ENABLE; 431 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 432 } 433 434 #ifdef CONFIG_CPU_PM 435 /* 436 * Saves the GIC distributor registers during suspend or idle. Must be called 437 * with interrupts disabled but before powering down the GIC. After calling 438 * this function, no interrupts will be delivered by the GIC, and another 439 * platform-specific wakeup source must be enabled. 440 */ 441 static void gic_dist_save(unsigned int gic_nr) 442 { 443 unsigned int gic_irqs; 444 void __iomem *dist_base; 445 int i; 446 447 if (gic_nr >= MAX_GIC_NR) 448 BUG(); 449 450 gic_irqs = gic_data[gic_nr].gic_irqs; 451 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 452 453 if (!dist_base) 454 return; 455 456 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 457 gic_data[gic_nr].saved_spi_conf[i] = 458 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 459 460 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 461 gic_data[gic_nr].saved_spi_target[i] = 462 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 463 464 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 465 gic_data[gic_nr].saved_spi_enable[i] = 466 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 467 } 468 469 /* 470 * Restores the GIC distributor registers during resume or when coming out of 471 * idle. Must be called before enabling interrupts. If a level interrupt 472 * that occured while the GIC was suspended is still present, it will be 473 * handled normally, but any edge interrupts that occured will not be seen by 474 * the GIC and need to be handled by the platform-specific wakeup source. 475 */ 476 static void gic_dist_restore(unsigned int gic_nr) 477 { 478 unsigned int gic_irqs; 479 unsigned int i; 480 void __iomem *dist_base; 481 482 if (gic_nr >= MAX_GIC_NR) 483 BUG(); 484 485 gic_irqs = gic_data[gic_nr].gic_irqs; 486 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 487 488 if (!dist_base) 489 return; 490 491 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 492 493 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 494 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], 495 dist_base + GIC_DIST_CONFIG + i * 4); 496 497 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 498 writel_relaxed(GICD_INT_DEF_PRI_X4, 499 dist_base + GIC_DIST_PRI + i * 4); 500 501 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 502 writel_relaxed(gic_data[gic_nr].saved_spi_target[i], 503 dist_base + GIC_DIST_TARGET + i * 4); 504 505 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 506 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], 507 dist_base + GIC_DIST_ENABLE_SET + i * 4); 508 509 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 510 } 511 512 static void gic_cpu_save(unsigned int gic_nr) 513 { 514 int i; 515 u32 *ptr; 516 void __iomem *dist_base; 517 void __iomem *cpu_base; 518 519 if (gic_nr >= MAX_GIC_NR) 520 BUG(); 521 522 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 523 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 524 525 if (!dist_base || !cpu_base) 526 return; 527 528 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 529 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 530 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 531 532 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 533 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 534 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 535 536 } 537 538 static void gic_cpu_restore(unsigned int gic_nr) 539 { 540 int i; 541 u32 *ptr; 542 void __iomem *dist_base; 543 void __iomem *cpu_base; 544 545 if (gic_nr >= MAX_GIC_NR) 546 BUG(); 547 548 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 549 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 550 551 if (!dist_base || !cpu_base) 552 return; 553 554 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 555 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 556 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 557 558 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 559 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 560 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 561 562 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 563 writel_relaxed(GICD_INT_DEF_PRI_X4, 564 dist_base + GIC_DIST_PRI + i * 4); 565 566 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 567 gic_cpu_if_up(); 568 } 569 570 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 571 { 572 int i; 573 574 for (i = 0; i < MAX_GIC_NR; i++) { 575 #ifdef CONFIG_GIC_NON_BANKED 576 /* Skip over unused GICs */ 577 if (!gic_data[i].get_base) 578 continue; 579 #endif 580 switch (cmd) { 581 case CPU_PM_ENTER: 582 gic_cpu_save(i); 583 break; 584 case CPU_PM_ENTER_FAILED: 585 case CPU_PM_EXIT: 586 gic_cpu_restore(i); 587 break; 588 case CPU_CLUSTER_PM_ENTER: 589 gic_dist_save(i); 590 break; 591 case CPU_CLUSTER_PM_ENTER_FAILED: 592 case CPU_CLUSTER_PM_EXIT: 593 gic_dist_restore(i); 594 break; 595 } 596 } 597 598 return NOTIFY_OK; 599 } 600 601 static struct notifier_block gic_notifier_block = { 602 .notifier_call = gic_notifier, 603 }; 604 605 static void __init gic_pm_init(struct gic_chip_data *gic) 606 { 607 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 608 sizeof(u32)); 609 BUG_ON(!gic->saved_ppi_enable); 610 611 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 612 sizeof(u32)); 613 BUG_ON(!gic->saved_ppi_conf); 614 615 if (gic == &gic_data[0]) 616 cpu_pm_register_notifier(&gic_notifier_block); 617 } 618 #else 619 static void __init gic_pm_init(struct gic_chip_data *gic) 620 { 621 } 622 #endif 623 624 #ifdef CONFIG_SMP 625 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 626 { 627 int cpu; 628 unsigned long flags, map = 0; 629 630 raw_spin_lock_irqsave(&irq_controller_lock, flags); 631 632 /* Convert our logical CPU mask into a physical one. */ 633 for_each_cpu(cpu, mask) 634 map |= gic_cpu_map[cpu]; 635 636 /* 637 * Ensure that stores to Normal memory are visible to the 638 * other CPUs before they observe us issuing the IPI. 639 */ 640 dmb(ishst); 641 642 /* this always happens on GIC0 */ 643 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 644 645 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 646 } 647 #endif 648 649 #ifdef CONFIG_BL_SWITCHER 650 /* 651 * gic_send_sgi - send a SGI directly to given CPU interface number 652 * 653 * cpu_id: the ID for the destination CPU interface 654 * irq: the IPI number to send a SGI for 655 */ 656 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 657 { 658 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 659 cpu_id = 1 << cpu_id; 660 /* this always happens on GIC0 */ 661 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 662 } 663 664 /* 665 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 666 * 667 * @cpu: the logical CPU number to get the GIC ID for. 668 * 669 * Return the CPU interface ID for the given logical CPU number, 670 * or -1 if the CPU number is too large or the interface ID is 671 * unknown (more than one bit set). 672 */ 673 int gic_get_cpu_id(unsigned int cpu) 674 { 675 unsigned int cpu_bit; 676 677 if (cpu >= NR_GIC_CPU_IF) 678 return -1; 679 cpu_bit = gic_cpu_map[cpu]; 680 if (cpu_bit & (cpu_bit - 1)) 681 return -1; 682 return __ffs(cpu_bit); 683 } 684 685 /* 686 * gic_migrate_target - migrate IRQs to another CPU interface 687 * 688 * @new_cpu_id: the CPU target ID to migrate IRQs to 689 * 690 * Migrate all peripheral interrupts with a target matching the current CPU 691 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 692 * is also updated. Targets to other CPU interfaces are unchanged. 693 * This must be called with IRQs locally disabled. 694 */ 695 void gic_migrate_target(unsigned int new_cpu_id) 696 { 697 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 698 void __iomem *dist_base; 699 int i, ror_val, cpu = smp_processor_id(); 700 u32 val, cur_target_mask, active_mask; 701 702 if (gic_nr >= MAX_GIC_NR) 703 BUG(); 704 705 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 706 if (!dist_base) 707 return; 708 gic_irqs = gic_data[gic_nr].gic_irqs; 709 710 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 711 cur_target_mask = 0x01010101 << cur_cpu_id; 712 ror_val = (cur_cpu_id - new_cpu_id) & 31; 713 714 raw_spin_lock(&irq_controller_lock); 715 716 /* Update the target interface for this logical CPU */ 717 gic_cpu_map[cpu] = 1 << new_cpu_id; 718 719 /* 720 * Find all the peripheral interrupts targetting the current 721 * CPU interface and migrate them to the new CPU interface. 722 * We skip DIST_TARGET 0 to 7 as they are read-only. 723 */ 724 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 725 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 726 active_mask = val & cur_target_mask; 727 if (active_mask) { 728 val &= ~active_mask; 729 val |= ror32(active_mask, ror_val); 730 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 731 } 732 } 733 734 raw_spin_unlock(&irq_controller_lock); 735 736 /* 737 * Now let's migrate and clear any potential SGIs that might be 738 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 739 * is a banked register, we can only forward the SGI using 740 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 741 * doesn't use that information anyway. 742 * 743 * For the same reason we do not adjust SGI source information 744 * for previously sent SGIs by us to other CPUs either. 745 */ 746 for (i = 0; i < 16; i += 4) { 747 int j; 748 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 749 if (!val) 750 continue; 751 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 752 for (j = i; j < i + 4; j++) { 753 if (val & 0xff) 754 writel_relaxed((1 << (new_cpu_id + 16)) | j, 755 dist_base + GIC_DIST_SOFTINT); 756 val >>= 8; 757 } 758 } 759 } 760 761 /* 762 * gic_get_sgir_physaddr - get the physical address for the SGI register 763 * 764 * REturn the physical address of the SGI register to be used 765 * by some early assembly code when the kernel is not yet available. 766 */ 767 static unsigned long gic_dist_physaddr; 768 769 unsigned long gic_get_sgir_physaddr(void) 770 { 771 if (!gic_dist_physaddr) 772 return 0; 773 return gic_dist_physaddr + GIC_DIST_SOFTINT; 774 } 775 776 void __init gic_init_physaddr(struct device_node *node) 777 { 778 struct resource res; 779 if (of_address_to_resource(node, 0, &res) == 0) { 780 gic_dist_physaddr = res.start; 781 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 782 } 783 } 784 785 #else 786 #define gic_init_physaddr(node) do { } while (0) 787 #endif 788 789 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 790 irq_hw_number_t hw) 791 { 792 if (hw < 32) { 793 irq_set_percpu_devid(irq); 794 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 795 handle_percpu_devid_irq, NULL, NULL); 796 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 797 } else { 798 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 799 handle_fasteoi_irq, NULL, NULL); 800 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 801 } 802 return 0; 803 } 804 805 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 806 { 807 } 808 809 static int gic_irq_domain_xlate(struct irq_domain *d, 810 struct device_node *controller, 811 const u32 *intspec, unsigned int intsize, 812 unsigned long *out_hwirq, unsigned int *out_type) 813 { 814 unsigned long ret = 0; 815 816 if (d->of_node != controller) 817 return -EINVAL; 818 if (intsize < 3) 819 return -EINVAL; 820 821 /* Get the interrupt number and add 16 to skip over SGIs */ 822 *out_hwirq = intspec[1] + 16; 823 824 /* For SPIs, we need to add 16 more to get the GIC irq ID number */ 825 if (!intspec[0]) 826 *out_hwirq += 16; 827 828 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 829 830 return ret; 831 } 832 833 #ifdef CONFIG_SMP 834 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, 835 void *hcpu) 836 { 837 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 838 gic_cpu_init(&gic_data[0]); 839 return NOTIFY_OK; 840 } 841 842 /* 843 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 844 * priority because the GIC needs to be up before the ARM generic timers. 845 */ 846 static struct notifier_block gic_cpu_notifier = { 847 .notifier_call = gic_secondary_init, 848 .priority = 100, 849 }; 850 #endif 851 852 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 853 unsigned int nr_irqs, void *arg) 854 { 855 int i, ret; 856 irq_hw_number_t hwirq; 857 unsigned int type = IRQ_TYPE_NONE; 858 struct of_phandle_args *irq_data = arg; 859 860 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 861 irq_data->args_count, &hwirq, &type); 862 if (ret) 863 return ret; 864 865 for (i = 0; i < nr_irqs; i++) 866 gic_irq_domain_map(domain, virq + i, hwirq + i); 867 868 return 0; 869 } 870 871 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 872 .xlate = gic_irq_domain_xlate, 873 .alloc = gic_irq_domain_alloc, 874 .free = irq_domain_free_irqs_top, 875 }; 876 877 static const struct irq_domain_ops gic_irq_domain_ops = { 878 .map = gic_irq_domain_map, 879 .unmap = gic_irq_domain_unmap, 880 .xlate = gic_irq_domain_xlate, 881 }; 882 883 void gic_set_irqchip_flags(unsigned long flags) 884 { 885 gic_chip.flags |= flags; 886 } 887 888 void __init gic_init_bases(unsigned int gic_nr, int irq_start, 889 void __iomem *dist_base, void __iomem *cpu_base, 890 u32 percpu_offset, struct device_node *node) 891 { 892 irq_hw_number_t hwirq_base; 893 struct gic_chip_data *gic; 894 int gic_irqs, irq_base, i; 895 896 BUG_ON(gic_nr >= MAX_GIC_NR); 897 898 gic = &gic_data[gic_nr]; 899 #ifdef CONFIG_GIC_NON_BANKED 900 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 901 unsigned int cpu; 902 903 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 904 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 905 if (WARN_ON(!gic->dist_base.percpu_base || 906 !gic->cpu_base.percpu_base)) { 907 free_percpu(gic->dist_base.percpu_base); 908 free_percpu(gic->cpu_base.percpu_base); 909 return; 910 } 911 912 for_each_possible_cpu(cpu) { 913 u32 mpidr = cpu_logical_map(cpu); 914 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 915 unsigned long offset = percpu_offset * core_id; 916 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; 917 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; 918 } 919 920 gic_set_base_accessor(gic, gic_get_percpu_base); 921 } else 922 #endif 923 { /* Normal, sane GIC... */ 924 WARN(percpu_offset, 925 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 926 percpu_offset); 927 gic->dist_base.common_base = dist_base; 928 gic->cpu_base.common_base = cpu_base; 929 gic_set_base_accessor(gic, gic_get_common_base); 930 } 931 932 /* 933 * Initialize the CPU interface map to all CPUs. 934 * It will be refined as each CPU probes its ID. 935 */ 936 for (i = 0; i < NR_GIC_CPU_IF; i++) 937 gic_cpu_map[i] = 0xff; 938 939 /* 940 * Find out how many interrupts are supported. 941 * The GIC only supports up to 1020 interrupt sources. 942 */ 943 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 944 gic_irqs = (gic_irqs + 1) * 32; 945 if (gic_irqs > 1020) 946 gic_irqs = 1020; 947 gic->gic_irqs = gic_irqs; 948 949 if (node) { /* DT case */ 950 gic->domain = irq_domain_add_linear(node, gic_irqs, 951 &gic_irq_domain_hierarchy_ops, 952 gic); 953 } else { /* Non-DT case */ 954 /* 955 * For primary GICs, skip over SGIs. 956 * For secondary GICs, skip over PPIs, too. 957 */ 958 if (gic_nr == 0 && (irq_start & 31) > 0) { 959 hwirq_base = 16; 960 if (irq_start != -1) 961 irq_start = (irq_start & ~31) + 16; 962 } else { 963 hwirq_base = 32; 964 } 965 966 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 967 968 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 969 numa_node_id()); 970 if (IS_ERR_VALUE(irq_base)) { 971 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 972 irq_start); 973 irq_base = irq_start; 974 } 975 976 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, 977 hwirq_base, &gic_irq_domain_ops, gic); 978 } 979 980 if (WARN_ON(!gic->domain)) 981 return; 982 983 if (gic_nr == 0) { 984 #ifdef CONFIG_SMP 985 set_smp_cross_call(gic_raise_softirq); 986 register_cpu_notifier(&gic_cpu_notifier); 987 #endif 988 set_handle_irq(gic_handle_irq); 989 } 990 991 gic_dist_init(gic); 992 gic_cpu_init(gic); 993 gic_pm_init(gic); 994 } 995 996 #ifdef CONFIG_OF 997 static int gic_cnt __initdata; 998 999 static int __init 1000 gic_of_init(struct device_node *node, struct device_node *parent) 1001 { 1002 void __iomem *cpu_base; 1003 void __iomem *dist_base; 1004 u32 percpu_offset; 1005 int irq; 1006 1007 if (WARN_ON(!node)) 1008 return -ENODEV; 1009 1010 dist_base = of_iomap(node, 0); 1011 WARN(!dist_base, "unable to map gic dist registers\n"); 1012 1013 cpu_base = of_iomap(node, 1); 1014 WARN(!cpu_base, "unable to map gic cpu registers\n"); 1015 1016 if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) 1017 percpu_offset = 0; 1018 1019 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); 1020 if (!gic_cnt) 1021 gic_init_physaddr(node); 1022 1023 if (parent) { 1024 irq = irq_of_parse_and_map(node, 0); 1025 gic_cascade_irq(gic_cnt, irq); 1026 } 1027 1028 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1029 gicv2m_of_init(node, gic_data[gic_cnt].domain); 1030 1031 gic_cnt++; 1032 return 0; 1033 } 1034 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1035 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1036 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1037 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1038 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1039 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1040 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1041 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1042 1043 #endif 1044 1045 #ifdef CONFIG_ACPI 1046 static phys_addr_t dist_phy_base, cpu_phy_base __initdata; 1047 1048 static int __init 1049 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, 1050 const unsigned long end) 1051 { 1052 struct acpi_madt_generic_interrupt *processor; 1053 phys_addr_t gic_cpu_base; 1054 static int cpu_base_assigned; 1055 1056 processor = (struct acpi_madt_generic_interrupt *)header; 1057 1058 if (BAD_MADT_GICC_ENTRY(processor, end)) 1059 return -EINVAL; 1060 1061 /* 1062 * There is no support for non-banked GICv1/2 register in ACPI spec. 1063 * All CPU interface addresses have to be the same. 1064 */ 1065 gic_cpu_base = processor->base_address; 1066 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) 1067 return -EINVAL; 1068 1069 cpu_phy_base = gic_cpu_base; 1070 cpu_base_assigned = 1; 1071 return 0; 1072 } 1073 1074 static int __init 1075 gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, 1076 const unsigned long end) 1077 { 1078 struct acpi_madt_generic_distributor *dist; 1079 1080 dist = (struct acpi_madt_generic_distributor *)header; 1081 1082 if (BAD_MADT_ENTRY(dist, end)) 1083 return -EINVAL; 1084 1085 dist_phy_base = dist->base_address; 1086 return 0; 1087 } 1088 1089 int __init 1090 gic_v2_acpi_init(struct acpi_table_header *table) 1091 { 1092 void __iomem *cpu_base, *dist_base; 1093 int count; 1094 1095 /* Collect CPU base addresses */ 1096 count = acpi_parse_entries(ACPI_SIG_MADT, 1097 sizeof(struct acpi_table_madt), 1098 gic_acpi_parse_madt_cpu, table, 1099 ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); 1100 if (count <= 0) { 1101 pr_err("No valid GICC entries exist\n"); 1102 return -EINVAL; 1103 } 1104 1105 /* 1106 * Find distributor base address. We expect one distributor entry since 1107 * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. 1108 */ 1109 count = acpi_parse_entries(ACPI_SIG_MADT, 1110 sizeof(struct acpi_table_madt), 1111 gic_acpi_parse_madt_distributor, table, 1112 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); 1113 if (count <= 0) { 1114 pr_err("No valid GICD entries exist\n"); 1115 return -EINVAL; 1116 } else if (count > 1) { 1117 pr_err("More than one GICD entry detected\n"); 1118 return -EINVAL; 1119 } 1120 1121 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1122 if (!cpu_base) { 1123 pr_err("Unable to map GICC registers\n"); 1124 return -ENOMEM; 1125 } 1126 1127 dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); 1128 if (!dist_base) { 1129 pr_err("Unable to map GICD registers\n"); 1130 iounmap(cpu_base); 1131 return -ENOMEM; 1132 } 1133 1134 /* 1135 * Initialize zero GIC instance (no multi-GIC support). Also, set GIC 1136 * as default IRQ domain to allow for GSI registration and GSI to IRQ 1137 * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). 1138 */ 1139 gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); 1140 irq_set_default_host(gic_data[0].domain); 1141 1142 acpi_irq_model = ACPI_IRQ_MODEL_GIC; 1143 return 0; 1144 } 1145 #endif 1146