1 /* 2 * linux/arch/arm/common/gic.c 3 * 4 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * Interrupt architecture for the GIC: 11 * 12 * o There is one Interrupt Distributor, which receives interrupts 13 * from system devices and sends them to the Interrupt Controllers. 14 * 15 * o There is one CPU Interface per CPU, which sends interrupts sent 16 * by the Distributor, and interrupts generated locally, to the 17 * associated CPU. The base address of the CPU interface is usually 18 * aliased so that the same address points to different chips depending 19 * on the CPU it is accessed from. 20 * 21 * Note that IRQs 0-31 are special - they are local to each CPU. 22 * As such, the enable set/clear, pending set/clear and active bit 23 * registers are banked per-cpu for these sources. 24 */ 25 #include <linux/init.h> 26 #include <linux/kernel.h> 27 #include <linux/err.h> 28 #include <linux/module.h> 29 #include <linux/list.h> 30 #include <linux/smp.h> 31 #include <linux/cpu.h> 32 #include <linux/cpu_pm.h> 33 #include <linux/cpumask.h> 34 #include <linux/io.h> 35 #include <linux/of.h> 36 #include <linux/of_address.h> 37 #include <linux/of_irq.h> 38 #include <linux/irqdomain.h> 39 #include <linux/interrupt.h> 40 #include <linux/percpu.h> 41 #include <linux/slab.h> 42 #include <linux/irqchip/chained_irq.h> 43 #include <linux/irqchip/arm-gic.h> 44 45 #include <asm/irq.h> 46 #include <asm/exception.h> 47 #include <asm/smp_plat.h> 48 49 #include "irqchip.h" 50 51 union gic_base { 52 void __iomem *common_base; 53 void __percpu * __iomem *percpu_base; 54 }; 55 56 struct gic_chip_data { 57 union gic_base dist_base; 58 union gic_base cpu_base; 59 #ifdef CONFIG_CPU_PM 60 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 61 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 62 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 63 u32 __percpu *saved_ppi_enable; 64 u32 __percpu *saved_ppi_conf; 65 #endif 66 struct irq_domain *domain; 67 unsigned int gic_irqs; 68 #ifdef CONFIG_GIC_NON_BANKED 69 void __iomem *(*get_base)(union gic_base *); 70 #endif 71 }; 72 73 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 74 75 /* 76 * The GIC mapping of CPU interfaces does not necessarily match 77 * the logical CPU numbering. Let's use a mapping as returned 78 * by the GIC itself. 79 */ 80 #define NR_GIC_CPU_IF 8 81 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 82 83 /* 84 * Supported arch specific GIC irq extension. 85 * Default make them NULL. 86 */ 87 struct irq_chip gic_arch_extn = { 88 .irq_eoi = NULL, 89 .irq_mask = NULL, 90 .irq_unmask = NULL, 91 .irq_retrigger = NULL, 92 .irq_set_type = NULL, 93 .irq_set_wake = NULL, 94 }; 95 96 #ifndef MAX_GIC_NR 97 #define MAX_GIC_NR 1 98 #endif 99 100 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; 101 102 #ifdef CONFIG_GIC_NON_BANKED 103 static void __iomem *gic_get_percpu_base(union gic_base *base) 104 { 105 return *__this_cpu_ptr(base->percpu_base); 106 } 107 108 static void __iomem *gic_get_common_base(union gic_base *base) 109 { 110 return base->common_base; 111 } 112 113 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 114 { 115 return data->get_base(&data->dist_base); 116 } 117 118 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 119 { 120 return data->get_base(&data->cpu_base); 121 } 122 123 static inline void gic_set_base_accessor(struct gic_chip_data *data, 124 void __iomem *(*f)(union gic_base *)) 125 { 126 data->get_base = f; 127 } 128 #else 129 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 130 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 131 #define gic_set_base_accessor(d, f) 132 #endif 133 134 static inline void __iomem *gic_dist_base(struct irq_data *d) 135 { 136 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 137 return gic_data_dist_base(gic_data); 138 } 139 140 static inline void __iomem *gic_cpu_base(struct irq_data *d) 141 { 142 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 143 return gic_data_cpu_base(gic_data); 144 } 145 146 static inline unsigned int gic_irq(struct irq_data *d) 147 { 148 return d->hwirq; 149 } 150 151 /* 152 * Routines to acknowledge, disable and enable interrupts 153 */ 154 static void gic_mask_irq(struct irq_data *d) 155 { 156 u32 mask = 1 << (gic_irq(d) % 32); 157 158 raw_spin_lock(&irq_controller_lock); 159 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4); 160 if (gic_arch_extn.irq_mask) 161 gic_arch_extn.irq_mask(d); 162 raw_spin_unlock(&irq_controller_lock); 163 } 164 165 static void gic_unmask_irq(struct irq_data *d) 166 { 167 u32 mask = 1 << (gic_irq(d) % 32); 168 169 raw_spin_lock(&irq_controller_lock); 170 if (gic_arch_extn.irq_unmask) 171 gic_arch_extn.irq_unmask(d); 172 writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4); 173 raw_spin_unlock(&irq_controller_lock); 174 } 175 176 static void gic_eoi_irq(struct irq_data *d) 177 { 178 if (gic_arch_extn.irq_eoi) { 179 raw_spin_lock(&irq_controller_lock); 180 gic_arch_extn.irq_eoi(d); 181 raw_spin_unlock(&irq_controller_lock); 182 } 183 184 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 185 } 186 187 static int gic_set_type(struct irq_data *d, unsigned int type) 188 { 189 void __iomem *base = gic_dist_base(d); 190 unsigned int gicirq = gic_irq(d); 191 u32 enablemask = 1 << (gicirq % 32); 192 u32 enableoff = (gicirq / 32) * 4; 193 u32 confmask = 0x2 << ((gicirq % 16) * 2); 194 u32 confoff = (gicirq / 16) * 4; 195 bool enabled = false; 196 u32 val; 197 198 /* Interrupt configuration for SGIs can't be changed */ 199 if (gicirq < 16) 200 return -EINVAL; 201 202 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 203 return -EINVAL; 204 205 raw_spin_lock(&irq_controller_lock); 206 207 if (gic_arch_extn.irq_set_type) 208 gic_arch_extn.irq_set_type(d, type); 209 210 val = readl_relaxed(base + GIC_DIST_CONFIG + confoff); 211 if (type == IRQ_TYPE_LEVEL_HIGH) 212 val &= ~confmask; 213 else if (type == IRQ_TYPE_EDGE_RISING) 214 val |= confmask; 215 216 /* 217 * As recommended by the spec, disable the interrupt before changing 218 * the configuration 219 */ 220 if (readl_relaxed(base + GIC_DIST_ENABLE_SET + enableoff) & enablemask) { 221 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_CLEAR + enableoff); 222 enabled = true; 223 } 224 225 writel_relaxed(val, base + GIC_DIST_CONFIG + confoff); 226 227 if (enabled) 228 writel_relaxed(enablemask, base + GIC_DIST_ENABLE_SET + enableoff); 229 230 raw_spin_unlock(&irq_controller_lock); 231 232 return 0; 233 } 234 235 static int gic_retrigger(struct irq_data *d) 236 { 237 if (gic_arch_extn.irq_retrigger) 238 return gic_arch_extn.irq_retrigger(d); 239 240 /* the genirq layer expects 0 if we can't retrigger in hardware */ 241 return 0; 242 } 243 244 #ifdef CONFIG_SMP 245 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 246 bool force) 247 { 248 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 249 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 250 u32 val, mask, bit; 251 252 if (!force) 253 cpu = cpumask_any_and(mask_val, cpu_online_mask); 254 else 255 cpu = cpumask_first(mask_val); 256 257 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 258 return -EINVAL; 259 260 raw_spin_lock(&irq_controller_lock); 261 mask = 0xff << shift; 262 bit = gic_cpu_map[cpu] << shift; 263 val = readl_relaxed(reg) & ~mask; 264 writel_relaxed(val | bit, reg); 265 raw_spin_unlock(&irq_controller_lock); 266 267 return IRQ_SET_MASK_OK; 268 } 269 #endif 270 271 #ifdef CONFIG_PM 272 static int gic_set_wake(struct irq_data *d, unsigned int on) 273 { 274 int ret = -ENXIO; 275 276 if (gic_arch_extn.irq_set_wake) 277 ret = gic_arch_extn.irq_set_wake(d, on); 278 279 return ret; 280 } 281 282 #else 283 #define gic_set_wake NULL 284 #endif 285 286 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 287 { 288 u32 irqstat, irqnr; 289 struct gic_chip_data *gic = &gic_data[0]; 290 void __iomem *cpu_base = gic_data_cpu_base(gic); 291 292 do { 293 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 294 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 295 296 if (likely(irqnr > 15 && irqnr < 1021)) { 297 irqnr = irq_find_mapping(gic->domain, irqnr); 298 handle_IRQ(irqnr, regs); 299 continue; 300 } 301 if (irqnr < 16) { 302 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 303 #ifdef CONFIG_SMP 304 handle_IPI(irqnr, regs); 305 #endif 306 continue; 307 } 308 break; 309 } while (1); 310 } 311 312 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 313 { 314 struct gic_chip_data *chip_data = irq_get_handler_data(irq); 315 struct irq_chip *chip = irq_get_chip(irq); 316 unsigned int cascade_irq, gic_irq; 317 unsigned long status; 318 319 chained_irq_enter(chip, desc); 320 321 raw_spin_lock(&irq_controller_lock); 322 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 323 raw_spin_unlock(&irq_controller_lock); 324 325 gic_irq = (status & 0x3ff); 326 if (gic_irq == 1023) 327 goto out; 328 329 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 330 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 331 handle_bad_irq(cascade_irq, desc); 332 else 333 generic_handle_irq(cascade_irq); 334 335 out: 336 chained_irq_exit(chip, desc); 337 } 338 339 static struct irq_chip gic_chip = { 340 .name = "GIC", 341 .irq_mask = gic_mask_irq, 342 .irq_unmask = gic_unmask_irq, 343 .irq_eoi = gic_eoi_irq, 344 .irq_set_type = gic_set_type, 345 .irq_retrigger = gic_retrigger, 346 #ifdef CONFIG_SMP 347 .irq_set_affinity = gic_set_affinity, 348 #endif 349 .irq_set_wake = gic_set_wake, 350 }; 351 352 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 353 { 354 if (gic_nr >= MAX_GIC_NR) 355 BUG(); 356 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) 357 BUG(); 358 irq_set_chained_handler(irq, gic_handle_cascade_irq); 359 } 360 361 static u8 gic_get_cpumask(struct gic_chip_data *gic) 362 { 363 void __iomem *base = gic_data_dist_base(gic); 364 u32 mask, i; 365 366 for (i = mask = 0; i < 32; i += 4) { 367 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 368 mask |= mask >> 16; 369 mask |= mask >> 8; 370 if (mask) 371 break; 372 } 373 374 if (!mask) 375 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 376 377 return mask; 378 } 379 380 static void __init gic_dist_init(struct gic_chip_data *gic) 381 { 382 unsigned int i; 383 u32 cpumask; 384 unsigned int gic_irqs = gic->gic_irqs; 385 void __iomem *base = gic_data_dist_base(gic); 386 387 writel_relaxed(0, base + GIC_DIST_CTRL); 388 389 /* 390 * Set all global interrupts to be level triggered, active low. 391 */ 392 for (i = 32; i < gic_irqs; i += 16) 393 writel_relaxed(0, base + GIC_DIST_CONFIG + i * 4 / 16); 394 395 /* 396 * Set all global interrupts to this CPU only. 397 */ 398 cpumask = gic_get_cpumask(gic); 399 cpumask |= cpumask << 8; 400 cpumask |= cpumask << 16; 401 for (i = 32; i < gic_irqs; i += 4) 402 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 403 404 /* 405 * Set priority on all global interrupts. 406 */ 407 for (i = 32; i < gic_irqs; i += 4) 408 writel_relaxed(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4); 409 410 /* 411 * Disable all interrupts. Leave the PPI and SGIs alone 412 * as these enables are banked registers. 413 */ 414 for (i = 32; i < gic_irqs; i += 32) 415 writel_relaxed(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32); 416 417 writel_relaxed(1, base + GIC_DIST_CTRL); 418 } 419 420 static void gic_cpu_init(struct gic_chip_data *gic) 421 { 422 void __iomem *dist_base = gic_data_dist_base(gic); 423 void __iomem *base = gic_data_cpu_base(gic); 424 unsigned int cpu_mask, cpu = smp_processor_id(); 425 int i; 426 427 /* 428 * Get what the GIC says our CPU mask is. 429 */ 430 BUG_ON(cpu >= NR_GIC_CPU_IF); 431 cpu_mask = gic_get_cpumask(gic); 432 gic_cpu_map[cpu] = cpu_mask; 433 434 /* 435 * Clear our mask from the other map entries in case they're 436 * still undefined. 437 */ 438 for (i = 0; i < NR_GIC_CPU_IF; i++) 439 if (i != cpu) 440 gic_cpu_map[i] &= ~cpu_mask; 441 442 /* 443 * Deal with the banked PPI and SGI interrupts - disable all 444 * PPI interrupts, ensure all SGI interrupts are enabled. 445 */ 446 writel_relaxed(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR); 447 writel_relaxed(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET); 448 449 /* 450 * Set priority on PPI and SGI interrupts 451 */ 452 for (i = 0; i < 32; i += 4) 453 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4); 454 455 writel_relaxed(0xf0, base + GIC_CPU_PRIMASK); 456 writel_relaxed(1, base + GIC_CPU_CTRL); 457 } 458 459 void gic_cpu_if_down(void) 460 { 461 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 462 writel_relaxed(0, cpu_base + GIC_CPU_CTRL); 463 } 464 465 #ifdef CONFIG_CPU_PM 466 /* 467 * Saves the GIC distributor registers during suspend or idle. Must be called 468 * with interrupts disabled but before powering down the GIC. After calling 469 * this function, no interrupts will be delivered by the GIC, and another 470 * platform-specific wakeup source must be enabled. 471 */ 472 static void gic_dist_save(unsigned int gic_nr) 473 { 474 unsigned int gic_irqs; 475 void __iomem *dist_base; 476 int i; 477 478 if (gic_nr >= MAX_GIC_NR) 479 BUG(); 480 481 gic_irqs = gic_data[gic_nr].gic_irqs; 482 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 483 484 if (!dist_base) 485 return; 486 487 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 488 gic_data[gic_nr].saved_spi_conf[i] = 489 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 490 491 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 492 gic_data[gic_nr].saved_spi_target[i] = 493 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 494 495 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 496 gic_data[gic_nr].saved_spi_enable[i] = 497 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 498 } 499 500 /* 501 * Restores the GIC distributor registers during resume or when coming out of 502 * idle. Must be called before enabling interrupts. If a level interrupt 503 * that occured while the GIC was suspended is still present, it will be 504 * handled normally, but any edge interrupts that occured will not be seen by 505 * the GIC and need to be handled by the platform-specific wakeup source. 506 */ 507 static void gic_dist_restore(unsigned int gic_nr) 508 { 509 unsigned int gic_irqs; 510 unsigned int i; 511 void __iomem *dist_base; 512 513 if (gic_nr >= MAX_GIC_NR) 514 BUG(); 515 516 gic_irqs = gic_data[gic_nr].gic_irqs; 517 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 518 519 if (!dist_base) 520 return; 521 522 writel_relaxed(0, dist_base + GIC_DIST_CTRL); 523 524 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 525 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], 526 dist_base + GIC_DIST_CONFIG + i * 4); 527 528 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 529 writel_relaxed(0xa0a0a0a0, 530 dist_base + GIC_DIST_PRI + i * 4); 531 532 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 533 writel_relaxed(gic_data[gic_nr].saved_spi_target[i], 534 dist_base + GIC_DIST_TARGET + i * 4); 535 536 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 537 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], 538 dist_base + GIC_DIST_ENABLE_SET + i * 4); 539 540 writel_relaxed(1, dist_base + GIC_DIST_CTRL); 541 } 542 543 static void gic_cpu_save(unsigned int gic_nr) 544 { 545 int i; 546 u32 *ptr; 547 void __iomem *dist_base; 548 void __iomem *cpu_base; 549 550 if (gic_nr >= MAX_GIC_NR) 551 BUG(); 552 553 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 554 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 555 556 if (!dist_base || !cpu_base) 557 return; 558 559 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 560 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 561 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 562 563 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 564 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 565 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 566 567 } 568 569 static void gic_cpu_restore(unsigned int gic_nr) 570 { 571 int i; 572 u32 *ptr; 573 void __iomem *dist_base; 574 void __iomem *cpu_base; 575 576 if (gic_nr >= MAX_GIC_NR) 577 BUG(); 578 579 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 580 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 581 582 if (!dist_base || !cpu_base) 583 return; 584 585 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 586 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 587 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 588 589 ptr = __this_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 590 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 591 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 592 593 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 594 writel_relaxed(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4); 595 596 writel_relaxed(0xf0, cpu_base + GIC_CPU_PRIMASK); 597 writel_relaxed(1, cpu_base + GIC_CPU_CTRL); 598 } 599 600 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 601 { 602 int i; 603 604 for (i = 0; i < MAX_GIC_NR; i++) { 605 #ifdef CONFIG_GIC_NON_BANKED 606 /* Skip over unused GICs */ 607 if (!gic_data[i].get_base) 608 continue; 609 #endif 610 switch (cmd) { 611 case CPU_PM_ENTER: 612 gic_cpu_save(i); 613 break; 614 case CPU_PM_ENTER_FAILED: 615 case CPU_PM_EXIT: 616 gic_cpu_restore(i); 617 break; 618 case CPU_CLUSTER_PM_ENTER: 619 gic_dist_save(i); 620 break; 621 case CPU_CLUSTER_PM_ENTER_FAILED: 622 case CPU_CLUSTER_PM_EXIT: 623 gic_dist_restore(i); 624 break; 625 } 626 } 627 628 return NOTIFY_OK; 629 } 630 631 static struct notifier_block gic_notifier_block = { 632 .notifier_call = gic_notifier, 633 }; 634 635 static void __init gic_pm_init(struct gic_chip_data *gic) 636 { 637 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 638 sizeof(u32)); 639 BUG_ON(!gic->saved_ppi_enable); 640 641 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 642 sizeof(u32)); 643 BUG_ON(!gic->saved_ppi_conf); 644 645 if (gic == &gic_data[0]) 646 cpu_pm_register_notifier(&gic_notifier_block); 647 } 648 #else 649 static void __init gic_pm_init(struct gic_chip_data *gic) 650 { 651 } 652 #endif 653 654 #ifdef CONFIG_SMP 655 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 656 { 657 int cpu; 658 unsigned long flags, map = 0; 659 660 raw_spin_lock_irqsave(&irq_controller_lock, flags); 661 662 /* Convert our logical CPU mask into a physical one. */ 663 for_each_cpu(cpu, mask) 664 map |= gic_cpu_map[cpu]; 665 666 /* 667 * Ensure that stores to Normal memory are visible to the 668 * other CPUs before they observe us issuing the IPI. 669 */ 670 dmb(ishst); 671 672 /* this always happens on GIC0 */ 673 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 674 675 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 676 } 677 #endif 678 679 #ifdef CONFIG_BL_SWITCHER 680 /* 681 * gic_send_sgi - send a SGI directly to given CPU interface number 682 * 683 * cpu_id: the ID for the destination CPU interface 684 * irq: the IPI number to send a SGI for 685 */ 686 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 687 { 688 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 689 cpu_id = 1 << cpu_id; 690 /* this always happens on GIC0 */ 691 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 692 } 693 694 /* 695 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 696 * 697 * @cpu: the logical CPU number to get the GIC ID for. 698 * 699 * Return the CPU interface ID for the given logical CPU number, 700 * or -1 if the CPU number is too large or the interface ID is 701 * unknown (more than one bit set). 702 */ 703 int gic_get_cpu_id(unsigned int cpu) 704 { 705 unsigned int cpu_bit; 706 707 if (cpu >= NR_GIC_CPU_IF) 708 return -1; 709 cpu_bit = gic_cpu_map[cpu]; 710 if (cpu_bit & (cpu_bit - 1)) 711 return -1; 712 return __ffs(cpu_bit); 713 } 714 715 /* 716 * gic_migrate_target - migrate IRQs to another CPU interface 717 * 718 * @new_cpu_id: the CPU target ID to migrate IRQs to 719 * 720 * Migrate all peripheral interrupts with a target matching the current CPU 721 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 722 * is also updated. Targets to other CPU interfaces are unchanged. 723 * This must be called with IRQs locally disabled. 724 */ 725 void gic_migrate_target(unsigned int new_cpu_id) 726 { 727 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 728 void __iomem *dist_base; 729 int i, ror_val, cpu = smp_processor_id(); 730 u32 val, cur_target_mask, active_mask; 731 732 if (gic_nr >= MAX_GIC_NR) 733 BUG(); 734 735 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 736 if (!dist_base) 737 return; 738 gic_irqs = gic_data[gic_nr].gic_irqs; 739 740 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 741 cur_target_mask = 0x01010101 << cur_cpu_id; 742 ror_val = (cur_cpu_id - new_cpu_id) & 31; 743 744 raw_spin_lock(&irq_controller_lock); 745 746 /* Update the target interface for this logical CPU */ 747 gic_cpu_map[cpu] = 1 << new_cpu_id; 748 749 /* 750 * Find all the peripheral interrupts targetting the current 751 * CPU interface and migrate them to the new CPU interface. 752 * We skip DIST_TARGET 0 to 7 as they are read-only. 753 */ 754 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 755 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 756 active_mask = val & cur_target_mask; 757 if (active_mask) { 758 val &= ~active_mask; 759 val |= ror32(active_mask, ror_val); 760 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 761 } 762 } 763 764 raw_spin_unlock(&irq_controller_lock); 765 766 /* 767 * Now let's migrate and clear any potential SGIs that might be 768 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 769 * is a banked register, we can only forward the SGI using 770 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 771 * doesn't use that information anyway. 772 * 773 * For the same reason we do not adjust SGI source information 774 * for previously sent SGIs by us to other CPUs either. 775 */ 776 for (i = 0; i < 16; i += 4) { 777 int j; 778 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 779 if (!val) 780 continue; 781 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 782 for (j = i; j < i + 4; j++) { 783 if (val & 0xff) 784 writel_relaxed((1 << (new_cpu_id + 16)) | j, 785 dist_base + GIC_DIST_SOFTINT); 786 val >>= 8; 787 } 788 } 789 } 790 791 /* 792 * gic_get_sgir_physaddr - get the physical address for the SGI register 793 * 794 * REturn the physical address of the SGI register to be used 795 * by some early assembly code when the kernel is not yet available. 796 */ 797 static unsigned long gic_dist_physaddr; 798 799 unsigned long gic_get_sgir_physaddr(void) 800 { 801 if (!gic_dist_physaddr) 802 return 0; 803 return gic_dist_physaddr + GIC_DIST_SOFTINT; 804 } 805 806 void __init gic_init_physaddr(struct device_node *node) 807 { 808 struct resource res; 809 if (of_address_to_resource(node, 0, &res) == 0) { 810 gic_dist_physaddr = res.start; 811 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 812 } 813 } 814 815 #else 816 #define gic_init_physaddr(node) do { } while (0) 817 #endif 818 819 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 820 irq_hw_number_t hw) 821 { 822 if (hw < 32) { 823 irq_set_percpu_devid(irq); 824 irq_set_chip_and_handler(irq, &gic_chip, 825 handle_percpu_devid_irq); 826 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 827 } else { 828 irq_set_chip_and_handler(irq, &gic_chip, 829 handle_fasteoi_irq); 830 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 831 832 gic_routable_irq_domain_ops->map(d, irq, hw); 833 } 834 irq_set_chip_data(irq, d->host_data); 835 return 0; 836 } 837 838 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 839 { 840 gic_routable_irq_domain_ops->unmap(d, irq); 841 } 842 843 static int gic_irq_domain_xlate(struct irq_domain *d, 844 struct device_node *controller, 845 const u32 *intspec, unsigned int intsize, 846 unsigned long *out_hwirq, unsigned int *out_type) 847 { 848 unsigned long ret = 0; 849 850 if (d->of_node != controller) 851 return -EINVAL; 852 if (intsize < 3) 853 return -EINVAL; 854 855 /* Get the interrupt number and add 16 to skip over SGIs */ 856 *out_hwirq = intspec[1] + 16; 857 858 /* For SPIs, we need to add 16 more to get the GIC irq ID number */ 859 if (!intspec[0]) { 860 ret = gic_routable_irq_domain_ops->xlate(d, controller, 861 intspec, 862 intsize, 863 out_hwirq, 864 out_type); 865 866 if (IS_ERR_VALUE(ret)) 867 return ret; 868 } 869 870 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 871 872 return ret; 873 } 874 875 #ifdef CONFIG_SMP 876 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, 877 void *hcpu) 878 { 879 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 880 gic_cpu_init(&gic_data[0]); 881 return NOTIFY_OK; 882 } 883 884 /* 885 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 886 * priority because the GIC needs to be up before the ARM generic timers. 887 */ 888 static struct notifier_block gic_cpu_notifier = { 889 .notifier_call = gic_secondary_init, 890 .priority = 100, 891 }; 892 #endif 893 894 static const struct irq_domain_ops gic_irq_domain_ops = { 895 .map = gic_irq_domain_map, 896 .unmap = gic_irq_domain_unmap, 897 .xlate = gic_irq_domain_xlate, 898 }; 899 900 /* Default functions for routable irq domain */ 901 static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq, 902 irq_hw_number_t hw) 903 { 904 return 0; 905 } 906 907 static void gic_routable_irq_domain_unmap(struct irq_domain *d, 908 unsigned int irq) 909 { 910 } 911 912 static int gic_routable_irq_domain_xlate(struct irq_domain *d, 913 struct device_node *controller, 914 const u32 *intspec, unsigned int intsize, 915 unsigned long *out_hwirq, 916 unsigned int *out_type) 917 { 918 *out_hwirq += 16; 919 return 0; 920 } 921 922 const struct irq_domain_ops gic_default_routable_irq_domain_ops = { 923 .map = gic_routable_irq_domain_map, 924 .unmap = gic_routable_irq_domain_unmap, 925 .xlate = gic_routable_irq_domain_xlate, 926 }; 927 928 const struct irq_domain_ops *gic_routable_irq_domain_ops = 929 &gic_default_routable_irq_domain_ops; 930 931 void __init gic_init_bases(unsigned int gic_nr, int irq_start, 932 void __iomem *dist_base, void __iomem *cpu_base, 933 u32 percpu_offset, struct device_node *node) 934 { 935 irq_hw_number_t hwirq_base; 936 struct gic_chip_data *gic; 937 int gic_irqs, irq_base, i; 938 int nr_routable_irqs; 939 940 BUG_ON(gic_nr >= MAX_GIC_NR); 941 942 gic = &gic_data[gic_nr]; 943 #ifdef CONFIG_GIC_NON_BANKED 944 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 945 unsigned int cpu; 946 947 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 948 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 949 if (WARN_ON(!gic->dist_base.percpu_base || 950 !gic->cpu_base.percpu_base)) { 951 free_percpu(gic->dist_base.percpu_base); 952 free_percpu(gic->cpu_base.percpu_base); 953 return; 954 } 955 956 for_each_possible_cpu(cpu) { 957 unsigned long offset = percpu_offset * cpu_logical_map(cpu); 958 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; 959 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; 960 } 961 962 gic_set_base_accessor(gic, gic_get_percpu_base); 963 } else 964 #endif 965 { /* Normal, sane GIC... */ 966 WARN(percpu_offset, 967 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 968 percpu_offset); 969 gic->dist_base.common_base = dist_base; 970 gic->cpu_base.common_base = cpu_base; 971 gic_set_base_accessor(gic, gic_get_common_base); 972 } 973 974 /* 975 * Initialize the CPU interface map to all CPUs. 976 * It will be refined as each CPU probes its ID. 977 */ 978 for (i = 0; i < NR_GIC_CPU_IF; i++) 979 gic_cpu_map[i] = 0xff; 980 981 /* 982 * For primary GICs, skip over SGIs. 983 * For secondary GICs, skip over PPIs, too. 984 */ 985 if (gic_nr == 0 && (irq_start & 31) > 0) { 986 hwirq_base = 16; 987 if (irq_start != -1) 988 irq_start = (irq_start & ~31) + 16; 989 } else { 990 hwirq_base = 32; 991 } 992 993 /* 994 * Find out how many interrupts are supported. 995 * The GIC only supports up to 1020 interrupt sources. 996 */ 997 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 998 gic_irqs = (gic_irqs + 1) * 32; 999 if (gic_irqs > 1020) 1000 gic_irqs = 1020; 1001 gic->gic_irqs = gic_irqs; 1002 1003 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 1004 1005 if (of_property_read_u32(node, "arm,routable-irqs", 1006 &nr_routable_irqs)) { 1007 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 1008 numa_node_id()); 1009 if (IS_ERR_VALUE(irq_base)) { 1010 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 1011 irq_start); 1012 irq_base = irq_start; 1013 } 1014 1015 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, 1016 hwirq_base, &gic_irq_domain_ops, gic); 1017 } else { 1018 gic->domain = irq_domain_add_linear(node, nr_routable_irqs, 1019 &gic_irq_domain_ops, 1020 gic); 1021 } 1022 1023 if (WARN_ON(!gic->domain)) 1024 return; 1025 1026 if (gic_nr == 0) { 1027 #ifdef CONFIG_SMP 1028 set_smp_cross_call(gic_raise_softirq); 1029 register_cpu_notifier(&gic_cpu_notifier); 1030 #endif 1031 set_handle_irq(gic_handle_irq); 1032 } 1033 1034 gic_chip.flags |= gic_arch_extn.flags; 1035 gic_dist_init(gic); 1036 gic_cpu_init(gic); 1037 gic_pm_init(gic); 1038 } 1039 1040 #ifdef CONFIG_OF 1041 static int gic_cnt __initdata; 1042 1043 static int __init 1044 gic_of_init(struct device_node *node, struct device_node *parent) 1045 { 1046 void __iomem *cpu_base; 1047 void __iomem *dist_base; 1048 u32 percpu_offset; 1049 int irq; 1050 1051 if (WARN_ON(!node)) 1052 return -ENODEV; 1053 1054 dist_base = of_iomap(node, 0); 1055 WARN(!dist_base, "unable to map gic dist registers\n"); 1056 1057 cpu_base = of_iomap(node, 1); 1058 WARN(!cpu_base, "unable to map gic cpu registers\n"); 1059 1060 if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) 1061 percpu_offset = 0; 1062 1063 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); 1064 if (!gic_cnt) 1065 gic_init_physaddr(node); 1066 1067 if (parent) { 1068 irq = irq_of_parse_and_map(node, 0); 1069 gic_cascade_irq(gic_cnt, irq); 1070 } 1071 gic_cnt++; 1072 return 0; 1073 } 1074 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1075 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1076 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1077 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1078 1079 #endif 1080