1 /* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Interrupt architecture for the GIC: 9 * 10 * o There is one Interrupt Distributor, which receives interrupts 11 * from system devices and sends them to the Interrupt Controllers. 12 * 13 * o There is one CPU Interface per CPU, which sends interrupts sent 14 * by the Distributor, and interrupts generated locally, to the 15 * associated CPU. The base address of the CPU interface is usually 16 * aliased so that the same address points to different chips depending 17 * on the CPU it is accessed from. 18 * 19 * Note that IRQs 0-31 are special - they are local to each CPU. 20 * As such, the enable set/clear, pending set/clear and active bit 21 * registers are banked per-cpu for these sources. 22 */ 23 #include <linux/init.h> 24 #include <linux/kernel.h> 25 #include <linux/err.h> 26 #include <linux/module.h> 27 #include <linux/list.h> 28 #include <linux/smp.h> 29 #include <linux/cpu.h> 30 #include <linux/cpu_pm.h> 31 #include <linux/cpumask.h> 32 #include <linux/io.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/acpi.h> 37 #include <linux/irqdomain.h> 38 #include <linux/interrupt.h> 39 #include <linux/percpu.h> 40 #include <linux/slab.h> 41 #include <linux/irqchip.h> 42 #include <linux/irqchip/chained_irq.h> 43 #include <linux/irqchip/arm-gic.h> 44 45 #include <asm/cputype.h> 46 #include <asm/irq.h> 47 #include <asm/exception.h> 48 #include <asm/smp_plat.h> 49 #include <asm/virt.h> 50 51 #include "irq-gic-common.h" 52 53 #ifdef CONFIG_ARM64 54 #include <asm/cpufeature.h> 55 56 static void gic_check_cpu_features(void) 57 { 58 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), 59 TAINT_CPU_OUT_OF_SPEC, 60 "GICv3 system registers enabled, broken firmware!\n"); 61 } 62 #else 63 #define gic_check_cpu_features() do { } while(0) 64 #endif 65 66 union gic_base { 67 void __iomem *common_base; 68 void __percpu * __iomem *percpu_base; 69 }; 70 71 struct gic_chip_data { 72 struct irq_chip chip; 73 union gic_base dist_base; 74 union gic_base cpu_base; 75 void __iomem *raw_dist_base; 76 void __iomem *raw_cpu_base; 77 u32 percpu_offset; 78 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 79 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 80 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 81 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 82 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 83 u32 __percpu *saved_ppi_enable; 84 u32 __percpu *saved_ppi_active; 85 u32 __percpu *saved_ppi_conf; 86 #endif 87 struct irq_domain *domain; 88 unsigned int gic_irqs; 89 #ifdef CONFIG_GIC_NON_BANKED 90 void __iomem *(*get_base)(union gic_base *); 91 #endif 92 }; 93 94 #ifdef CONFIG_BL_SWITCHER 95 96 static DEFINE_RAW_SPINLOCK(cpu_map_lock); 97 98 #define gic_lock_irqsave(f) \ 99 raw_spin_lock_irqsave(&cpu_map_lock, (f)) 100 #define gic_unlock_irqrestore(f) \ 101 raw_spin_unlock_irqrestore(&cpu_map_lock, (f)) 102 103 #define gic_lock() raw_spin_lock(&cpu_map_lock) 104 #define gic_unlock() raw_spin_unlock(&cpu_map_lock) 105 106 #else 107 108 #define gic_lock_irqsave(f) do { (void)(f); } while(0) 109 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0) 110 111 #define gic_lock() do { } while(0) 112 #define gic_unlock() do { } while(0) 113 114 #endif 115 116 /* 117 * The GIC mapping of CPU interfaces does not necessarily match 118 * the logical CPU numbering. Let's use a mapping as returned 119 * by the GIC itself. 120 */ 121 #define NR_GIC_CPU_IF 8 122 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 123 124 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 125 126 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; 127 128 static struct gic_kvm_info gic_v2_kvm_info; 129 130 #ifdef CONFIG_GIC_NON_BANKED 131 static void __iomem *gic_get_percpu_base(union gic_base *base) 132 { 133 return raw_cpu_read(*base->percpu_base); 134 } 135 136 static void __iomem *gic_get_common_base(union gic_base *base) 137 { 138 return base->common_base; 139 } 140 141 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 142 { 143 return data->get_base(&data->dist_base); 144 } 145 146 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 147 { 148 return data->get_base(&data->cpu_base); 149 } 150 151 static inline void gic_set_base_accessor(struct gic_chip_data *data, 152 void __iomem *(*f)(union gic_base *)) 153 { 154 data->get_base = f; 155 } 156 #else 157 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 158 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 159 #define gic_set_base_accessor(d, f) 160 #endif 161 162 static inline void __iomem *gic_dist_base(struct irq_data *d) 163 { 164 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 165 return gic_data_dist_base(gic_data); 166 } 167 168 static inline void __iomem *gic_cpu_base(struct irq_data *d) 169 { 170 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 171 return gic_data_cpu_base(gic_data); 172 } 173 174 static inline unsigned int gic_irq(struct irq_data *d) 175 { 176 return d->hwirq; 177 } 178 179 static inline bool cascading_gic_irq(struct irq_data *d) 180 { 181 void *data = irq_data_get_irq_handler_data(d); 182 183 /* 184 * If handler_data is set, this is a cascading interrupt, and 185 * it cannot possibly be forwarded. 186 */ 187 return data != NULL; 188 } 189 190 /* 191 * Routines to acknowledge, disable and enable interrupts 192 */ 193 static void gic_poke_irq(struct irq_data *d, u32 offset) 194 { 195 u32 mask = 1 << (gic_irq(d) % 32); 196 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 197 } 198 199 static int gic_peek_irq(struct irq_data *d, u32 offset) 200 { 201 u32 mask = 1 << (gic_irq(d) % 32); 202 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 203 } 204 205 static void gic_mask_irq(struct irq_data *d) 206 { 207 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 208 } 209 210 static void gic_eoimode1_mask_irq(struct irq_data *d) 211 { 212 gic_mask_irq(d); 213 /* 214 * When masking a forwarded interrupt, make sure it is 215 * deactivated as well. 216 * 217 * This ensures that an interrupt that is getting 218 * disabled/masked will not get "stuck", because there is 219 * noone to deactivate it (guest is being terminated). 220 */ 221 if (irqd_is_forwarded_to_vcpu(d)) 222 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); 223 } 224 225 static void gic_unmask_irq(struct irq_data *d) 226 { 227 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 228 } 229 230 static void gic_eoi_irq(struct irq_data *d) 231 { 232 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 233 } 234 235 static void gic_eoimode1_eoi_irq(struct irq_data *d) 236 { 237 /* Do not deactivate an IRQ forwarded to a vcpu. */ 238 if (irqd_is_forwarded_to_vcpu(d)) 239 return; 240 241 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); 242 } 243 244 static int gic_irq_set_irqchip_state(struct irq_data *d, 245 enum irqchip_irq_state which, bool val) 246 { 247 u32 reg; 248 249 switch (which) { 250 case IRQCHIP_STATE_PENDING: 251 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 252 break; 253 254 case IRQCHIP_STATE_ACTIVE: 255 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 256 break; 257 258 case IRQCHIP_STATE_MASKED: 259 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 260 break; 261 262 default: 263 return -EINVAL; 264 } 265 266 gic_poke_irq(d, reg); 267 return 0; 268 } 269 270 static int gic_irq_get_irqchip_state(struct irq_data *d, 271 enum irqchip_irq_state which, bool *val) 272 { 273 switch (which) { 274 case IRQCHIP_STATE_PENDING: 275 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 276 break; 277 278 case IRQCHIP_STATE_ACTIVE: 279 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 280 break; 281 282 case IRQCHIP_STATE_MASKED: 283 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 284 break; 285 286 default: 287 return -EINVAL; 288 } 289 290 return 0; 291 } 292 293 static int gic_set_type(struct irq_data *d, unsigned int type) 294 { 295 void __iomem *base = gic_dist_base(d); 296 unsigned int gicirq = gic_irq(d); 297 298 /* Interrupt configuration for SGIs can't be changed */ 299 if (gicirq < 16) 300 return -EINVAL; 301 302 /* SPIs have restrictions on the supported types */ 303 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 304 type != IRQ_TYPE_EDGE_RISING) 305 return -EINVAL; 306 307 return gic_configure_irq(gicirq, type, base, NULL); 308 } 309 310 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 311 { 312 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ 313 if (cascading_gic_irq(d)) 314 return -EINVAL; 315 316 if (vcpu) 317 irqd_set_forwarded_to_vcpu(d); 318 else 319 irqd_clr_forwarded_to_vcpu(d); 320 return 0; 321 } 322 323 #ifdef CONFIG_SMP 324 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 325 bool force) 326 { 327 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 328 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 329 u32 val, mask, bit; 330 unsigned long flags; 331 332 if (!force) 333 cpu = cpumask_any_and(mask_val, cpu_online_mask); 334 else 335 cpu = cpumask_first(mask_val); 336 337 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 338 return -EINVAL; 339 340 gic_lock_irqsave(flags); 341 mask = 0xff << shift; 342 bit = gic_cpu_map[cpu] << shift; 343 val = readl_relaxed(reg) & ~mask; 344 writel_relaxed(val | bit, reg); 345 gic_unlock_irqrestore(flags); 346 347 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 348 349 return IRQ_SET_MASK_OK_DONE; 350 } 351 #endif 352 353 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 354 { 355 u32 irqstat, irqnr; 356 struct gic_chip_data *gic = &gic_data[0]; 357 void __iomem *cpu_base = gic_data_cpu_base(gic); 358 359 do { 360 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 361 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 362 363 if (likely(irqnr > 15 && irqnr < 1020)) { 364 if (static_key_true(&supports_deactivate)) 365 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 366 isb(); 367 handle_domain_irq(gic->domain, irqnr, regs); 368 continue; 369 } 370 if (irqnr < 16) { 371 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 372 if (static_key_true(&supports_deactivate)) 373 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); 374 #ifdef CONFIG_SMP 375 /* 376 * Ensure any shared data written by the CPU sending 377 * the IPI is read after we've read the ACK register 378 * on the GIC. 379 * 380 * Pairs with the write barrier in gic_raise_softirq 381 */ 382 smp_rmb(); 383 handle_IPI(irqnr, regs); 384 #endif 385 continue; 386 } 387 break; 388 } while (1); 389 } 390 391 static void gic_handle_cascade_irq(struct irq_desc *desc) 392 { 393 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); 394 struct irq_chip *chip = irq_desc_get_chip(desc); 395 unsigned int cascade_irq, gic_irq; 396 unsigned long status; 397 398 chained_irq_enter(chip, desc); 399 400 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 401 402 gic_irq = (status & GICC_IAR_INT_ID_MASK); 403 if (gic_irq == GICC_INT_SPURIOUS) 404 goto out; 405 406 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 407 if (unlikely(gic_irq < 32 || gic_irq > 1020)) { 408 handle_bad_irq(desc); 409 } else { 410 isb(); 411 generic_handle_irq(cascade_irq); 412 } 413 414 out: 415 chained_irq_exit(chip, desc); 416 } 417 418 static const struct irq_chip gic_chip = { 419 .irq_mask = gic_mask_irq, 420 .irq_unmask = gic_unmask_irq, 421 .irq_eoi = gic_eoi_irq, 422 .irq_set_type = gic_set_type, 423 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 424 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 425 .flags = IRQCHIP_SET_TYPE_MASKED | 426 IRQCHIP_SKIP_SET_WAKE | 427 IRQCHIP_MASK_ON_SUSPEND, 428 }; 429 430 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 431 { 432 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 433 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, 434 &gic_data[gic_nr]); 435 } 436 437 static u8 gic_get_cpumask(struct gic_chip_data *gic) 438 { 439 void __iomem *base = gic_data_dist_base(gic); 440 u32 mask, i; 441 442 for (i = mask = 0; i < 32; i += 4) { 443 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 444 mask |= mask >> 16; 445 mask |= mask >> 8; 446 if (mask) 447 break; 448 } 449 450 if (!mask && num_possible_cpus() > 1) 451 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 452 453 return mask; 454 } 455 456 static void gic_cpu_if_up(struct gic_chip_data *gic) 457 { 458 void __iomem *cpu_base = gic_data_cpu_base(gic); 459 u32 bypass = 0; 460 u32 mode = 0; 461 462 if (gic == &gic_data[0] && static_key_true(&supports_deactivate)) 463 mode = GIC_CPU_CTRL_EOImodeNS; 464 465 /* 466 * Preserve bypass disable bits to be written back later 467 */ 468 bypass = readl(cpu_base + GIC_CPU_CTRL); 469 bypass &= GICC_DIS_BYPASS_MASK; 470 471 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 472 } 473 474 475 static void gic_dist_init(struct gic_chip_data *gic) 476 { 477 unsigned int i; 478 u32 cpumask; 479 unsigned int gic_irqs = gic->gic_irqs; 480 void __iomem *base = gic_data_dist_base(gic); 481 482 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 483 484 /* 485 * Set all global interrupts to this CPU only. 486 */ 487 cpumask = gic_get_cpumask(gic); 488 cpumask |= cpumask << 8; 489 cpumask |= cpumask << 16; 490 for (i = 32; i < gic_irqs; i += 4) 491 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 492 493 gic_dist_config(base, gic_irqs, NULL); 494 495 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 496 } 497 498 static int gic_cpu_init(struct gic_chip_data *gic) 499 { 500 void __iomem *dist_base = gic_data_dist_base(gic); 501 void __iomem *base = gic_data_cpu_base(gic); 502 unsigned int cpu_mask, cpu = smp_processor_id(); 503 int i; 504 505 /* 506 * Setting up the CPU map is only relevant for the primary GIC 507 * because any nested/secondary GICs do not directly interface 508 * with the CPU(s). 509 */ 510 if (gic == &gic_data[0]) { 511 /* 512 * Get what the GIC says our CPU mask is. 513 */ 514 if (WARN_ON(cpu >= NR_GIC_CPU_IF)) 515 return -EINVAL; 516 517 gic_check_cpu_features(); 518 cpu_mask = gic_get_cpumask(gic); 519 gic_cpu_map[cpu] = cpu_mask; 520 521 /* 522 * Clear our mask from the other map entries in case they're 523 * still undefined. 524 */ 525 for (i = 0; i < NR_GIC_CPU_IF; i++) 526 if (i != cpu) 527 gic_cpu_map[i] &= ~cpu_mask; 528 } 529 530 gic_cpu_config(dist_base, NULL); 531 532 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 533 gic_cpu_if_up(gic); 534 535 return 0; 536 } 537 538 int gic_cpu_if_down(unsigned int gic_nr) 539 { 540 void __iomem *cpu_base; 541 u32 val = 0; 542 543 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) 544 return -EINVAL; 545 546 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 547 val = readl(cpu_base + GIC_CPU_CTRL); 548 val &= ~GICC_ENABLE; 549 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 550 551 return 0; 552 } 553 554 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 555 /* 556 * Saves the GIC distributor registers during suspend or idle. Must be called 557 * with interrupts disabled but before powering down the GIC. After calling 558 * this function, no interrupts will be delivered by the GIC, and another 559 * platform-specific wakeup source must be enabled. 560 */ 561 void gic_dist_save(struct gic_chip_data *gic) 562 { 563 unsigned int gic_irqs; 564 void __iomem *dist_base; 565 int i; 566 567 if (WARN_ON(!gic)) 568 return; 569 570 gic_irqs = gic->gic_irqs; 571 dist_base = gic_data_dist_base(gic); 572 573 if (!dist_base) 574 return; 575 576 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 577 gic->saved_spi_conf[i] = 578 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 579 580 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 581 gic->saved_spi_target[i] = 582 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 583 584 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 585 gic->saved_spi_enable[i] = 586 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 587 588 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 589 gic->saved_spi_active[i] = 590 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 591 } 592 593 /* 594 * Restores the GIC distributor registers during resume or when coming out of 595 * idle. Must be called before enabling interrupts. If a level interrupt 596 * that occured while the GIC was suspended is still present, it will be 597 * handled normally, but any edge interrupts that occured will not be seen by 598 * the GIC and need to be handled by the platform-specific wakeup source. 599 */ 600 void gic_dist_restore(struct gic_chip_data *gic) 601 { 602 unsigned int gic_irqs; 603 unsigned int i; 604 void __iomem *dist_base; 605 606 if (WARN_ON(!gic)) 607 return; 608 609 gic_irqs = gic->gic_irqs; 610 dist_base = gic_data_dist_base(gic); 611 612 if (!dist_base) 613 return; 614 615 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 616 617 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 618 writel_relaxed(gic->saved_spi_conf[i], 619 dist_base + GIC_DIST_CONFIG + i * 4); 620 621 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 622 writel_relaxed(GICD_INT_DEF_PRI_X4, 623 dist_base + GIC_DIST_PRI + i * 4); 624 625 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 626 writel_relaxed(gic->saved_spi_target[i], 627 dist_base + GIC_DIST_TARGET + i * 4); 628 629 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 630 writel_relaxed(GICD_INT_EN_CLR_X32, 631 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 632 writel_relaxed(gic->saved_spi_enable[i], 633 dist_base + GIC_DIST_ENABLE_SET + i * 4); 634 } 635 636 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 637 writel_relaxed(GICD_INT_EN_CLR_X32, 638 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 639 writel_relaxed(gic->saved_spi_active[i], 640 dist_base + GIC_DIST_ACTIVE_SET + i * 4); 641 } 642 643 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 644 } 645 646 void gic_cpu_save(struct gic_chip_data *gic) 647 { 648 int i; 649 u32 *ptr; 650 void __iomem *dist_base; 651 void __iomem *cpu_base; 652 653 if (WARN_ON(!gic)) 654 return; 655 656 dist_base = gic_data_dist_base(gic); 657 cpu_base = gic_data_cpu_base(gic); 658 659 if (!dist_base || !cpu_base) 660 return; 661 662 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 663 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 664 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 665 666 ptr = raw_cpu_ptr(gic->saved_ppi_active); 667 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 668 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 669 670 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 671 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 672 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 673 674 } 675 676 void gic_cpu_restore(struct gic_chip_data *gic) 677 { 678 int i; 679 u32 *ptr; 680 void __iomem *dist_base; 681 void __iomem *cpu_base; 682 683 if (WARN_ON(!gic)) 684 return; 685 686 dist_base = gic_data_dist_base(gic); 687 cpu_base = gic_data_cpu_base(gic); 688 689 if (!dist_base || !cpu_base) 690 return; 691 692 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 693 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 694 writel_relaxed(GICD_INT_EN_CLR_X32, 695 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 696 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 697 } 698 699 ptr = raw_cpu_ptr(gic->saved_ppi_active); 700 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 701 writel_relaxed(GICD_INT_EN_CLR_X32, 702 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 703 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); 704 } 705 706 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 707 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 708 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 709 710 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 711 writel_relaxed(GICD_INT_DEF_PRI_X4, 712 dist_base + GIC_DIST_PRI + i * 4); 713 714 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 715 gic_cpu_if_up(gic); 716 } 717 718 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 719 { 720 int i; 721 722 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { 723 #ifdef CONFIG_GIC_NON_BANKED 724 /* Skip over unused GICs */ 725 if (!gic_data[i].get_base) 726 continue; 727 #endif 728 switch (cmd) { 729 case CPU_PM_ENTER: 730 gic_cpu_save(&gic_data[i]); 731 break; 732 case CPU_PM_ENTER_FAILED: 733 case CPU_PM_EXIT: 734 gic_cpu_restore(&gic_data[i]); 735 break; 736 case CPU_CLUSTER_PM_ENTER: 737 gic_dist_save(&gic_data[i]); 738 break; 739 case CPU_CLUSTER_PM_ENTER_FAILED: 740 case CPU_CLUSTER_PM_EXIT: 741 gic_dist_restore(&gic_data[i]); 742 break; 743 } 744 } 745 746 return NOTIFY_OK; 747 } 748 749 static struct notifier_block gic_notifier_block = { 750 .notifier_call = gic_notifier, 751 }; 752 753 static int gic_pm_init(struct gic_chip_data *gic) 754 { 755 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 756 sizeof(u32)); 757 if (WARN_ON(!gic->saved_ppi_enable)) 758 return -ENOMEM; 759 760 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 761 sizeof(u32)); 762 if (WARN_ON(!gic->saved_ppi_active)) 763 goto free_ppi_enable; 764 765 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 766 sizeof(u32)); 767 if (WARN_ON(!gic->saved_ppi_conf)) 768 goto free_ppi_active; 769 770 if (gic == &gic_data[0]) 771 cpu_pm_register_notifier(&gic_notifier_block); 772 773 return 0; 774 775 free_ppi_active: 776 free_percpu(gic->saved_ppi_active); 777 free_ppi_enable: 778 free_percpu(gic->saved_ppi_enable); 779 780 return -ENOMEM; 781 } 782 #else 783 static int gic_pm_init(struct gic_chip_data *gic) 784 { 785 return 0; 786 } 787 #endif 788 789 #ifdef CONFIG_SMP 790 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 791 { 792 int cpu; 793 unsigned long flags, map = 0; 794 795 if (unlikely(nr_cpu_ids == 1)) { 796 /* Only one CPU? let's do a self-IPI... */ 797 writel_relaxed(2 << 24 | irq, 798 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 799 return; 800 } 801 802 gic_lock_irqsave(flags); 803 804 /* Convert our logical CPU mask into a physical one. */ 805 for_each_cpu(cpu, mask) 806 map |= gic_cpu_map[cpu]; 807 808 /* 809 * Ensure that stores to Normal memory are visible to the 810 * other CPUs before they observe us issuing the IPI. 811 */ 812 dmb(ishst); 813 814 /* this always happens on GIC0 */ 815 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 816 817 gic_unlock_irqrestore(flags); 818 } 819 #endif 820 821 #ifdef CONFIG_BL_SWITCHER 822 /* 823 * gic_send_sgi - send a SGI directly to given CPU interface number 824 * 825 * cpu_id: the ID for the destination CPU interface 826 * irq: the IPI number to send a SGI for 827 */ 828 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 829 { 830 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 831 cpu_id = 1 << cpu_id; 832 /* this always happens on GIC0 */ 833 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 834 } 835 836 /* 837 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 838 * 839 * @cpu: the logical CPU number to get the GIC ID for. 840 * 841 * Return the CPU interface ID for the given logical CPU number, 842 * or -1 if the CPU number is too large or the interface ID is 843 * unknown (more than one bit set). 844 */ 845 int gic_get_cpu_id(unsigned int cpu) 846 { 847 unsigned int cpu_bit; 848 849 if (cpu >= NR_GIC_CPU_IF) 850 return -1; 851 cpu_bit = gic_cpu_map[cpu]; 852 if (cpu_bit & (cpu_bit - 1)) 853 return -1; 854 return __ffs(cpu_bit); 855 } 856 857 /* 858 * gic_migrate_target - migrate IRQs to another CPU interface 859 * 860 * @new_cpu_id: the CPU target ID to migrate IRQs to 861 * 862 * Migrate all peripheral interrupts with a target matching the current CPU 863 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 864 * is also updated. Targets to other CPU interfaces are unchanged. 865 * This must be called with IRQs locally disabled. 866 */ 867 void gic_migrate_target(unsigned int new_cpu_id) 868 { 869 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 870 void __iomem *dist_base; 871 int i, ror_val, cpu = smp_processor_id(); 872 u32 val, cur_target_mask, active_mask; 873 874 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 875 876 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 877 if (!dist_base) 878 return; 879 gic_irqs = gic_data[gic_nr].gic_irqs; 880 881 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 882 cur_target_mask = 0x01010101 << cur_cpu_id; 883 ror_val = (cur_cpu_id - new_cpu_id) & 31; 884 885 gic_lock(); 886 887 /* Update the target interface for this logical CPU */ 888 gic_cpu_map[cpu] = 1 << new_cpu_id; 889 890 /* 891 * Find all the peripheral interrupts targetting the current 892 * CPU interface and migrate them to the new CPU interface. 893 * We skip DIST_TARGET 0 to 7 as they are read-only. 894 */ 895 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 896 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 897 active_mask = val & cur_target_mask; 898 if (active_mask) { 899 val &= ~active_mask; 900 val |= ror32(active_mask, ror_val); 901 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 902 } 903 } 904 905 gic_unlock(); 906 907 /* 908 * Now let's migrate and clear any potential SGIs that might be 909 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 910 * is a banked register, we can only forward the SGI using 911 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 912 * doesn't use that information anyway. 913 * 914 * For the same reason we do not adjust SGI source information 915 * for previously sent SGIs by us to other CPUs either. 916 */ 917 for (i = 0; i < 16; i += 4) { 918 int j; 919 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 920 if (!val) 921 continue; 922 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 923 for (j = i; j < i + 4; j++) { 924 if (val & 0xff) 925 writel_relaxed((1 << (new_cpu_id + 16)) | j, 926 dist_base + GIC_DIST_SOFTINT); 927 val >>= 8; 928 } 929 } 930 } 931 932 /* 933 * gic_get_sgir_physaddr - get the physical address for the SGI register 934 * 935 * REturn the physical address of the SGI register to be used 936 * by some early assembly code when the kernel is not yet available. 937 */ 938 static unsigned long gic_dist_physaddr; 939 940 unsigned long gic_get_sgir_physaddr(void) 941 { 942 if (!gic_dist_physaddr) 943 return 0; 944 return gic_dist_physaddr + GIC_DIST_SOFTINT; 945 } 946 947 static void __init gic_init_physaddr(struct device_node *node) 948 { 949 struct resource res; 950 if (of_address_to_resource(node, 0, &res) == 0) { 951 gic_dist_physaddr = res.start; 952 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 953 } 954 } 955 956 #else 957 #define gic_init_physaddr(node) do { } while (0) 958 #endif 959 960 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 961 irq_hw_number_t hw) 962 { 963 struct gic_chip_data *gic = d->host_data; 964 965 if (hw < 32) { 966 irq_set_percpu_devid(irq); 967 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 968 handle_percpu_devid_irq, NULL, NULL); 969 irq_set_status_flags(irq, IRQ_NOAUTOEN); 970 } else { 971 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 972 handle_fasteoi_irq, NULL, NULL); 973 irq_set_probe(irq); 974 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 975 } 976 return 0; 977 } 978 979 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 980 { 981 } 982 983 static int gic_irq_domain_translate(struct irq_domain *d, 984 struct irq_fwspec *fwspec, 985 unsigned long *hwirq, 986 unsigned int *type) 987 { 988 if (is_of_node(fwspec->fwnode)) { 989 if (fwspec->param_count < 3) 990 return -EINVAL; 991 992 /* Get the interrupt number and add 16 to skip over SGIs */ 993 *hwirq = fwspec->param[1] + 16; 994 995 /* 996 * For SPIs, we need to add 16 more to get the GIC irq 997 * ID number 998 */ 999 if (!fwspec->param[0]) 1000 *hwirq += 16; 1001 1002 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1003 return 0; 1004 } 1005 1006 if (is_fwnode_irqchip(fwspec->fwnode)) { 1007 if(fwspec->param_count != 2) 1008 return -EINVAL; 1009 1010 *hwirq = fwspec->param[0]; 1011 *type = fwspec->param[1]; 1012 return 0; 1013 } 1014 1015 return -EINVAL; 1016 } 1017 1018 static int gic_starting_cpu(unsigned int cpu) 1019 { 1020 gic_cpu_init(&gic_data[0]); 1021 return 0; 1022 } 1023 1024 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1025 unsigned int nr_irqs, void *arg) 1026 { 1027 int i, ret; 1028 irq_hw_number_t hwirq; 1029 unsigned int type = IRQ_TYPE_NONE; 1030 struct irq_fwspec *fwspec = arg; 1031 1032 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1033 if (ret) 1034 return ret; 1035 1036 for (i = 0; i < nr_irqs; i++) { 1037 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 1038 if (ret) 1039 return ret; 1040 } 1041 1042 return 0; 1043 } 1044 1045 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 1046 .translate = gic_irq_domain_translate, 1047 .alloc = gic_irq_domain_alloc, 1048 .free = irq_domain_free_irqs_top, 1049 }; 1050 1051 static const struct irq_domain_ops gic_irq_domain_ops = { 1052 .map = gic_irq_domain_map, 1053 .unmap = gic_irq_domain_unmap, 1054 }; 1055 1056 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, 1057 const char *name, bool use_eoimode1) 1058 { 1059 /* Initialize irq_chip */ 1060 gic->chip = gic_chip; 1061 gic->chip.name = name; 1062 gic->chip.parent_device = dev; 1063 1064 if (use_eoimode1) { 1065 gic->chip.irq_mask = gic_eoimode1_mask_irq; 1066 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; 1067 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; 1068 } 1069 1070 #ifdef CONFIG_SMP 1071 if (gic == &gic_data[0]) 1072 gic->chip.irq_set_affinity = gic_set_affinity; 1073 #endif 1074 } 1075 1076 static int gic_init_bases(struct gic_chip_data *gic, int irq_start, 1077 struct fwnode_handle *handle) 1078 { 1079 irq_hw_number_t hwirq_base; 1080 int gic_irqs, irq_base, ret; 1081 1082 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1083 /* Frankein-GIC without banked registers... */ 1084 unsigned int cpu; 1085 1086 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 1087 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 1088 if (WARN_ON(!gic->dist_base.percpu_base || 1089 !gic->cpu_base.percpu_base)) { 1090 ret = -ENOMEM; 1091 goto error; 1092 } 1093 1094 for_each_possible_cpu(cpu) { 1095 u32 mpidr = cpu_logical_map(cpu); 1096 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 1097 unsigned long offset = gic->percpu_offset * core_id; 1098 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 1099 gic->raw_dist_base + offset; 1100 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = 1101 gic->raw_cpu_base + offset; 1102 } 1103 1104 gic_set_base_accessor(gic, gic_get_percpu_base); 1105 } else { 1106 /* Normal, sane GIC... */ 1107 WARN(gic->percpu_offset, 1108 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 1109 gic->percpu_offset); 1110 gic->dist_base.common_base = gic->raw_dist_base; 1111 gic->cpu_base.common_base = gic->raw_cpu_base; 1112 gic_set_base_accessor(gic, gic_get_common_base); 1113 } 1114 1115 /* 1116 * Find out how many interrupts are supported. 1117 * The GIC only supports up to 1020 interrupt sources. 1118 */ 1119 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1120 gic_irqs = (gic_irqs + 1) * 32; 1121 if (gic_irqs > 1020) 1122 gic_irqs = 1020; 1123 gic->gic_irqs = gic_irqs; 1124 1125 if (handle) { /* DT/ACPI */ 1126 gic->domain = irq_domain_create_linear(handle, gic_irqs, 1127 &gic_irq_domain_hierarchy_ops, 1128 gic); 1129 } else { /* Legacy support */ 1130 /* 1131 * For primary GICs, skip over SGIs. 1132 * For secondary GICs, skip over PPIs, too. 1133 */ 1134 if (gic == &gic_data[0] && (irq_start & 31) > 0) { 1135 hwirq_base = 16; 1136 if (irq_start != -1) 1137 irq_start = (irq_start & ~31) + 16; 1138 } else { 1139 hwirq_base = 32; 1140 } 1141 1142 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 1143 1144 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 1145 numa_node_id()); 1146 if (irq_base < 0) { 1147 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 1148 irq_start); 1149 irq_base = irq_start; 1150 } 1151 1152 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, 1153 hwirq_base, &gic_irq_domain_ops, gic); 1154 } 1155 1156 if (WARN_ON(!gic->domain)) { 1157 ret = -ENODEV; 1158 goto error; 1159 } 1160 1161 gic_dist_init(gic); 1162 ret = gic_cpu_init(gic); 1163 if (ret) 1164 goto error; 1165 1166 ret = gic_pm_init(gic); 1167 if (ret) 1168 goto error; 1169 1170 return 0; 1171 1172 error: 1173 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1174 free_percpu(gic->dist_base.percpu_base); 1175 free_percpu(gic->cpu_base.percpu_base); 1176 } 1177 1178 return ret; 1179 } 1180 1181 static int __init __gic_init_bases(struct gic_chip_data *gic, 1182 int irq_start, 1183 struct fwnode_handle *handle) 1184 { 1185 char *name; 1186 int i, ret; 1187 1188 if (WARN_ON(!gic || gic->domain)) 1189 return -EINVAL; 1190 1191 if (gic == &gic_data[0]) { 1192 /* 1193 * Initialize the CPU interface map to all CPUs. 1194 * It will be refined as each CPU probes its ID. 1195 * This is only necessary for the primary GIC. 1196 */ 1197 for (i = 0; i < NR_GIC_CPU_IF; i++) 1198 gic_cpu_map[i] = 0xff; 1199 #ifdef CONFIG_SMP 1200 set_smp_cross_call(gic_raise_softirq); 1201 #endif 1202 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 1203 "irqchip/arm/gic:starting", 1204 gic_starting_cpu, NULL); 1205 set_handle_irq(gic_handle_irq); 1206 if (static_key_true(&supports_deactivate)) 1207 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1208 } 1209 1210 if (static_key_true(&supports_deactivate) && gic == &gic_data[0]) { 1211 name = kasprintf(GFP_KERNEL, "GICv2"); 1212 gic_init_chip(gic, NULL, name, true); 1213 } else { 1214 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); 1215 gic_init_chip(gic, NULL, name, false); 1216 } 1217 1218 ret = gic_init_bases(gic, irq_start, handle); 1219 if (ret) 1220 kfree(name); 1221 1222 return ret; 1223 } 1224 1225 void __init gic_init(unsigned int gic_nr, int irq_start, 1226 void __iomem *dist_base, void __iomem *cpu_base) 1227 { 1228 struct gic_chip_data *gic; 1229 1230 if (WARN_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR)) 1231 return; 1232 1233 /* 1234 * Non-DT/ACPI systems won't run a hypervisor, so let's not 1235 * bother with these... 1236 */ 1237 static_key_slow_dec(&supports_deactivate); 1238 1239 gic = &gic_data[gic_nr]; 1240 gic->raw_dist_base = dist_base; 1241 gic->raw_cpu_base = cpu_base; 1242 1243 __gic_init_bases(gic, irq_start, NULL); 1244 } 1245 1246 static void gic_teardown(struct gic_chip_data *gic) 1247 { 1248 if (WARN_ON(!gic)) 1249 return; 1250 1251 if (gic->raw_dist_base) 1252 iounmap(gic->raw_dist_base); 1253 if (gic->raw_cpu_base) 1254 iounmap(gic->raw_cpu_base); 1255 } 1256 1257 #ifdef CONFIG_OF 1258 static int gic_cnt __initdata; 1259 static bool gicv2_force_probe; 1260 1261 static int __init gicv2_force_probe_cfg(char *buf) 1262 { 1263 return strtobool(buf, &gicv2_force_probe); 1264 } 1265 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg); 1266 1267 static bool gic_check_gicv2(void __iomem *base) 1268 { 1269 u32 val = readl_relaxed(base + GIC_CPU_IDENT); 1270 return (val & 0xff0fff) == 0x02043B; 1271 } 1272 1273 static bool gic_check_eoimode(struct device_node *node, void __iomem **base) 1274 { 1275 struct resource cpuif_res; 1276 1277 of_address_to_resource(node, 1, &cpuif_res); 1278 1279 if (!is_hyp_mode_available()) 1280 return false; 1281 if (resource_size(&cpuif_res) < SZ_8K) { 1282 void __iomem *alt; 1283 /* 1284 * Check for a stupid firmware that only exposes the 1285 * first page of a GICv2. 1286 */ 1287 if (!gic_check_gicv2(*base)) 1288 return false; 1289 1290 if (!gicv2_force_probe) { 1291 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); 1292 return false; 1293 } 1294 1295 alt = ioremap(cpuif_res.start, SZ_8K); 1296 if (!alt) 1297 return false; 1298 if (!gic_check_gicv2(alt + SZ_4K)) { 1299 /* 1300 * The first page was that of a GICv2, and 1301 * the second was *something*. Let's trust it 1302 * to be a GICv2, and update the mapping. 1303 */ 1304 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", 1305 &cpuif_res.start); 1306 iounmap(*base); 1307 *base = alt; 1308 return true; 1309 } 1310 1311 /* 1312 * We detected *two* initial GICv2 pages in a 1313 * row. Could be a GICv2 aliased over two 64kB 1314 * pages. Update the resource, map the iospace, and 1315 * pray. 1316 */ 1317 iounmap(alt); 1318 alt = ioremap(cpuif_res.start, SZ_128K); 1319 if (!alt) 1320 return false; 1321 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", 1322 &cpuif_res.start); 1323 cpuif_res.end = cpuif_res.start + SZ_128K -1; 1324 iounmap(*base); 1325 *base = alt; 1326 } 1327 if (resource_size(&cpuif_res) == SZ_128K) { 1328 /* 1329 * Verify that we have the first 4kB of a GICv2 1330 * aliased over the first 64kB by checking the 1331 * GICC_IIDR register on both ends. 1332 */ 1333 if (!gic_check_gicv2(*base) || 1334 !gic_check_gicv2(*base + 0xf000)) 1335 return false; 1336 1337 /* 1338 * Move the base up by 60kB, so that we have a 8kB 1339 * contiguous region, which allows us to use GICC_DIR 1340 * at its normal offset. Please pass me that bucket. 1341 */ 1342 *base += 0xf000; 1343 cpuif_res.start += 0xf000; 1344 pr_warn("GIC: Adjusting CPU interface base to %pa\n", 1345 &cpuif_res.start); 1346 } 1347 1348 return true; 1349 } 1350 1351 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) 1352 { 1353 if (!gic || !node) 1354 return -EINVAL; 1355 1356 gic->raw_dist_base = of_iomap(node, 0); 1357 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) 1358 goto error; 1359 1360 gic->raw_cpu_base = of_iomap(node, 1); 1361 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) 1362 goto error; 1363 1364 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) 1365 gic->percpu_offset = 0; 1366 1367 return 0; 1368 1369 error: 1370 gic_teardown(gic); 1371 1372 return -ENOMEM; 1373 } 1374 1375 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1376 { 1377 int ret; 1378 1379 if (!dev || !dev->of_node || !gic || !irq) 1380 return -EINVAL; 1381 1382 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); 1383 if (!*gic) 1384 return -ENOMEM; 1385 1386 gic_init_chip(*gic, dev, dev->of_node->name, false); 1387 1388 ret = gic_of_setup(*gic, dev->of_node); 1389 if (ret) 1390 return ret; 1391 1392 ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode); 1393 if (ret) { 1394 gic_teardown(*gic); 1395 return ret; 1396 } 1397 1398 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); 1399 1400 return 0; 1401 } 1402 1403 static void __init gic_of_setup_kvm_info(struct device_node *node) 1404 { 1405 int ret; 1406 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1407 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1408 1409 gic_v2_kvm_info.type = GIC_V2; 1410 1411 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1412 if (!gic_v2_kvm_info.maint_irq) 1413 return; 1414 1415 ret = of_address_to_resource(node, 2, vctrl_res); 1416 if (ret) 1417 return; 1418 1419 ret = of_address_to_resource(node, 3, vcpu_res); 1420 if (ret) 1421 return; 1422 1423 if (static_key_true(&supports_deactivate)) 1424 gic_set_kvm_info(&gic_v2_kvm_info); 1425 } 1426 1427 int __init 1428 gic_of_init(struct device_node *node, struct device_node *parent) 1429 { 1430 struct gic_chip_data *gic; 1431 int irq, ret; 1432 1433 if (WARN_ON(!node)) 1434 return -ENODEV; 1435 1436 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) 1437 return -EINVAL; 1438 1439 gic = &gic_data[gic_cnt]; 1440 1441 ret = gic_of_setup(gic, node); 1442 if (ret) 1443 return ret; 1444 1445 /* 1446 * Disable split EOI/Deactivate if either HYP is not available 1447 * or the CPU interface is too small. 1448 */ 1449 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) 1450 static_key_slow_dec(&supports_deactivate); 1451 1452 ret = __gic_init_bases(gic, -1, &node->fwnode); 1453 if (ret) { 1454 gic_teardown(gic); 1455 return ret; 1456 } 1457 1458 if (!gic_cnt) { 1459 gic_init_physaddr(node); 1460 gic_of_setup_kvm_info(node); 1461 } 1462 1463 if (parent) { 1464 irq = irq_of_parse_and_map(node, 0); 1465 gic_cascade_irq(gic_cnt, irq); 1466 } 1467 1468 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1469 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); 1470 1471 gic_cnt++; 1472 return 0; 1473 } 1474 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1475 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1476 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1477 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1478 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1479 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1480 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1481 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1482 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1483 #else 1484 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1485 { 1486 return -ENOTSUPP; 1487 } 1488 #endif 1489 1490 #ifdef CONFIG_ACPI 1491 static struct 1492 { 1493 phys_addr_t cpu_phys_base; 1494 u32 maint_irq; 1495 int maint_irq_mode; 1496 phys_addr_t vctrl_base; 1497 phys_addr_t vcpu_base; 1498 } acpi_data __initdata; 1499 1500 static int __init 1501 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, 1502 const unsigned long end) 1503 { 1504 struct acpi_madt_generic_interrupt *processor; 1505 phys_addr_t gic_cpu_base; 1506 static int cpu_base_assigned; 1507 1508 processor = (struct acpi_madt_generic_interrupt *)header; 1509 1510 if (BAD_MADT_GICC_ENTRY(processor, end)) 1511 return -EINVAL; 1512 1513 /* 1514 * There is no support for non-banked GICv1/2 register in ACPI spec. 1515 * All CPU interface addresses have to be the same. 1516 */ 1517 gic_cpu_base = processor->base_address; 1518 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) 1519 return -EINVAL; 1520 1521 acpi_data.cpu_phys_base = gic_cpu_base; 1522 acpi_data.maint_irq = processor->vgic_interrupt; 1523 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1524 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1525 acpi_data.vctrl_base = processor->gich_base_address; 1526 acpi_data.vcpu_base = processor->gicv_base_address; 1527 1528 cpu_base_assigned = 1; 1529 return 0; 1530 } 1531 1532 /* The things you have to do to just *count* something... */ 1533 static int __init acpi_dummy_func(struct acpi_subtable_header *header, 1534 const unsigned long end) 1535 { 1536 return 0; 1537 } 1538 1539 static bool __init acpi_gic_redist_is_present(void) 1540 { 1541 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1542 acpi_dummy_func, 0) > 0; 1543 } 1544 1545 static bool __init gic_validate_dist(struct acpi_subtable_header *header, 1546 struct acpi_probe_entry *ape) 1547 { 1548 struct acpi_madt_generic_distributor *dist; 1549 dist = (struct acpi_madt_generic_distributor *)header; 1550 1551 return (dist->version == ape->driver_data && 1552 (dist->version != ACPI_MADT_GIC_VERSION_NONE || 1553 !acpi_gic_redist_is_present())); 1554 } 1555 1556 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) 1557 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) 1558 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1559 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1560 1561 static void __init gic_acpi_setup_kvm_info(void) 1562 { 1563 int irq; 1564 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1565 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1566 1567 gic_v2_kvm_info.type = GIC_V2; 1568 1569 if (!acpi_data.vctrl_base) 1570 return; 1571 1572 vctrl_res->flags = IORESOURCE_MEM; 1573 vctrl_res->start = acpi_data.vctrl_base; 1574 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; 1575 1576 if (!acpi_data.vcpu_base) 1577 return; 1578 1579 vcpu_res->flags = IORESOURCE_MEM; 1580 vcpu_res->start = acpi_data.vcpu_base; 1581 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1582 1583 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1584 acpi_data.maint_irq_mode, 1585 ACPI_ACTIVE_HIGH); 1586 if (irq <= 0) 1587 return; 1588 1589 gic_v2_kvm_info.maint_irq = irq; 1590 1591 gic_set_kvm_info(&gic_v2_kvm_info); 1592 } 1593 1594 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, 1595 const unsigned long end) 1596 { 1597 struct acpi_madt_generic_distributor *dist; 1598 struct fwnode_handle *domain_handle; 1599 struct gic_chip_data *gic = &gic_data[0]; 1600 int count, ret; 1601 1602 /* Collect CPU base addresses */ 1603 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1604 gic_acpi_parse_madt_cpu, 0); 1605 if (count <= 0) { 1606 pr_err("No valid GICC entries exist\n"); 1607 return -EINVAL; 1608 } 1609 1610 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1611 if (!gic->raw_cpu_base) { 1612 pr_err("Unable to map GICC registers\n"); 1613 return -ENOMEM; 1614 } 1615 1616 dist = (struct acpi_madt_generic_distributor *)header; 1617 gic->raw_dist_base = ioremap(dist->base_address, 1618 ACPI_GICV2_DIST_MEM_SIZE); 1619 if (!gic->raw_dist_base) { 1620 pr_err("Unable to map GICD registers\n"); 1621 gic_teardown(gic); 1622 return -ENOMEM; 1623 } 1624 1625 /* 1626 * Disable split EOI/Deactivate if HYP is not available. ACPI 1627 * guarantees that we'll always have a GICv2, so the CPU 1628 * interface will always be the right size. 1629 */ 1630 if (!is_hyp_mode_available()) 1631 static_key_slow_dec(&supports_deactivate); 1632 1633 /* 1634 * Initialize GIC instance zero (no multi-GIC support). 1635 */ 1636 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base); 1637 if (!domain_handle) { 1638 pr_err("Unable to allocate domain handle\n"); 1639 gic_teardown(gic); 1640 return -ENOMEM; 1641 } 1642 1643 ret = __gic_init_bases(gic, -1, domain_handle); 1644 if (ret) { 1645 pr_err("Failed to initialise GIC\n"); 1646 irq_domain_free_fwnode(domain_handle); 1647 gic_teardown(gic); 1648 return ret; 1649 } 1650 1651 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1652 1653 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1654 gicv2m_init(NULL, gic_data[0].domain); 1655 1656 if (static_key_true(&supports_deactivate)) 1657 gic_acpi_setup_kvm_info(); 1658 1659 return 0; 1660 } 1661 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1662 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, 1663 gic_v2_acpi_init); 1664 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1665 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, 1666 gic_v2_acpi_init); 1667 #endif 1668