1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 4 * 5 * Interrupt architecture for the GIC: 6 * 7 * o There is one Interrupt Distributor, which receives interrupts 8 * from system devices and sends them to the Interrupt Controllers. 9 * 10 * o There is one CPU Interface per CPU, which sends interrupts sent 11 * by the Distributor, and interrupts generated locally, to the 12 * associated CPU. The base address of the CPU interface is usually 13 * aliased so that the same address points to different chips depending 14 * on the CPU it is accessed from. 15 * 16 * Note that IRQs 0-31 are special - they are local to each CPU. 17 * As such, the enable set/clear, pending set/clear and active bit 18 * registers are banked per-cpu for these sources. 19 */ 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/err.h> 23 #include <linux/module.h> 24 #include <linux/list.h> 25 #include <linux/smp.h> 26 #include <linux/cpu.h> 27 #include <linux/cpu_pm.h> 28 #include <linux/cpumask.h> 29 #include <linux/io.h> 30 #include <linux/of.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/acpi.h> 34 #include <linux/irqdomain.h> 35 #include <linux/interrupt.h> 36 #include <linux/percpu.h> 37 #include <linux/slab.h> 38 #include <linux/irqchip.h> 39 #include <linux/irqchip/chained_irq.h> 40 #include <linux/irqchip/arm-gic.h> 41 42 #include <asm/cputype.h> 43 #include <asm/irq.h> 44 #include <asm/exception.h> 45 #include <asm/smp_plat.h> 46 #include <asm/virt.h> 47 48 #include "irq-gic-common.h" 49 50 #ifdef CONFIG_ARM64 51 #include <asm/cpufeature.h> 52 53 static void gic_check_cpu_features(void) 54 { 55 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), 56 TAINT_CPU_OUT_OF_SPEC, 57 "GICv3 system registers enabled, broken firmware!\n"); 58 } 59 #else 60 #define gic_check_cpu_features() do { } while(0) 61 #endif 62 63 union gic_base { 64 void __iomem *common_base; 65 void __percpu * __iomem *percpu_base; 66 }; 67 68 struct gic_chip_data { 69 struct irq_chip chip; 70 union gic_base dist_base; 71 union gic_base cpu_base; 72 void __iomem *raw_dist_base; 73 void __iomem *raw_cpu_base; 74 u32 percpu_offset; 75 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 77 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 78 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 79 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 80 u32 __percpu *saved_ppi_enable; 81 u32 __percpu *saved_ppi_active; 82 u32 __percpu *saved_ppi_conf; 83 #endif 84 struct irq_domain *domain; 85 unsigned int gic_irqs; 86 #ifdef CONFIG_GIC_NON_BANKED 87 void __iomem *(*get_base)(union gic_base *); 88 #endif 89 }; 90 91 #ifdef CONFIG_BL_SWITCHER 92 93 static DEFINE_RAW_SPINLOCK(cpu_map_lock); 94 95 #define gic_lock_irqsave(f) \ 96 raw_spin_lock_irqsave(&cpu_map_lock, (f)) 97 #define gic_unlock_irqrestore(f) \ 98 raw_spin_unlock_irqrestore(&cpu_map_lock, (f)) 99 100 #define gic_lock() raw_spin_lock(&cpu_map_lock) 101 #define gic_unlock() raw_spin_unlock(&cpu_map_lock) 102 103 #else 104 105 #define gic_lock_irqsave(f) do { (void)(f); } while(0) 106 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0) 107 108 #define gic_lock() do { } while(0) 109 #define gic_unlock() do { } while(0) 110 111 #endif 112 113 /* 114 * The GIC mapping of CPU interfaces does not necessarily match 115 * the logical CPU numbering. Let's use a mapping as returned 116 * by the GIC itself. 117 */ 118 #define NR_GIC_CPU_IF 8 119 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 120 121 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 122 123 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; 124 125 static struct gic_kvm_info gic_v2_kvm_info; 126 127 #ifdef CONFIG_GIC_NON_BANKED 128 static void __iomem *gic_get_percpu_base(union gic_base *base) 129 { 130 return raw_cpu_read(*base->percpu_base); 131 } 132 133 static void __iomem *gic_get_common_base(union gic_base *base) 134 { 135 return base->common_base; 136 } 137 138 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 139 { 140 return data->get_base(&data->dist_base); 141 } 142 143 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 144 { 145 return data->get_base(&data->cpu_base); 146 } 147 148 static inline void gic_set_base_accessor(struct gic_chip_data *data, 149 void __iomem *(*f)(union gic_base *)) 150 { 151 data->get_base = f; 152 } 153 #else 154 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 155 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 156 #define gic_set_base_accessor(d, f) 157 #endif 158 159 static inline void __iomem *gic_dist_base(struct irq_data *d) 160 { 161 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 162 return gic_data_dist_base(gic_data); 163 } 164 165 static inline void __iomem *gic_cpu_base(struct irq_data *d) 166 { 167 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 168 return gic_data_cpu_base(gic_data); 169 } 170 171 static inline unsigned int gic_irq(struct irq_data *d) 172 { 173 return d->hwirq; 174 } 175 176 static inline bool cascading_gic_irq(struct irq_data *d) 177 { 178 void *data = irq_data_get_irq_handler_data(d); 179 180 /* 181 * If handler_data is set, this is a cascading interrupt, and 182 * it cannot possibly be forwarded. 183 */ 184 return data != NULL; 185 } 186 187 /* 188 * Routines to acknowledge, disable and enable interrupts 189 */ 190 static void gic_poke_irq(struct irq_data *d, u32 offset) 191 { 192 u32 mask = 1 << (gic_irq(d) % 32); 193 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 194 } 195 196 static int gic_peek_irq(struct irq_data *d, u32 offset) 197 { 198 u32 mask = 1 << (gic_irq(d) % 32); 199 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 200 } 201 202 static void gic_mask_irq(struct irq_data *d) 203 { 204 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 205 } 206 207 static void gic_eoimode1_mask_irq(struct irq_data *d) 208 { 209 gic_mask_irq(d); 210 /* 211 * When masking a forwarded interrupt, make sure it is 212 * deactivated as well. 213 * 214 * This ensures that an interrupt that is getting 215 * disabled/masked will not get "stuck", because there is 216 * noone to deactivate it (guest is being terminated). 217 */ 218 if (irqd_is_forwarded_to_vcpu(d)) 219 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); 220 } 221 222 static void gic_unmask_irq(struct irq_data *d) 223 { 224 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 225 } 226 227 static void gic_eoi_irq(struct irq_data *d) 228 { 229 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 230 } 231 232 static void gic_eoimode1_eoi_irq(struct irq_data *d) 233 { 234 /* Do not deactivate an IRQ forwarded to a vcpu. */ 235 if (irqd_is_forwarded_to_vcpu(d)) 236 return; 237 238 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); 239 } 240 241 static int gic_irq_set_irqchip_state(struct irq_data *d, 242 enum irqchip_irq_state which, bool val) 243 { 244 u32 reg; 245 246 switch (which) { 247 case IRQCHIP_STATE_PENDING: 248 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 249 break; 250 251 case IRQCHIP_STATE_ACTIVE: 252 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 253 break; 254 255 case IRQCHIP_STATE_MASKED: 256 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 257 break; 258 259 default: 260 return -EINVAL; 261 } 262 263 gic_poke_irq(d, reg); 264 return 0; 265 } 266 267 static int gic_irq_get_irqchip_state(struct irq_data *d, 268 enum irqchip_irq_state which, bool *val) 269 { 270 switch (which) { 271 case IRQCHIP_STATE_PENDING: 272 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 273 break; 274 275 case IRQCHIP_STATE_ACTIVE: 276 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 277 break; 278 279 case IRQCHIP_STATE_MASKED: 280 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 281 break; 282 283 default: 284 return -EINVAL; 285 } 286 287 return 0; 288 } 289 290 static int gic_set_type(struct irq_data *d, unsigned int type) 291 { 292 void __iomem *base = gic_dist_base(d); 293 unsigned int gicirq = gic_irq(d); 294 int ret; 295 296 /* Interrupt configuration for SGIs can't be changed */ 297 if (gicirq < 16) 298 return -EINVAL; 299 300 /* SPIs have restrictions on the supported types */ 301 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 302 type != IRQ_TYPE_EDGE_RISING) 303 return -EINVAL; 304 305 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL); 306 if (ret && gicirq < 32) { 307 /* Misconfigured PPIs are usually not fatal */ 308 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); 309 ret = 0; 310 } 311 312 return ret; 313 } 314 315 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 316 { 317 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ 318 if (cascading_gic_irq(d)) 319 return -EINVAL; 320 321 if (vcpu) 322 irqd_set_forwarded_to_vcpu(d); 323 else 324 irqd_clr_forwarded_to_vcpu(d); 325 return 0; 326 } 327 328 #ifdef CONFIG_SMP 329 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 330 bool force) 331 { 332 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 333 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 334 u32 val, mask, bit; 335 unsigned long flags; 336 337 if (!force) 338 cpu = cpumask_any_and(mask_val, cpu_online_mask); 339 else 340 cpu = cpumask_first(mask_val); 341 342 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 343 return -EINVAL; 344 345 gic_lock_irqsave(flags); 346 mask = 0xff << shift; 347 bit = gic_cpu_map[cpu] << shift; 348 val = readl_relaxed(reg) & ~mask; 349 writel_relaxed(val | bit, reg); 350 gic_unlock_irqrestore(flags); 351 352 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 353 354 return IRQ_SET_MASK_OK_DONE; 355 } 356 #endif 357 358 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 359 { 360 u32 irqstat, irqnr; 361 struct gic_chip_data *gic = &gic_data[0]; 362 void __iomem *cpu_base = gic_data_cpu_base(gic); 363 364 do { 365 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 366 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 367 368 if (likely(irqnr > 15 && irqnr < 1020)) { 369 if (static_branch_likely(&supports_deactivate_key)) 370 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 371 isb(); 372 handle_domain_irq(gic->domain, irqnr, regs); 373 continue; 374 } 375 if (irqnr < 16) { 376 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 377 if (static_branch_likely(&supports_deactivate_key)) 378 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); 379 #ifdef CONFIG_SMP 380 /* 381 * Ensure any shared data written by the CPU sending 382 * the IPI is read after we've read the ACK register 383 * on the GIC. 384 * 385 * Pairs with the write barrier in gic_raise_softirq 386 */ 387 smp_rmb(); 388 handle_IPI(irqnr, regs); 389 #endif 390 continue; 391 } 392 break; 393 } while (1); 394 } 395 396 static void gic_handle_cascade_irq(struct irq_desc *desc) 397 { 398 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); 399 struct irq_chip *chip = irq_desc_get_chip(desc); 400 unsigned int cascade_irq, gic_irq; 401 unsigned long status; 402 403 chained_irq_enter(chip, desc); 404 405 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 406 407 gic_irq = (status & GICC_IAR_INT_ID_MASK); 408 if (gic_irq == GICC_INT_SPURIOUS) 409 goto out; 410 411 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 412 if (unlikely(gic_irq < 32 || gic_irq > 1020)) { 413 handle_bad_irq(desc); 414 } else { 415 isb(); 416 generic_handle_irq(cascade_irq); 417 } 418 419 out: 420 chained_irq_exit(chip, desc); 421 } 422 423 static const struct irq_chip gic_chip = { 424 .irq_mask = gic_mask_irq, 425 .irq_unmask = gic_unmask_irq, 426 .irq_eoi = gic_eoi_irq, 427 .irq_set_type = gic_set_type, 428 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 429 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 430 .flags = IRQCHIP_SET_TYPE_MASKED | 431 IRQCHIP_SKIP_SET_WAKE | 432 IRQCHIP_MASK_ON_SUSPEND, 433 }; 434 435 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 436 { 437 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 438 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, 439 &gic_data[gic_nr]); 440 } 441 442 static u8 gic_get_cpumask(struct gic_chip_data *gic) 443 { 444 void __iomem *base = gic_data_dist_base(gic); 445 u32 mask, i; 446 447 for (i = mask = 0; i < 32; i += 4) { 448 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 449 mask |= mask >> 16; 450 mask |= mask >> 8; 451 if (mask) 452 break; 453 } 454 455 if (!mask && num_possible_cpus() > 1) 456 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 457 458 return mask; 459 } 460 461 static bool gic_check_gicv2(void __iomem *base) 462 { 463 u32 val = readl_relaxed(base + GIC_CPU_IDENT); 464 return (val & 0xff0fff) == 0x02043B; 465 } 466 467 static void gic_cpu_if_up(struct gic_chip_data *gic) 468 { 469 void __iomem *cpu_base = gic_data_cpu_base(gic); 470 u32 bypass = 0; 471 u32 mode = 0; 472 int i; 473 474 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) 475 mode = GIC_CPU_CTRL_EOImodeNS; 476 477 if (gic_check_gicv2(cpu_base)) 478 for (i = 0; i < 4; i++) 479 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4); 480 481 /* 482 * Preserve bypass disable bits to be written back later 483 */ 484 bypass = readl(cpu_base + GIC_CPU_CTRL); 485 bypass &= GICC_DIS_BYPASS_MASK; 486 487 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 488 } 489 490 491 static void gic_dist_init(struct gic_chip_data *gic) 492 { 493 unsigned int i; 494 u32 cpumask; 495 unsigned int gic_irqs = gic->gic_irqs; 496 void __iomem *base = gic_data_dist_base(gic); 497 498 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 499 500 /* 501 * Set all global interrupts to this CPU only. 502 */ 503 cpumask = gic_get_cpumask(gic); 504 cpumask |= cpumask << 8; 505 cpumask |= cpumask << 16; 506 for (i = 32; i < gic_irqs; i += 4) 507 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 508 509 gic_dist_config(base, gic_irqs, NULL); 510 511 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 512 } 513 514 static int gic_cpu_init(struct gic_chip_data *gic) 515 { 516 void __iomem *dist_base = gic_data_dist_base(gic); 517 void __iomem *base = gic_data_cpu_base(gic); 518 unsigned int cpu_mask, cpu = smp_processor_id(); 519 int i; 520 521 /* 522 * Setting up the CPU map is only relevant for the primary GIC 523 * because any nested/secondary GICs do not directly interface 524 * with the CPU(s). 525 */ 526 if (gic == &gic_data[0]) { 527 /* 528 * Get what the GIC says our CPU mask is. 529 */ 530 if (WARN_ON(cpu >= NR_GIC_CPU_IF)) 531 return -EINVAL; 532 533 gic_check_cpu_features(); 534 cpu_mask = gic_get_cpumask(gic); 535 gic_cpu_map[cpu] = cpu_mask; 536 537 /* 538 * Clear our mask from the other map entries in case they're 539 * still undefined. 540 */ 541 for (i = 0; i < NR_GIC_CPU_IF; i++) 542 if (i != cpu) 543 gic_cpu_map[i] &= ~cpu_mask; 544 } 545 546 gic_cpu_config(dist_base, 32, NULL); 547 548 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 549 gic_cpu_if_up(gic); 550 551 return 0; 552 } 553 554 int gic_cpu_if_down(unsigned int gic_nr) 555 { 556 void __iomem *cpu_base; 557 u32 val = 0; 558 559 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) 560 return -EINVAL; 561 562 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 563 val = readl(cpu_base + GIC_CPU_CTRL); 564 val &= ~GICC_ENABLE; 565 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 566 567 return 0; 568 } 569 570 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 571 /* 572 * Saves the GIC distributor registers during suspend or idle. Must be called 573 * with interrupts disabled but before powering down the GIC. After calling 574 * this function, no interrupts will be delivered by the GIC, and another 575 * platform-specific wakeup source must be enabled. 576 */ 577 void gic_dist_save(struct gic_chip_data *gic) 578 { 579 unsigned int gic_irqs; 580 void __iomem *dist_base; 581 int i; 582 583 if (WARN_ON(!gic)) 584 return; 585 586 gic_irqs = gic->gic_irqs; 587 dist_base = gic_data_dist_base(gic); 588 589 if (!dist_base) 590 return; 591 592 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 593 gic->saved_spi_conf[i] = 594 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 595 596 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 597 gic->saved_spi_target[i] = 598 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 599 600 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 601 gic->saved_spi_enable[i] = 602 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 603 604 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 605 gic->saved_spi_active[i] = 606 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 607 } 608 609 /* 610 * Restores the GIC distributor registers during resume or when coming out of 611 * idle. Must be called before enabling interrupts. If a level interrupt 612 * that occurred while the GIC was suspended is still present, it will be 613 * handled normally, but any edge interrupts that occurred will not be seen by 614 * the GIC and need to be handled by the platform-specific wakeup source. 615 */ 616 void gic_dist_restore(struct gic_chip_data *gic) 617 { 618 unsigned int gic_irqs; 619 unsigned int i; 620 void __iomem *dist_base; 621 622 if (WARN_ON(!gic)) 623 return; 624 625 gic_irqs = gic->gic_irqs; 626 dist_base = gic_data_dist_base(gic); 627 628 if (!dist_base) 629 return; 630 631 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 632 633 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 634 writel_relaxed(gic->saved_spi_conf[i], 635 dist_base + GIC_DIST_CONFIG + i * 4); 636 637 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 638 writel_relaxed(GICD_INT_DEF_PRI_X4, 639 dist_base + GIC_DIST_PRI + i * 4); 640 641 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 642 writel_relaxed(gic->saved_spi_target[i], 643 dist_base + GIC_DIST_TARGET + i * 4); 644 645 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 646 writel_relaxed(GICD_INT_EN_CLR_X32, 647 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 648 writel_relaxed(gic->saved_spi_enable[i], 649 dist_base + GIC_DIST_ENABLE_SET + i * 4); 650 } 651 652 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 653 writel_relaxed(GICD_INT_EN_CLR_X32, 654 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 655 writel_relaxed(gic->saved_spi_active[i], 656 dist_base + GIC_DIST_ACTIVE_SET + i * 4); 657 } 658 659 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 660 } 661 662 void gic_cpu_save(struct gic_chip_data *gic) 663 { 664 int i; 665 u32 *ptr; 666 void __iomem *dist_base; 667 void __iomem *cpu_base; 668 669 if (WARN_ON(!gic)) 670 return; 671 672 dist_base = gic_data_dist_base(gic); 673 cpu_base = gic_data_cpu_base(gic); 674 675 if (!dist_base || !cpu_base) 676 return; 677 678 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 679 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 680 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 681 682 ptr = raw_cpu_ptr(gic->saved_ppi_active); 683 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 684 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 685 686 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 687 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 688 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 689 690 } 691 692 void gic_cpu_restore(struct gic_chip_data *gic) 693 { 694 int i; 695 u32 *ptr; 696 void __iomem *dist_base; 697 void __iomem *cpu_base; 698 699 if (WARN_ON(!gic)) 700 return; 701 702 dist_base = gic_data_dist_base(gic); 703 cpu_base = gic_data_cpu_base(gic); 704 705 if (!dist_base || !cpu_base) 706 return; 707 708 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 709 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 710 writel_relaxed(GICD_INT_EN_CLR_X32, 711 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 712 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 713 } 714 715 ptr = raw_cpu_ptr(gic->saved_ppi_active); 716 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 717 writel_relaxed(GICD_INT_EN_CLR_X32, 718 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 719 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); 720 } 721 722 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 723 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 724 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 725 726 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 727 writel_relaxed(GICD_INT_DEF_PRI_X4, 728 dist_base + GIC_DIST_PRI + i * 4); 729 730 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 731 gic_cpu_if_up(gic); 732 } 733 734 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 735 { 736 int i; 737 738 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { 739 #ifdef CONFIG_GIC_NON_BANKED 740 /* Skip over unused GICs */ 741 if (!gic_data[i].get_base) 742 continue; 743 #endif 744 switch (cmd) { 745 case CPU_PM_ENTER: 746 gic_cpu_save(&gic_data[i]); 747 break; 748 case CPU_PM_ENTER_FAILED: 749 case CPU_PM_EXIT: 750 gic_cpu_restore(&gic_data[i]); 751 break; 752 case CPU_CLUSTER_PM_ENTER: 753 gic_dist_save(&gic_data[i]); 754 break; 755 case CPU_CLUSTER_PM_ENTER_FAILED: 756 case CPU_CLUSTER_PM_EXIT: 757 gic_dist_restore(&gic_data[i]); 758 break; 759 } 760 } 761 762 return NOTIFY_OK; 763 } 764 765 static struct notifier_block gic_notifier_block = { 766 .notifier_call = gic_notifier, 767 }; 768 769 static int gic_pm_init(struct gic_chip_data *gic) 770 { 771 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 772 sizeof(u32)); 773 if (WARN_ON(!gic->saved_ppi_enable)) 774 return -ENOMEM; 775 776 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 777 sizeof(u32)); 778 if (WARN_ON(!gic->saved_ppi_active)) 779 goto free_ppi_enable; 780 781 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 782 sizeof(u32)); 783 if (WARN_ON(!gic->saved_ppi_conf)) 784 goto free_ppi_active; 785 786 if (gic == &gic_data[0]) 787 cpu_pm_register_notifier(&gic_notifier_block); 788 789 return 0; 790 791 free_ppi_active: 792 free_percpu(gic->saved_ppi_active); 793 free_ppi_enable: 794 free_percpu(gic->saved_ppi_enable); 795 796 return -ENOMEM; 797 } 798 #else 799 static int gic_pm_init(struct gic_chip_data *gic) 800 { 801 return 0; 802 } 803 #endif 804 805 #ifdef CONFIG_SMP 806 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 807 { 808 int cpu; 809 unsigned long flags, map = 0; 810 811 if (unlikely(nr_cpu_ids == 1)) { 812 /* Only one CPU? let's do a self-IPI... */ 813 writel_relaxed(2 << 24 | irq, 814 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 815 return; 816 } 817 818 gic_lock_irqsave(flags); 819 820 /* Convert our logical CPU mask into a physical one. */ 821 for_each_cpu(cpu, mask) 822 map |= gic_cpu_map[cpu]; 823 824 /* 825 * Ensure that stores to Normal memory are visible to the 826 * other CPUs before they observe us issuing the IPI. 827 */ 828 dmb(ishst); 829 830 /* this always happens on GIC0 */ 831 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 832 833 gic_unlock_irqrestore(flags); 834 } 835 #endif 836 837 #ifdef CONFIG_BL_SWITCHER 838 /* 839 * gic_send_sgi - send a SGI directly to given CPU interface number 840 * 841 * cpu_id: the ID for the destination CPU interface 842 * irq: the IPI number to send a SGI for 843 */ 844 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 845 { 846 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 847 cpu_id = 1 << cpu_id; 848 /* this always happens on GIC0 */ 849 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 850 } 851 852 /* 853 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 854 * 855 * @cpu: the logical CPU number to get the GIC ID for. 856 * 857 * Return the CPU interface ID for the given logical CPU number, 858 * or -1 if the CPU number is too large or the interface ID is 859 * unknown (more than one bit set). 860 */ 861 int gic_get_cpu_id(unsigned int cpu) 862 { 863 unsigned int cpu_bit; 864 865 if (cpu >= NR_GIC_CPU_IF) 866 return -1; 867 cpu_bit = gic_cpu_map[cpu]; 868 if (cpu_bit & (cpu_bit - 1)) 869 return -1; 870 return __ffs(cpu_bit); 871 } 872 873 /* 874 * gic_migrate_target - migrate IRQs to another CPU interface 875 * 876 * @new_cpu_id: the CPU target ID to migrate IRQs to 877 * 878 * Migrate all peripheral interrupts with a target matching the current CPU 879 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 880 * is also updated. Targets to other CPU interfaces are unchanged. 881 * This must be called with IRQs locally disabled. 882 */ 883 void gic_migrate_target(unsigned int new_cpu_id) 884 { 885 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 886 void __iomem *dist_base; 887 int i, ror_val, cpu = smp_processor_id(); 888 u32 val, cur_target_mask, active_mask; 889 890 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 891 892 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 893 if (!dist_base) 894 return; 895 gic_irqs = gic_data[gic_nr].gic_irqs; 896 897 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 898 cur_target_mask = 0x01010101 << cur_cpu_id; 899 ror_val = (cur_cpu_id - new_cpu_id) & 31; 900 901 gic_lock(); 902 903 /* Update the target interface for this logical CPU */ 904 gic_cpu_map[cpu] = 1 << new_cpu_id; 905 906 /* 907 * Find all the peripheral interrupts targeting the current 908 * CPU interface and migrate them to the new CPU interface. 909 * We skip DIST_TARGET 0 to 7 as they are read-only. 910 */ 911 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 912 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 913 active_mask = val & cur_target_mask; 914 if (active_mask) { 915 val &= ~active_mask; 916 val |= ror32(active_mask, ror_val); 917 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 918 } 919 } 920 921 gic_unlock(); 922 923 /* 924 * Now let's migrate and clear any potential SGIs that might be 925 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 926 * is a banked register, we can only forward the SGI using 927 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 928 * doesn't use that information anyway. 929 * 930 * For the same reason we do not adjust SGI source information 931 * for previously sent SGIs by us to other CPUs either. 932 */ 933 for (i = 0; i < 16; i += 4) { 934 int j; 935 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 936 if (!val) 937 continue; 938 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 939 for (j = i; j < i + 4; j++) { 940 if (val & 0xff) 941 writel_relaxed((1 << (new_cpu_id + 16)) | j, 942 dist_base + GIC_DIST_SOFTINT); 943 val >>= 8; 944 } 945 } 946 } 947 948 /* 949 * gic_get_sgir_physaddr - get the physical address for the SGI register 950 * 951 * REturn the physical address of the SGI register to be used 952 * by some early assembly code when the kernel is not yet available. 953 */ 954 static unsigned long gic_dist_physaddr; 955 956 unsigned long gic_get_sgir_physaddr(void) 957 { 958 if (!gic_dist_physaddr) 959 return 0; 960 return gic_dist_physaddr + GIC_DIST_SOFTINT; 961 } 962 963 static void __init gic_init_physaddr(struct device_node *node) 964 { 965 struct resource res; 966 if (of_address_to_resource(node, 0, &res) == 0) { 967 gic_dist_physaddr = res.start; 968 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 969 } 970 } 971 972 #else 973 #define gic_init_physaddr(node) do { } while (0) 974 #endif 975 976 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 977 irq_hw_number_t hw) 978 { 979 struct gic_chip_data *gic = d->host_data; 980 981 if (hw < 32) { 982 irq_set_percpu_devid(irq); 983 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 984 handle_percpu_devid_irq, NULL, NULL); 985 irq_set_status_flags(irq, IRQ_NOAUTOEN); 986 } else { 987 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 988 handle_fasteoi_irq, NULL, NULL); 989 irq_set_probe(irq); 990 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 991 } 992 return 0; 993 } 994 995 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 996 { 997 } 998 999 static int gic_irq_domain_translate(struct irq_domain *d, 1000 struct irq_fwspec *fwspec, 1001 unsigned long *hwirq, 1002 unsigned int *type) 1003 { 1004 if (is_of_node(fwspec->fwnode)) { 1005 if (fwspec->param_count < 3) 1006 return -EINVAL; 1007 1008 /* Get the interrupt number and add 16 to skip over SGIs */ 1009 *hwirq = fwspec->param[1] + 16; 1010 1011 /* 1012 * For SPIs, we need to add 16 more to get the GIC irq 1013 * ID number 1014 */ 1015 if (!fwspec->param[0]) 1016 *hwirq += 16; 1017 1018 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1019 1020 /* Make it clear that broken DTs are... broken */ 1021 WARN_ON(*type == IRQ_TYPE_NONE); 1022 return 0; 1023 } 1024 1025 if (is_fwnode_irqchip(fwspec->fwnode)) { 1026 if(fwspec->param_count != 2) 1027 return -EINVAL; 1028 1029 *hwirq = fwspec->param[0]; 1030 *type = fwspec->param[1]; 1031 1032 WARN_ON(*type == IRQ_TYPE_NONE); 1033 return 0; 1034 } 1035 1036 return -EINVAL; 1037 } 1038 1039 static int gic_starting_cpu(unsigned int cpu) 1040 { 1041 gic_cpu_init(&gic_data[0]); 1042 return 0; 1043 } 1044 1045 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1046 unsigned int nr_irqs, void *arg) 1047 { 1048 int i, ret; 1049 irq_hw_number_t hwirq; 1050 unsigned int type = IRQ_TYPE_NONE; 1051 struct irq_fwspec *fwspec = arg; 1052 1053 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1054 if (ret) 1055 return ret; 1056 1057 for (i = 0; i < nr_irqs; i++) { 1058 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 1059 if (ret) 1060 return ret; 1061 } 1062 1063 return 0; 1064 } 1065 1066 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 1067 .translate = gic_irq_domain_translate, 1068 .alloc = gic_irq_domain_alloc, 1069 .free = irq_domain_free_irqs_top, 1070 }; 1071 1072 static const struct irq_domain_ops gic_irq_domain_ops = { 1073 .map = gic_irq_domain_map, 1074 .unmap = gic_irq_domain_unmap, 1075 }; 1076 1077 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, 1078 const char *name, bool use_eoimode1) 1079 { 1080 /* Initialize irq_chip */ 1081 gic->chip = gic_chip; 1082 gic->chip.name = name; 1083 gic->chip.parent_device = dev; 1084 1085 if (use_eoimode1) { 1086 gic->chip.irq_mask = gic_eoimode1_mask_irq; 1087 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; 1088 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; 1089 } 1090 1091 #ifdef CONFIG_SMP 1092 if (gic == &gic_data[0]) 1093 gic->chip.irq_set_affinity = gic_set_affinity; 1094 #endif 1095 } 1096 1097 static int gic_init_bases(struct gic_chip_data *gic, 1098 struct fwnode_handle *handle) 1099 { 1100 int gic_irqs, ret; 1101 1102 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1103 /* Frankein-GIC without banked registers... */ 1104 unsigned int cpu; 1105 1106 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 1107 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 1108 if (WARN_ON(!gic->dist_base.percpu_base || 1109 !gic->cpu_base.percpu_base)) { 1110 ret = -ENOMEM; 1111 goto error; 1112 } 1113 1114 for_each_possible_cpu(cpu) { 1115 u32 mpidr = cpu_logical_map(cpu); 1116 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 1117 unsigned long offset = gic->percpu_offset * core_id; 1118 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 1119 gic->raw_dist_base + offset; 1120 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = 1121 gic->raw_cpu_base + offset; 1122 } 1123 1124 gic_set_base_accessor(gic, gic_get_percpu_base); 1125 } else { 1126 /* Normal, sane GIC... */ 1127 WARN(gic->percpu_offset, 1128 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 1129 gic->percpu_offset); 1130 gic->dist_base.common_base = gic->raw_dist_base; 1131 gic->cpu_base.common_base = gic->raw_cpu_base; 1132 gic_set_base_accessor(gic, gic_get_common_base); 1133 } 1134 1135 /* 1136 * Find out how many interrupts are supported. 1137 * The GIC only supports up to 1020 interrupt sources. 1138 */ 1139 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1140 gic_irqs = (gic_irqs + 1) * 32; 1141 if (gic_irqs > 1020) 1142 gic_irqs = 1020; 1143 gic->gic_irqs = gic_irqs; 1144 1145 if (handle) { /* DT/ACPI */ 1146 gic->domain = irq_domain_create_linear(handle, gic_irqs, 1147 &gic_irq_domain_hierarchy_ops, 1148 gic); 1149 } else { /* Legacy support */ 1150 /* 1151 * For primary GICs, skip over SGIs. 1152 * No secondary GIC support whatsoever. 1153 */ 1154 int irq_base; 1155 1156 gic_irqs -= 16; /* calculate # of irqs to allocate */ 1157 1158 irq_base = irq_alloc_descs(16, 16, gic_irqs, 1159 numa_node_id()); 1160 if (irq_base < 0) { 1161 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n"); 1162 irq_base = 16; 1163 } 1164 1165 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, 1166 16, &gic_irq_domain_ops, gic); 1167 } 1168 1169 if (WARN_ON(!gic->domain)) { 1170 ret = -ENODEV; 1171 goto error; 1172 } 1173 1174 gic_dist_init(gic); 1175 ret = gic_cpu_init(gic); 1176 if (ret) 1177 goto error; 1178 1179 ret = gic_pm_init(gic); 1180 if (ret) 1181 goto error; 1182 1183 return 0; 1184 1185 error: 1186 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1187 free_percpu(gic->dist_base.percpu_base); 1188 free_percpu(gic->cpu_base.percpu_base); 1189 } 1190 1191 return ret; 1192 } 1193 1194 static int __init __gic_init_bases(struct gic_chip_data *gic, 1195 struct fwnode_handle *handle) 1196 { 1197 char *name; 1198 int i, ret; 1199 1200 if (WARN_ON(!gic || gic->domain)) 1201 return -EINVAL; 1202 1203 if (gic == &gic_data[0]) { 1204 /* 1205 * Initialize the CPU interface map to all CPUs. 1206 * It will be refined as each CPU probes its ID. 1207 * This is only necessary for the primary GIC. 1208 */ 1209 for (i = 0; i < NR_GIC_CPU_IF; i++) 1210 gic_cpu_map[i] = 0xff; 1211 #ifdef CONFIG_SMP 1212 set_smp_cross_call(gic_raise_softirq); 1213 #endif 1214 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 1215 "irqchip/arm/gic:starting", 1216 gic_starting_cpu, NULL); 1217 set_handle_irq(gic_handle_irq); 1218 if (static_branch_likely(&supports_deactivate_key)) 1219 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1220 } 1221 1222 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { 1223 name = kasprintf(GFP_KERNEL, "GICv2"); 1224 gic_init_chip(gic, NULL, name, true); 1225 } else { 1226 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); 1227 gic_init_chip(gic, NULL, name, false); 1228 } 1229 1230 ret = gic_init_bases(gic, handle); 1231 if (ret) 1232 kfree(name); 1233 1234 return ret; 1235 } 1236 1237 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base) 1238 { 1239 struct gic_chip_data *gic; 1240 1241 /* 1242 * Non-DT/ACPI systems won't run a hypervisor, so let's not 1243 * bother with these... 1244 */ 1245 static_branch_disable(&supports_deactivate_key); 1246 1247 gic = &gic_data[0]; 1248 gic->raw_dist_base = dist_base; 1249 gic->raw_cpu_base = cpu_base; 1250 1251 __gic_init_bases(gic, NULL); 1252 } 1253 1254 static void gic_teardown(struct gic_chip_data *gic) 1255 { 1256 if (WARN_ON(!gic)) 1257 return; 1258 1259 if (gic->raw_dist_base) 1260 iounmap(gic->raw_dist_base); 1261 if (gic->raw_cpu_base) 1262 iounmap(gic->raw_cpu_base); 1263 } 1264 1265 #ifdef CONFIG_OF 1266 static int gic_cnt __initdata; 1267 static bool gicv2_force_probe; 1268 1269 static int __init gicv2_force_probe_cfg(char *buf) 1270 { 1271 return strtobool(buf, &gicv2_force_probe); 1272 } 1273 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg); 1274 1275 static bool gic_check_eoimode(struct device_node *node, void __iomem **base) 1276 { 1277 struct resource cpuif_res; 1278 1279 of_address_to_resource(node, 1, &cpuif_res); 1280 1281 if (!is_hyp_mode_available()) 1282 return false; 1283 if (resource_size(&cpuif_res) < SZ_8K) { 1284 void __iomem *alt; 1285 /* 1286 * Check for a stupid firmware that only exposes the 1287 * first page of a GICv2. 1288 */ 1289 if (!gic_check_gicv2(*base)) 1290 return false; 1291 1292 if (!gicv2_force_probe) { 1293 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); 1294 return false; 1295 } 1296 1297 alt = ioremap(cpuif_res.start, SZ_8K); 1298 if (!alt) 1299 return false; 1300 if (!gic_check_gicv2(alt + SZ_4K)) { 1301 /* 1302 * The first page was that of a GICv2, and 1303 * the second was *something*. Let's trust it 1304 * to be a GICv2, and update the mapping. 1305 */ 1306 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", 1307 &cpuif_res.start); 1308 iounmap(*base); 1309 *base = alt; 1310 return true; 1311 } 1312 1313 /* 1314 * We detected *two* initial GICv2 pages in a 1315 * row. Could be a GICv2 aliased over two 64kB 1316 * pages. Update the resource, map the iospace, and 1317 * pray. 1318 */ 1319 iounmap(alt); 1320 alt = ioremap(cpuif_res.start, SZ_128K); 1321 if (!alt) 1322 return false; 1323 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", 1324 &cpuif_res.start); 1325 cpuif_res.end = cpuif_res.start + SZ_128K -1; 1326 iounmap(*base); 1327 *base = alt; 1328 } 1329 if (resource_size(&cpuif_res) == SZ_128K) { 1330 /* 1331 * Verify that we have the first 4kB of a GICv2 1332 * aliased over the first 64kB by checking the 1333 * GICC_IIDR register on both ends. 1334 */ 1335 if (!gic_check_gicv2(*base) || 1336 !gic_check_gicv2(*base + 0xf000)) 1337 return false; 1338 1339 /* 1340 * Move the base up by 60kB, so that we have a 8kB 1341 * contiguous region, which allows us to use GICC_DIR 1342 * at its normal offset. Please pass me that bucket. 1343 */ 1344 *base += 0xf000; 1345 cpuif_res.start += 0xf000; 1346 pr_warn("GIC: Adjusting CPU interface base to %pa\n", 1347 &cpuif_res.start); 1348 } 1349 1350 return true; 1351 } 1352 1353 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) 1354 { 1355 if (!gic || !node) 1356 return -EINVAL; 1357 1358 gic->raw_dist_base = of_iomap(node, 0); 1359 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) 1360 goto error; 1361 1362 gic->raw_cpu_base = of_iomap(node, 1); 1363 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) 1364 goto error; 1365 1366 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) 1367 gic->percpu_offset = 0; 1368 1369 return 0; 1370 1371 error: 1372 gic_teardown(gic); 1373 1374 return -ENOMEM; 1375 } 1376 1377 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1378 { 1379 int ret; 1380 1381 if (!dev || !dev->of_node || !gic || !irq) 1382 return -EINVAL; 1383 1384 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); 1385 if (!*gic) 1386 return -ENOMEM; 1387 1388 gic_init_chip(*gic, dev, dev->of_node->name, false); 1389 1390 ret = gic_of_setup(*gic, dev->of_node); 1391 if (ret) 1392 return ret; 1393 1394 ret = gic_init_bases(*gic, &dev->of_node->fwnode); 1395 if (ret) { 1396 gic_teardown(*gic); 1397 return ret; 1398 } 1399 1400 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); 1401 1402 return 0; 1403 } 1404 1405 static void __init gic_of_setup_kvm_info(struct device_node *node) 1406 { 1407 int ret; 1408 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1409 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1410 1411 gic_v2_kvm_info.type = GIC_V2; 1412 1413 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1414 if (!gic_v2_kvm_info.maint_irq) 1415 return; 1416 1417 ret = of_address_to_resource(node, 2, vctrl_res); 1418 if (ret) 1419 return; 1420 1421 ret = of_address_to_resource(node, 3, vcpu_res); 1422 if (ret) 1423 return; 1424 1425 if (static_branch_likely(&supports_deactivate_key)) 1426 gic_set_kvm_info(&gic_v2_kvm_info); 1427 } 1428 1429 int __init 1430 gic_of_init(struct device_node *node, struct device_node *parent) 1431 { 1432 struct gic_chip_data *gic; 1433 int irq, ret; 1434 1435 if (WARN_ON(!node)) 1436 return -ENODEV; 1437 1438 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) 1439 return -EINVAL; 1440 1441 gic = &gic_data[gic_cnt]; 1442 1443 ret = gic_of_setup(gic, node); 1444 if (ret) 1445 return ret; 1446 1447 /* 1448 * Disable split EOI/Deactivate if either HYP is not available 1449 * or the CPU interface is too small. 1450 */ 1451 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) 1452 static_branch_disable(&supports_deactivate_key); 1453 1454 ret = __gic_init_bases(gic, &node->fwnode); 1455 if (ret) { 1456 gic_teardown(gic); 1457 return ret; 1458 } 1459 1460 if (!gic_cnt) { 1461 gic_init_physaddr(node); 1462 gic_of_setup_kvm_info(node); 1463 } 1464 1465 if (parent) { 1466 irq = irq_of_parse_and_map(node, 0); 1467 gic_cascade_irq(gic_cnt, irq); 1468 } 1469 1470 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1471 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); 1472 1473 gic_cnt++; 1474 return 0; 1475 } 1476 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1477 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1478 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1479 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1480 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1481 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1482 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1483 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1484 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1485 #else 1486 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1487 { 1488 return -ENOTSUPP; 1489 } 1490 #endif 1491 1492 #ifdef CONFIG_ACPI 1493 static struct 1494 { 1495 phys_addr_t cpu_phys_base; 1496 u32 maint_irq; 1497 int maint_irq_mode; 1498 phys_addr_t vctrl_base; 1499 phys_addr_t vcpu_base; 1500 } acpi_data __initdata; 1501 1502 static int __init 1503 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header, 1504 const unsigned long end) 1505 { 1506 struct acpi_madt_generic_interrupt *processor; 1507 phys_addr_t gic_cpu_base; 1508 static int cpu_base_assigned; 1509 1510 processor = (struct acpi_madt_generic_interrupt *)header; 1511 1512 if (BAD_MADT_GICC_ENTRY(processor, end)) 1513 return -EINVAL; 1514 1515 /* 1516 * There is no support for non-banked GICv1/2 register in ACPI spec. 1517 * All CPU interface addresses have to be the same. 1518 */ 1519 gic_cpu_base = processor->base_address; 1520 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) 1521 return -EINVAL; 1522 1523 acpi_data.cpu_phys_base = gic_cpu_base; 1524 acpi_data.maint_irq = processor->vgic_interrupt; 1525 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1526 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1527 acpi_data.vctrl_base = processor->gich_base_address; 1528 acpi_data.vcpu_base = processor->gicv_base_address; 1529 1530 cpu_base_assigned = 1; 1531 return 0; 1532 } 1533 1534 /* The things you have to do to just *count* something... */ 1535 static int __init acpi_dummy_func(union acpi_subtable_headers *header, 1536 const unsigned long end) 1537 { 1538 return 0; 1539 } 1540 1541 static bool __init acpi_gic_redist_is_present(void) 1542 { 1543 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1544 acpi_dummy_func, 0) > 0; 1545 } 1546 1547 static bool __init gic_validate_dist(struct acpi_subtable_header *header, 1548 struct acpi_probe_entry *ape) 1549 { 1550 struct acpi_madt_generic_distributor *dist; 1551 dist = (struct acpi_madt_generic_distributor *)header; 1552 1553 return (dist->version == ape->driver_data && 1554 (dist->version != ACPI_MADT_GIC_VERSION_NONE || 1555 !acpi_gic_redist_is_present())); 1556 } 1557 1558 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) 1559 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) 1560 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1561 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1562 1563 static void __init gic_acpi_setup_kvm_info(void) 1564 { 1565 int irq; 1566 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1567 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1568 1569 gic_v2_kvm_info.type = GIC_V2; 1570 1571 if (!acpi_data.vctrl_base) 1572 return; 1573 1574 vctrl_res->flags = IORESOURCE_MEM; 1575 vctrl_res->start = acpi_data.vctrl_base; 1576 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; 1577 1578 if (!acpi_data.vcpu_base) 1579 return; 1580 1581 vcpu_res->flags = IORESOURCE_MEM; 1582 vcpu_res->start = acpi_data.vcpu_base; 1583 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1584 1585 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1586 acpi_data.maint_irq_mode, 1587 ACPI_ACTIVE_HIGH); 1588 if (irq <= 0) 1589 return; 1590 1591 gic_v2_kvm_info.maint_irq = irq; 1592 1593 gic_set_kvm_info(&gic_v2_kvm_info); 1594 } 1595 1596 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, 1597 const unsigned long end) 1598 { 1599 struct acpi_madt_generic_distributor *dist; 1600 struct fwnode_handle *domain_handle; 1601 struct gic_chip_data *gic = &gic_data[0]; 1602 int count, ret; 1603 1604 /* Collect CPU base addresses */ 1605 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1606 gic_acpi_parse_madt_cpu, 0); 1607 if (count <= 0) { 1608 pr_err("No valid GICC entries exist\n"); 1609 return -EINVAL; 1610 } 1611 1612 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1613 if (!gic->raw_cpu_base) { 1614 pr_err("Unable to map GICC registers\n"); 1615 return -ENOMEM; 1616 } 1617 1618 dist = (struct acpi_madt_generic_distributor *)header; 1619 gic->raw_dist_base = ioremap(dist->base_address, 1620 ACPI_GICV2_DIST_MEM_SIZE); 1621 if (!gic->raw_dist_base) { 1622 pr_err("Unable to map GICD registers\n"); 1623 gic_teardown(gic); 1624 return -ENOMEM; 1625 } 1626 1627 /* 1628 * Disable split EOI/Deactivate if HYP is not available. ACPI 1629 * guarantees that we'll always have a GICv2, so the CPU 1630 * interface will always be the right size. 1631 */ 1632 if (!is_hyp_mode_available()) 1633 static_branch_disable(&supports_deactivate_key); 1634 1635 /* 1636 * Initialize GIC instance zero (no multi-GIC support). 1637 */ 1638 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 1639 if (!domain_handle) { 1640 pr_err("Unable to allocate domain handle\n"); 1641 gic_teardown(gic); 1642 return -ENOMEM; 1643 } 1644 1645 ret = __gic_init_bases(gic, domain_handle); 1646 if (ret) { 1647 pr_err("Failed to initialise GIC\n"); 1648 irq_domain_free_fwnode(domain_handle); 1649 gic_teardown(gic); 1650 return ret; 1651 } 1652 1653 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1654 1655 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1656 gicv2m_init(NULL, gic_data[0].domain); 1657 1658 if (static_branch_likely(&supports_deactivate_key)) 1659 gic_acpi_setup_kvm_info(); 1660 1661 return 0; 1662 } 1663 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1664 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, 1665 gic_v2_acpi_init); 1666 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1667 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, 1668 gic_v2_acpi_init); 1669 #endif 1670