xref: /openbmc/linux/drivers/irqchip/irq-gic.c (revision 92a2c6b2)
1 /*
2  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
3  *
4  * This program is free software; you can redistribute it and/or modify
5  * it under the terms of the GNU General Public License version 2 as
6  * published by the Free Software Foundation.
7  *
8  * Interrupt architecture for the GIC:
9  *
10  * o There is one Interrupt Distributor, which receives interrupts
11  *   from system devices and sends them to the Interrupt Controllers.
12  *
13  * o There is one CPU Interface per CPU, which sends interrupts sent
14  *   by the Distributor, and interrupts generated locally, to the
15  *   associated CPU. The base address of the CPU interface is usually
16  *   aliased so that the same address points to different chips depending
17  *   on the CPU it is accessed from.
18  *
19  * Note that IRQs 0-31 are special - they are local to each CPU.
20  * As such, the enable set/clear, pending set/clear and active bit
21  * registers are banked per-cpu for these sources.
22  */
23 #include <linux/init.h>
24 #include <linux/kernel.h>
25 #include <linux/err.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/smp.h>
29 #include <linux/cpu.h>
30 #include <linux/cpu_pm.h>
31 #include <linux/cpumask.h>
32 #include <linux/io.h>
33 #include <linux/of.h>
34 #include <linux/of_address.h>
35 #include <linux/of_irq.h>
36 #include <linux/irqdomain.h>
37 #include <linux/interrupt.h>
38 #include <linux/percpu.h>
39 #include <linux/slab.h>
40 #include <linux/irqchip/chained_irq.h>
41 #include <linux/irqchip/arm-gic.h>
42 
43 #include <asm/cputype.h>
44 #include <asm/irq.h>
45 #include <asm/exception.h>
46 #include <asm/smp_plat.h>
47 
48 #include "irq-gic-common.h"
49 #include "irqchip.h"
50 
51 union gic_base {
52 	void __iomem *common_base;
53 	void __percpu * __iomem *percpu_base;
54 };
55 
56 struct gic_chip_data {
57 	union gic_base dist_base;
58 	union gic_base cpu_base;
59 #ifdef CONFIG_CPU_PM
60 	u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)];
61 	u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)];
62 	u32 saved_spi_target[DIV_ROUND_UP(1020, 4)];
63 	u32 __percpu *saved_ppi_enable;
64 	u32 __percpu *saved_ppi_conf;
65 #endif
66 	struct irq_domain *domain;
67 	unsigned int gic_irqs;
68 #ifdef CONFIG_GIC_NON_BANKED
69 	void __iomem *(*get_base)(union gic_base *);
70 #endif
71 };
72 
73 static DEFINE_RAW_SPINLOCK(irq_controller_lock);
74 
75 /*
76  * The GIC mapping of CPU interfaces does not necessarily match
77  * the logical CPU numbering.  Let's use a mapping as returned
78  * by the GIC itself.
79  */
80 #define NR_GIC_CPU_IF 8
81 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly;
82 
83 /*
84  * Supported arch specific GIC irq extension.
85  * Default make them NULL.
86  */
87 struct irq_chip gic_arch_extn = {
88 	.irq_eoi	= NULL,
89 	.irq_mask	= NULL,
90 	.irq_unmask	= NULL,
91 	.irq_retrigger	= NULL,
92 	.irq_set_type	= NULL,
93 	.irq_set_wake	= NULL,
94 };
95 
96 #ifndef MAX_GIC_NR
97 #define MAX_GIC_NR	1
98 #endif
99 
100 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly;
101 
102 #ifdef CONFIG_GIC_NON_BANKED
103 static void __iomem *gic_get_percpu_base(union gic_base *base)
104 {
105 	return raw_cpu_read(*base->percpu_base);
106 }
107 
108 static void __iomem *gic_get_common_base(union gic_base *base)
109 {
110 	return base->common_base;
111 }
112 
113 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data)
114 {
115 	return data->get_base(&data->dist_base);
116 }
117 
118 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data)
119 {
120 	return data->get_base(&data->cpu_base);
121 }
122 
123 static inline void gic_set_base_accessor(struct gic_chip_data *data,
124 					 void __iomem *(*f)(union gic_base *))
125 {
126 	data->get_base = f;
127 }
128 #else
129 #define gic_data_dist_base(d)	((d)->dist_base.common_base)
130 #define gic_data_cpu_base(d)	((d)->cpu_base.common_base)
131 #define gic_set_base_accessor(d, f)
132 #endif
133 
134 static inline void __iomem *gic_dist_base(struct irq_data *d)
135 {
136 	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
137 	return gic_data_dist_base(gic_data);
138 }
139 
140 static inline void __iomem *gic_cpu_base(struct irq_data *d)
141 {
142 	struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d);
143 	return gic_data_cpu_base(gic_data);
144 }
145 
146 static inline unsigned int gic_irq(struct irq_data *d)
147 {
148 	return d->hwirq;
149 }
150 
151 /*
152  * Routines to acknowledge, disable and enable interrupts
153  */
154 static void gic_mask_irq(struct irq_data *d)
155 {
156 	u32 mask = 1 << (gic_irq(d) % 32);
157 
158 	raw_spin_lock(&irq_controller_lock);
159 	writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_CLEAR + (gic_irq(d) / 32) * 4);
160 	if (gic_arch_extn.irq_mask)
161 		gic_arch_extn.irq_mask(d);
162 	raw_spin_unlock(&irq_controller_lock);
163 }
164 
165 static void gic_unmask_irq(struct irq_data *d)
166 {
167 	u32 mask = 1 << (gic_irq(d) % 32);
168 
169 	raw_spin_lock(&irq_controller_lock);
170 	if (gic_arch_extn.irq_unmask)
171 		gic_arch_extn.irq_unmask(d);
172 	writel_relaxed(mask, gic_dist_base(d) + GIC_DIST_ENABLE_SET + (gic_irq(d) / 32) * 4);
173 	raw_spin_unlock(&irq_controller_lock);
174 }
175 
176 static void gic_eoi_irq(struct irq_data *d)
177 {
178 	if (gic_arch_extn.irq_eoi) {
179 		raw_spin_lock(&irq_controller_lock);
180 		gic_arch_extn.irq_eoi(d);
181 		raw_spin_unlock(&irq_controller_lock);
182 	}
183 
184 	writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI);
185 }
186 
187 static int gic_set_type(struct irq_data *d, unsigned int type)
188 {
189 	void __iomem *base = gic_dist_base(d);
190 	unsigned int gicirq = gic_irq(d);
191 	int ret;
192 
193 	/* Interrupt configuration for SGIs can't be changed */
194 	if (gicirq < 16)
195 		return -EINVAL;
196 
197 	/* SPIs have restrictions on the supported types */
198 	if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH &&
199 			    type != IRQ_TYPE_EDGE_RISING)
200 		return -EINVAL;
201 
202 	raw_spin_lock(&irq_controller_lock);
203 
204 	if (gic_arch_extn.irq_set_type)
205 		gic_arch_extn.irq_set_type(d, type);
206 
207 	ret = gic_configure_irq(gicirq, type, base, NULL);
208 
209 	raw_spin_unlock(&irq_controller_lock);
210 
211 	return ret;
212 }
213 
214 static int gic_retrigger(struct irq_data *d)
215 {
216 	if (gic_arch_extn.irq_retrigger)
217 		return gic_arch_extn.irq_retrigger(d);
218 
219 	/* the genirq layer expects 0 if we can't retrigger in hardware */
220 	return 0;
221 }
222 
223 #ifdef CONFIG_SMP
224 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
225 			    bool force)
226 {
227 	void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
228 	unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
229 	u32 val, mask, bit;
230 
231 	if (!force)
232 		cpu = cpumask_any_and(mask_val, cpu_online_mask);
233 	else
234 		cpu = cpumask_first(mask_val);
235 
236 	if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
237 		return -EINVAL;
238 
239 	raw_spin_lock(&irq_controller_lock);
240 	mask = 0xff << shift;
241 	bit = gic_cpu_map[cpu] << shift;
242 	val = readl_relaxed(reg) & ~mask;
243 	writel_relaxed(val | bit, reg);
244 	raw_spin_unlock(&irq_controller_lock);
245 
246 	return IRQ_SET_MASK_OK;
247 }
248 #endif
249 
250 #ifdef CONFIG_PM
251 static int gic_set_wake(struct irq_data *d, unsigned int on)
252 {
253 	int ret = -ENXIO;
254 
255 	if (gic_arch_extn.irq_set_wake)
256 		ret = gic_arch_extn.irq_set_wake(d, on);
257 
258 	return ret;
259 }
260 
261 #else
262 #define gic_set_wake	NULL
263 #endif
264 
265 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs)
266 {
267 	u32 irqstat, irqnr;
268 	struct gic_chip_data *gic = &gic_data[0];
269 	void __iomem *cpu_base = gic_data_cpu_base(gic);
270 
271 	do {
272 		irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK);
273 		irqnr = irqstat & GICC_IAR_INT_ID_MASK;
274 
275 		if (likely(irqnr > 15 && irqnr < 1021)) {
276 			handle_domain_irq(gic->domain, irqnr, regs);
277 			continue;
278 		}
279 		if (irqnr < 16) {
280 			writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI);
281 #ifdef CONFIG_SMP
282 			handle_IPI(irqnr, regs);
283 #endif
284 			continue;
285 		}
286 		break;
287 	} while (1);
288 }
289 
290 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc)
291 {
292 	struct gic_chip_data *chip_data = irq_get_handler_data(irq);
293 	struct irq_chip *chip = irq_get_chip(irq);
294 	unsigned int cascade_irq, gic_irq;
295 	unsigned long status;
296 
297 	chained_irq_enter(chip, desc);
298 
299 	raw_spin_lock(&irq_controller_lock);
300 	status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK);
301 	raw_spin_unlock(&irq_controller_lock);
302 
303 	gic_irq = (status & GICC_IAR_INT_ID_MASK);
304 	if (gic_irq == GICC_INT_SPURIOUS)
305 		goto out;
306 
307 	cascade_irq = irq_find_mapping(chip_data->domain, gic_irq);
308 	if (unlikely(gic_irq < 32 || gic_irq > 1020))
309 		handle_bad_irq(cascade_irq, desc);
310 	else
311 		generic_handle_irq(cascade_irq);
312 
313  out:
314 	chained_irq_exit(chip, desc);
315 }
316 
317 static struct irq_chip gic_chip = {
318 	.name			= "GIC",
319 	.irq_mask		= gic_mask_irq,
320 	.irq_unmask		= gic_unmask_irq,
321 	.irq_eoi		= gic_eoi_irq,
322 	.irq_set_type		= gic_set_type,
323 	.irq_retrigger		= gic_retrigger,
324 #ifdef CONFIG_SMP
325 	.irq_set_affinity	= gic_set_affinity,
326 #endif
327 	.irq_set_wake		= gic_set_wake,
328 };
329 
330 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq)
331 {
332 	if (gic_nr >= MAX_GIC_NR)
333 		BUG();
334 	if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0)
335 		BUG();
336 	irq_set_chained_handler(irq, gic_handle_cascade_irq);
337 }
338 
339 static u8 gic_get_cpumask(struct gic_chip_data *gic)
340 {
341 	void __iomem *base = gic_data_dist_base(gic);
342 	u32 mask, i;
343 
344 	for (i = mask = 0; i < 32; i += 4) {
345 		mask = readl_relaxed(base + GIC_DIST_TARGET + i);
346 		mask |= mask >> 16;
347 		mask |= mask >> 8;
348 		if (mask)
349 			break;
350 	}
351 
352 	if (!mask)
353 		pr_crit("GIC CPU mask not found - kernel will fail to boot.\n");
354 
355 	return mask;
356 }
357 
358 static void gic_cpu_if_up(void)
359 {
360 	void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
361 	u32 bypass = 0;
362 
363 	/*
364 	* Preserve bypass disable bits to be written back later
365 	*/
366 	bypass = readl(cpu_base + GIC_CPU_CTRL);
367 	bypass &= GICC_DIS_BYPASS_MASK;
368 
369 	writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL);
370 }
371 
372 
373 static void __init gic_dist_init(struct gic_chip_data *gic)
374 {
375 	unsigned int i;
376 	u32 cpumask;
377 	unsigned int gic_irqs = gic->gic_irqs;
378 	void __iomem *base = gic_data_dist_base(gic);
379 
380 	writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL);
381 
382 	/*
383 	 * Set all global interrupts to this CPU only.
384 	 */
385 	cpumask = gic_get_cpumask(gic);
386 	cpumask |= cpumask << 8;
387 	cpumask |= cpumask << 16;
388 	for (i = 32; i < gic_irqs; i += 4)
389 		writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
390 
391 	gic_dist_config(base, gic_irqs, NULL);
392 
393 	writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL);
394 }
395 
396 static void gic_cpu_init(struct gic_chip_data *gic)
397 {
398 	void __iomem *dist_base = gic_data_dist_base(gic);
399 	void __iomem *base = gic_data_cpu_base(gic);
400 	unsigned int cpu_mask, cpu = smp_processor_id();
401 	int i;
402 
403 	/*
404 	 * Get what the GIC says our CPU mask is.
405 	 */
406 	BUG_ON(cpu >= NR_GIC_CPU_IF);
407 	cpu_mask = gic_get_cpumask(gic);
408 	gic_cpu_map[cpu] = cpu_mask;
409 
410 	/*
411 	 * Clear our mask from the other map entries in case they're
412 	 * still undefined.
413 	 */
414 	for (i = 0; i < NR_GIC_CPU_IF; i++)
415 		if (i != cpu)
416 			gic_cpu_map[i] &= ~cpu_mask;
417 
418 	gic_cpu_config(dist_base, NULL);
419 
420 	writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK);
421 	gic_cpu_if_up();
422 }
423 
424 void gic_cpu_if_down(void)
425 {
426 	void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]);
427 	u32 val = 0;
428 
429 	val = readl(cpu_base + GIC_CPU_CTRL);
430 	val &= ~GICC_ENABLE;
431 	writel_relaxed(val, cpu_base + GIC_CPU_CTRL);
432 }
433 
434 #ifdef CONFIG_CPU_PM
435 /*
436  * Saves the GIC distributor registers during suspend or idle.  Must be called
437  * with interrupts disabled but before powering down the GIC.  After calling
438  * this function, no interrupts will be delivered by the GIC, and another
439  * platform-specific wakeup source must be enabled.
440  */
441 static void gic_dist_save(unsigned int gic_nr)
442 {
443 	unsigned int gic_irqs;
444 	void __iomem *dist_base;
445 	int i;
446 
447 	if (gic_nr >= MAX_GIC_NR)
448 		BUG();
449 
450 	gic_irqs = gic_data[gic_nr].gic_irqs;
451 	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
452 
453 	if (!dist_base)
454 		return;
455 
456 	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
457 		gic_data[gic_nr].saved_spi_conf[i] =
458 			readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
459 
460 	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
461 		gic_data[gic_nr].saved_spi_target[i] =
462 			readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
463 
464 	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
465 		gic_data[gic_nr].saved_spi_enable[i] =
466 			readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
467 }
468 
469 /*
470  * Restores the GIC distributor registers during resume or when coming out of
471  * idle.  Must be called before enabling interrupts.  If a level interrupt
472  * that occured while the GIC was suspended is still present, it will be
473  * handled normally, but any edge interrupts that occured will not be seen by
474  * the GIC and need to be handled by the platform-specific wakeup source.
475  */
476 static void gic_dist_restore(unsigned int gic_nr)
477 {
478 	unsigned int gic_irqs;
479 	unsigned int i;
480 	void __iomem *dist_base;
481 
482 	if (gic_nr >= MAX_GIC_NR)
483 		BUG();
484 
485 	gic_irqs = gic_data[gic_nr].gic_irqs;
486 	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
487 
488 	if (!dist_base)
489 		return;
490 
491 	writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL);
492 
493 	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++)
494 		writel_relaxed(gic_data[gic_nr].saved_spi_conf[i],
495 			dist_base + GIC_DIST_CONFIG + i * 4);
496 
497 	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
498 		writel_relaxed(GICD_INT_DEF_PRI_X4,
499 			dist_base + GIC_DIST_PRI + i * 4);
500 
501 	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++)
502 		writel_relaxed(gic_data[gic_nr].saved_spi_target[i],
503 			dist_base + GIC_DIST_TARGET + i * 4);
504 
505 	for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++)
506 		writel_relaxed(gic_data[gic_nr].saved_spi_enable[i],
507 			dist_base + GIC_DIST_ENABLE_SET + i * 4);
508 
509 	writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL);
510 }
511 
512 static void gic_cpu_save(unsigned int gic_nr)
513 {
514 	int i;
515 	u32 *ptr;
516 	void __iomem *dist_base;
517 	void __iomem *cpu_base;
518 
519 	if (gic_nr >= MAX_GIC_NR)
520 		BUG();
521 
522 	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
523 	cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
524 
525 	if (!dist_base || !cpu_base)
526 		return;
527 
528 	ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
529 	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
530 		ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4);
531 
532 	ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
533 	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
534 		ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4);
535 
536 }
537 
538 static void gic_cpu_restore(unsigned int gic_nr)
539 {
540 	int i;
541 	u32 *ptr;
542 	void __iomem *dist_base;
543 	void __iomem *cpu_base;
544 
545 	if (gic_nr >= MAX_GIC_NR)
546 		BUG();
547 
548 	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
549 	cpu_base = gic_data_cpu_base(&gic_data[gic_nr]);
550 
551 	if (!dist_base || !cpu_base)
552 		return;
553 
554 	ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable);
555 	for (i = 0; i < DIV_ROUND_UP(32, 32); i++)
556 		writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4);
557 
558 	ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf);
559 	for (i = 0; i < DIV_ROUND_UP(32, 16); i++)
560 		writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4);
561 
562 	for (i = 0; i < DIV_ROUND_UP(32, 4); i++)
563 		writel_relaxed(GICD_INT_DEF_PRI_X4,
564 					dist_base + GIC_DIST_PRI + i * 4);
565 
566 	writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK);
567 	gic_cpu_if_up();
568 }
569 
570 static int gic_notifier(struct notifier_block *self, unsigned long cmd,	void *v)
571 {
572 	int i;
573 
574 	for (i = 0; i < MAX_GIC_NR; i++) {
575 #ifdef CONFIG_GIC_NON_BANKED
576 		/* Skip over unused GICs */
577 		if (!gic_data[i].get_base)
578 			continue;
579 #endif
580 		switch (cmd) {
581 		case CPU_PM_ENTER:
582 			gic_cpu_save(i);
583 			break;
584 		case CPU_PM_ENTER_FAILED:
585 		case CPU_PM_EXIT:
586 			gic_cpu_restore(i);
587 			break;
588 		case CPU_CLUSTER_PM_ENTER:
589 			gic_dist_save(i);
590 			break;
591 		case CPU_CLUSTER_PM_ENTER_FAILED:
592 		case CPU_CLUSTER_PM_EXIT:
593 			gic_dist_restore(i);
594 			break;
595 		}
596 	}
597 
598 	return NOTIFY_OK;
599 }
600 
601 static struct notifier_block gic_notifier_block = {
602 	.notifier_call = gic_notifier,
603 };
604 
605 static void __init gic_pm_init(struct gic_chip_data *gic)
606 {
607 	gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4,
608 		sizeof(u32));
609 	BUG_ON(!gic->saved_ppi_enable);
610 
611 	gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4,
612 		sizeof(u32));
613 	BUG_ON(!gic->saved_ppi_conf);
614 
615 	if (gic == &gic_data[0])
616 		cpu_pm_register_notifier(&gic_notifier_block);
617 }
618 #else
619 static void __init gic_pm_init(struct gic_chip_data *gic)
620 {
621 }
622 #endif
623 
624 #ifdef CONFIG_SMP
625 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq)
626 {
627 	int cpu;
628 	unsigned long flags, map = 0;
629 
630 	raw_spin_lock_irqsave(&irq_controller_lock, flags);
631 
632 	/* Convert our logical CPU mask into a physical one. */
633 	for_each_cpu(cpu, mask)
634 		map |= gic_cpu_map[cpu];
635 
636 	/*
637 	 * Ensure that stores to Normal memory are visible to the
638 	 * other CPUs before they observe us issuing the IPI.
639 	 */
640 	dmb(ishst);
641 
642 	/* this always happens on GIC0 */
643 	writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
644 
645 	raw_spin_unlock_irqrestore(&irq_controller_lock, flags);
646 }
647 #endif
648 
649 #ifdef CONFIG_BL_SWITCHER
650 /*
651  * gic_send_sgi - send a SGI directly to given CPU interface number
652  *
653  * cpu_id: the ID for the destination CPU interface
654  * irq: the IPI number to send a SGI for
655  */
656 void gic_send_sgi(unsigned int cpu_id, unsigned int irq)
657 {
658 	BUG_ON(cpu_id >= NR_GIC_CPU_IF);
659 	cpu_id = 1 << cpu_id;
660 	/* this always happens on GIC0 */
661 	writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT);
662 }
663 
664 /*
665  * gic_get_cpu_id - get the CPU interface ID for the specified CPU
666  *
667  * @cpu: the logical CPU number to get the GIC ID for.
668  *
669  * Return the CPU interface ID for the given logical CPU number,
670  * or -1 if the CPU number is too large or the interface ID is
671  * unknown (more than one bit set).
672  */
673 int gic_get_cpu_id(unsigned int cpu)
674 {
675 	unsigned int cpu_bit;
676 
677 	if (cpu >= NR_GIC_CPU_IF)
678 		return -1;
679 	cpu_bit = gic_cpu_map[cpu];
680 	if (cpu_bit & (cpu_bit - 1))
681 		return -1;
682 	return __ffs(cpu_bit);
683 }
684 
685 /*
686  * gic_migrate_target - migrate IRQs to another CPU interface
687  *
688  * @new_cpu_id: the CPU target ID to migrate IRQs to
689  *
690  * Migrate all peripheral interrupts with a target matching the current CPU
691  * to the interface corresponding to @new_cpu_id.  The CPU interface mapping
692  * is also updated.  Targets to other CPU interfaces are unchanged.
693  * This must be called with IRQs locally disabled.
694  */
695 void gic_migrate_target(unsigned int new_cpu_id)
696 {
697 	unsigned int cur_cpu_id, gic_irqs, gic_nr = 0;
698 	void __iomem *dist_base;
699 	int i, ror_val, cpu = smp_processor_id();
700 	u32 val, cur_target_mask, active_mask;
701 
702 	if (gic_nr >= MAX_GIC_NR)
703 		BUG();
704 
705 	dist_base = gic_data_dist_base(&gic_data[gic_nr]);
706 	if (!dist_base)
707 		return;
708 	gic_irqs = gic_data[gic_nr].gic_irqs;
709 
710 	cur_cpu_id = __ffs(gic_cpu_map[cpu]);
711 	cur_target_mask = 0x01010101 << cur_cpu_id;
712 	ror_val = (cur_cpu_id - new_cpu_id) & 31;
713 
714 	raw_spin_lock(&irq_controller_lock);
715 
716 	/* Update the target interface for this logical CPU */
717 	gic_cpu_map[cpu] = 1 << new_cpu_id;
718 
719 	/*
720 	 * Find all the peripheral interrupts targetting the current
721 	 * CPU interface and migrate them to the new CPU interface.
722 	 * We skip DIST_TARGET 0 to 7 as they are read-only.
723 	 */
724 	for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) {
725 		val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4);
726 		active_mask = val & cur_target_mask;
727 		if (active_mask) {
728 			val &= ~active_mask;
729 			val |= ror32(active_mask, ror_val);
730 			writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4);
731 		}
732 	}
733 
734 	raw_spin_unlock(&irq_controller_lock);
735 
736 	/*
737 	 * Now let's migrate and clear any potential SGIs that might be
738 	 * pending for us (cur_cpu_id).  Since GIC_DIST_SGI_PENDING_SET
739 	 * is a banked register, we can only forward the SGI using
740 	 * GIC_DIST_SOFTINT.  The original SGI source is lost but Linux
741 	 * doesn't use that information anyway.
742 	 *
743 	 * For the same reason we do not adjust SGI source information
744 	 * for previously sent SGIs by us to other CPUs either.
745 	 */
746 	for (i = 0; i < 16; i += 4) {
747 		int j;
748 		val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i);
749 		if (!val)
750 			continue;
751 		writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i);
752 		for (j = i; j < i + 4; j++) {
753 			if (val & 0xff)
754 				writel_relaxed((1 << (new_cpu_id + 16)) | j,
755 						dist_base + GIC_DIST_SOFTINT);
756 			val >>= 8;
757 		}
758 	}
759 }
760 
761 /*
762  * gic_get_sgir_physaddr - get the physical address for the SGI register
763  *
764  * REturn the physical address of the SGI register to be used
765  * by some early assembly code when the kernel is not yet available.
766  */
767 static unsigned long gic_dist_physaddr;
768 
769 unsigned long gic_get_sgir_physaddr(void)
770 {
771 	if (!gic_dist_physaddr)
772 		return 0;
773 	return gic_dist_physaddr + GIC_DIST_SOFTINT;
774 }
775 
776 void __init gic_init_physaddr(struct device_node *node)
777 {
778 	struct resource res;
779 	if (of_address_to_resource(node, 0, &res) == 0) {
780 		gic_dist_physaddr = res.start;
781 		pr_info("GIC physical location is %#lx\n", gic_dist_physaddr);
782 	}
783 }
784 
785 #else
786 #define gic_init_physaddr(node)  do { } while (0)
787 #endif
788 
789 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq,
790 				irq_hw_number_t hw)
791 {
792 	if (hw < 32) {
793 		irq_set_percpu_devid(irq);
794 		irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
795 				    handle_percpu_devid_irq, NULL, NULL);
796 		set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN);
797 	} else {
798 		irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data,
799 				    handle_fasteoi_irq, NULL, NULL);
800 		set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
801 
802 		gic_routable_irq_domain_ops->map(d, irq, hw);
803 	}
804 	return 0;
805 }
806 
807 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq)
808 {
809 	gic_routable_irq_domain_ops->unmap(d, irq);
810 }
811 
812 static int gic_irq_domain_xlate(struct irq_domain *d,
813 				struct device_node *controller,
814 				const u32 *intspec, unsigned int intsize,
815 				unsigned long *out_hwirq, unsigned int *out_type)
816 {
817 	unsigned long ret = 0;
818 
819 	if (d->of_node != controller)
820 		return -EINVAL;
821 	if (intsize < 3)
822 		return -EINVAL;
823 
824 	/* Get the interrupt number and add 16 to skip over SGIs */
825 	*out_hwirq = intspec[1] + 16;
826 
827 	/* For SPIs, we need to add 16 more to get the GIC irq ID number */
828 	if (!intspec[0]) {
829 		ret = gic_routable_irq_domain_ops->xlate(d, controller,
830 							 intspec,
831 							 intsize,
832 							 out_hwirq,
833 							 out_type);
834 
835 		if (IS_ERR_VALUE(ret))
836 			return ret;
837 	}
838 
839 	*out_type = intspec[2] & IRQ_TYPE_SENSE_MASK;
840 
841 	return ret;
842 }
843 
844 #ifdef CONFIG_SMP
845 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action,
846 			      void *hcpu)
847 {
848 	if (action == CPU_STARTING || action == CPU_STARTING_FROZEN)
849 		gic_cpu_init(&gic_data[0]);
850 	return NOTIFY_OK;
851 }
852 
853 /*
854  * Notifier for enabling the GIC CPU interface. Set an arbitrarily high
855  * priority because the GIC needs to be up before the ARM generic timers.
856  */
857 static struct notifier_block gic_cpu_notifier = {
858 	.notifier_call = gic_secondary_init,
859 	.priority = 100,
860 };
861 #endif
862 
863 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
864 				unsigned int nr_irqs, void *arg)
865 {
866 	int i, ret;
867 	irq_hw_number_t hwirq;
868 	unsigned int type = IRQ_TYPE_NONE;
869 	struct of_phandle_args *irq_data = arg;
870 
871 	ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args,
872 				   irq_data->args_count, &hwirq, &type);
873 	if (ret)
874 		return ret;
875 
876 	for (i = 0; i < nr_irqs; i++)
877 		gic_irq_domain_map(domain, virq + i, hwirq + i);
878 
879 	return 0;
880 }
881 
882 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = {
883 	.xlate = gic_irq_domain_xlate,
884 	.alloc = gic_irq_domain_alloc,
885 	.free = irq_domain_free_irqs_top,
886 };
887 
888 static const struct irq_domain_ops gic_irq_domain_ops = {
889 	.map = gic_irq_domain_map,
890 	.unmap = gic_irq_domain_unmap,
891 	.xlate = gic_irq_domain_xlate,
892 };
893 
894 /* Default functions for routable irq domain */
895 static int gic_routable_irq_domain_map(struct irq_domain *d, unsigned int irq,
896 			      irq_hw_number_t hw)
897 {
898 	return 0;
899 }
900 
901 static void gic_routable_irq_domain_unmap(struct irq_domain *d,
902 					  unsigned int irq)
903 {
904 }
905 
906 static int gic_routable_irq_domain_xlate(struct irq_domain *d,
907 				struct device_node *controller,
908 				const u32 *intspec, unsigned int intsize,
909 				unsigned long *out_hwirq,
910 				unsigned int *out_type)
911 {
912 	*out_hwirq += 16;
913 	return 0;
914 }
915 
916 static const struct irq_domain_ops gic_default_routable_irq_domain_ops = {
917 	.map = gic_routable_irq_domain_map,
918 	.unmap = gic_routable_irq_domain_unmap,
919 	.xlate = gic_routable_irq_domain_xlate,
920 };
921 
922 const struct irq_domain_ops *gic_routable_irq_domain_ops =
923 					&gic_default_routable_irq_domain_ops;
924 
925 void __init gic_init_bases(unsigned int gic_nr, int irq_start,
926 			   void __iomem *dist_base, void __iomem *cpu_base,
927 			   u32 percpu_offset, struct device_node *node)
928 {
929 	irq_hw_number_t hwirq_base;
930 	struct gic_chip_data *gic;
931 	int gic_irqs, irq_base, i;
932 	int nr_routable_irqs;
933 
934 	BUG_ON(gic_nr >= MAX_GIC_NR);
935 
936 	gic = &gic_data[gic_nr];
937 #ifdef CONFIG_GIC_NON_BANKED
938 	if (percpu_offset) { /* Frankein-GIC without banked registers... */
939 		unsigned int cpu;
940 
941 		gic->dist_base.percpu_base = alloc_percpu(void __iomem *);
942 		gic->cpu_base.percpu_base = alloc_percpu(void __iomem *);
943 		if (WARN_ON(!gic->dist_base.percpu_base ||
944 			    !gic->cpu_base.percpu_base)) {
945 			free_percpu(gic->dist_base.percpu_base);
946 			free_percpu(gic->cpu_base.percpu_base);
947 			return;
948 		}
949 
950 		for_each_possible_cpu(cpu) {
951 			u32 mpidr = cpu_logical_map(cpu);
952 			u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
953 			unsigned long offset = percpu_offset * core_id;
954 			*per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset;
955 			*per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset;
956 		}
957 
958 		gic_set_base_accessor(gic, gic_get_percpu_base);
959 	} else
960 #endif
961 	{			/* Normal, sane GIC... */
962 		WARN(percpu_offset,
963 		     "GIC_NON_BANKED not enabled, ignoring %08x offset!",
964 		     percpu_offset);
965 		gic->dist_base.common_base = dist_base;
966 		gic->cpu_base.common_base = cpu_base;
967 		gic_set_base_accessor(gic, gic_get_common_base);
968 	}
969 
970 	/*
971 	 * Initialize the CPU interface map to all CPUs.
972 	 * It will be refined as each CPU probes its ID.
973 	 */
974 	for (i = 0; i < NR_GIC_CPU_IF; i++)
975 		gic_cpu_map[i] = 0xff;
976 
977 	/*
978 	 * Find out how many interrupts are supported.
979 	 * The GIC only supports up to 1020 interrupt sources.
980 	 */
981 	gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f;
982 	gic_irqs = (gic_irqs + 1) * 32;
983 	if (gic_irqs > 1020)
984 		gic_irqs = 1020;
985 	gic->gic_irqs = gic_irqs;
986 
987 	if (node) {		/* DT case */
988 		const struct irq_domain_ops *ops = &gic_irq_domain_hierarchy_ops;
989 
990 		if (!of_property_read_u32(node, "arm,routable-irqs",
991 					  &nr_routable_irqs)) {
992 			ops = &gic_irq_domain_ops;
993 			gic_irqs = nr_routable_irqs;
994 		}
995 
996 		gic->domain = irq_domain_add_linear(node, gic_irqs, ops, gic);
997 	} else {		/* Non-DT case */
998 		/*
999 		 * For primary GICs, skip over SGIs.
1000 		 * For secondary GICs, skip over PPIs, too.
1001 		 */
1002 		if (gic_nr == 0 && (irq_start & 31) > 0) {
1003 			hwirq_base = 16;
1004 			if (irq_start != -1)
1005 				irq_start = (irq_start & ~31) + 16;
1006 		} else {
1007 			hwirq_base = 32;
1008 		}
1009 
1010 		gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */
1011 
1012 		irq_base = irq_alloc_descs(irq_start, 16, gic_irqs,
1013 					   numa_node_id());
1014 		if (IS_ERR_VALUE(irq_base)) {
1015 			WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n",
1016 			     irq_start);
1017 			irq_base = irq_start;
1018 		}
1019 
1020 		gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base,
1021 					hwirq_base, &gic_irq_domain_ops, gic);
1022 	}
1023 
1024 	if (WARN_ON(!gic->domain))
1025 		return;
1026 
1027 	if (gic_nr == 0) {
1028 #ifdef CONFIG_SMP
1029 		set_smp_cross_call(gic_raise_softirq);
1030 		register_cpu_notifier(&gic_cpu_notifier);
1031 #endif
1032 		set_handle_irq(gic_handle_irq);
1033 	}
1034 
1035 	gic_chip.flags |= gic_arch_extn.flags;
1036 	gic_dist_init(gic);
1037 	gic_cpu_init(gic);
1038 	gic_pm_init(gic);
1039 }
1040 
1041 #ifdef CONFIG_OF
1042 static int gic_cnt __initdata;
1043 
1044 static int __init
1045 gic_of_init(struct device_node *node, struct device_node *parent)
1046 {
1047 	void __iomem *cpu_base;
1048 	void __iomem *dist_base;
1049 	u32 percpu_offset;
1050 	int irq;
1051 
1052 	if (WARN_ON(!node))
1053 		return -ENODEV;
1054 
1055 	dist_base = of_iomap(node, 0);
1056 	WARN(!dist_base, "unable to map gic dist registers\n");
1057 
1058 	cpu_base = of_iomap(node, 1);
1059 	WARN(!cpu_base, "unable to map gic cpu registers\n");
1060 
1061 	if (of_property_read_u32(node, "cpu-offset", &percpu_offset))
1062 		percpu_offset = 0;
1063 
1064 	gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node);
1065 	if (!gic_cnt)
1066 		gic_init_physaddr(node);
1067 
1068 	if (parent) {
1069 		irq = irq_of_parse_and_map(node, 0);
1070 		gic_cascade_irq(gic_cnt, irq);
1071 	}
1072 
1073 	if (IS_ENABLED(CONFIG_ARM_GIC_V2M))
1074 		gicv2m_of_init(node, gic_data[gic_cnt].domain);
1075 
1076 	gic_cnt++;
1077 	return 0;
1078 }
1079 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1080 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1081 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1082 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1083 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1084 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1085 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init);
1086 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init);
1087 
1088 #endif
1089