1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 4 * 5 * Interrupt architecture for the GIC: 6 * 7 * o There is one Interrupt Distributor, which receives interrupts 8 * from system devices and sends them to the Interrupt Controllers. 9 * 10 * o There is one CPU Interface per CPU, which sends interrupts sent 11 * by the Distributor, and interrupts generated locally, to the 12 * associated CPU. The base address of the CPU interface is usually 13 * aliased so that the same address points to different chips depending 14 * on the CPU it is accessed from. 15 * 16 * Note that IRQs 0-31 are special - they are local to each CPU. 17 * As such, the enable set/clear, pending set/clear and active bit 18 * registers are banked per-cpu for these sources. 19 */ 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/err.h> 23 #include <linux/module.h> 24 #include <linux/list.h> 25 #include <linux/smp.h> 26 #include <linux/cpu.h> 27 #include <linux/cpu_pm.h> 28 #include <linux/cpumask.h> 29 #include <linux/io.h> 30 #include <linux/of.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/acpi.h> 34 #include <linux/irqdomain.h> 35 #include <linux/interrupt.h> 36 #include <linux/percpu.h> 37 #include <linux/slab.h> 38 #include <linux/irqchip.h> 39 #include <linux/irqchip/chained_irq.h> 40 #include <linux/irqchip/arm-gic.h> 41 42 #include <asm/cputype.h> 43 #include <asm/irq.h> 44 #include <asm/exception.h> 45 #include <asm/smp_plat.h> 46 #include <asm/virt.h> 47 48 #include "irq-gic-common.h" 49 50 #ifdef CONFIG_ARM64 51 #include <asm/cpufeature.h> 52 53 static void gic_check_cpu_features(void) 54 { 55 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), 56 TAINT_CPU_OUT_OF_SPEC, 57 "GICv3 system registers enabled, broken firmware!\n"); 58 } 59 #else 60 #define gic_check_cpu_features() do { } while(0) 61 #endif 62 63 union gic_base { 64 void __iomem *common_base; 65 void __percpu * __iomem *percpu_base; 66 }; 67 68 struct gic_chip_data { 69 struct irq_chip chip; 70 union gic_base dist_base; 71 union gic_base cpu_base; 72 void __iomem *raw_dist_base; 73 void __iomem *raw_cpu_base; 74 u32 percpu_offset; 75 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 77 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 78 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 79 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 80 u32 __percpu *saved_ppi_enable; 81 u32 __percpu *saved_ppi_active; 82 u32 __percpu *saved_ppi_conf; 83 #endif 84 struct irq_domain *domain; 85 unsigned int gic_irqs; 86 }; 87 88 #ifdef CONFIG_BL_SWITCHER 89 90 static DEFINE_RAW_SPINLOCK(cpu_map_lock); 91 92 #define gic_lock_irqsave(f) \ 93 raw_spin_lock_irqsave(&cpu_map_lock, (f)) 94 #define gic_unlock_irqrestore(f) \ 95 raw_spin_unlock_irqrestore(&cpu_map_lock, (f)) 96 97 #define gic_lock() raw_spin_lock(&cpu_map_lock) 98 #define gic_unlock() raw_spin_unlock(&cpu_map_lock) 99 100 #else 101 102 #define gic_lock_irqsave(f) do { (void)(f); } while(0) 103 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0) 104 105 #define gic_lock() do { } while(0) 106 #define gic_unlock() do { } while(0) 107 108 #endif 109 110 /* 111 * The GIC mapping of CPU interfaces does not necessarily match 112 * the logical CPU numbering. Let's use a mapping as returned 113 * by the GIC itself. 114 */ 115 #define NR_GIC_CPU_IF 8 116 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 117 118 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 119 120 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; 121 122 static struct gic_kvm_info gic_v2_kvm_info; 123 124 static DEFINE_PER_CPU(u32, sgi_intid); 125 126 #ifdef CONFIG_GIC_NON_BANKED 127 static DEFINE_STATIC_KEY_FALSE(frankengic_key); 128 129 static void enable_frankengic(void) 130 { 131 static_branch_enable(&frankengic_key); 132 } 133 134 static inline void __iomem *__get_base(union gic_base *base) 135 { 136 if (static_branch_unlikely(&frankengic_key)) 137 return raw_cpu_read(*base->percpu_base); 138 139 return base->common_base; 140 } 141 142 #define gic_data_dist_base(d) __get_base(&(d)->dist_base) 143 #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base) 144 #else 145 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 146 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 147 #define enable_frankengic() do { } while(0) 148 #endif 149 150 static inline void __iomem *gic_dist_base(struct irq_data *d) 151 { 152 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 153 return gic_data_dist_base(gic_data); 154 } 155 156 static inline void __iomem *gic_cpu_base(struct irq_data *d) 157 { 158 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 159 return gic_data_cpu_base(gic_data); 160 } 161 162 static inline unsigned int gic_irq(struct irq_data *d) 163 { 164 return d->hwirq; 165 } 166 167 static inline bool cascading_gic_irq(struct irq_data *d) 168 { 169 void *data = irq_data_get_irq_handler_data(d); 170 171 /* 172 * If handler_data is set, this is a cascading interrupt, and 173 * it cannot possibly be forwarded. 174 */ 175 return data != NULL; 176 } 177 178 /* 179 * Routines to acknowledge, disable and enable interrupts 180 */ 181 static void gic_poke_irq(struct irq_data *d, u32 offset) 182 { 183 u32 mask = 1 << (gic_irq(d) % 32); 184 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 185 } 186 187 static int gic_peek_irq(struct irq_data *d, u32 offset) 188 { 189 u32 mask = 1 << (gic_irq(d) % 32); 190 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 191 } 192 193 static void gic_mask_irq(struct irq_data *d) 194 { 195 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 196 } 197 198 static void gic_eoimode1_mask_irq(struct irq_data *d) 199 { 200 gic_mask_irq(d); 201 /* 202 * When masking a forwarded interrupt, make sure it is 203 * deactivated as well. 204 * 205 * This ensures that an interrupt that is getting 206 * disabled/masked will not get "stuck", because there is 207 * noone to deactivate it (guest is being terminated). 208 */ 209 if (irqd_is_forwarded_to_vcpu(d)) 210 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); 211 } 212 213 static void gic_unmask_irq(struct irq_data *d) 214 { 215 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 216 } 217 218 static void gic_eoi_irq(struct irq_data *d) 219 { 220 u32 hwirq = gic_irq(d); 221 222 if (hwirq < 16) 223 hwirq = this_cpu_read(sgi_intid); 224 225 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI); 226 } 227 228 static void gic_eoimode1_eoi_irq(struct irq_data *d) 229 { 230 u32 hwirq = gic_irq(d); 231 232 /* Do not deactivate an IRQ forwarded to a vcpu. */ 233 if (irqd_is_forwarded_to_vcpu(d)) 234 return; 235 236 if (hwirq < 16) 237 hwirq = this_cpu_read(sgi_intid); 238 239 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE); 240 } 241 242 static int gic_irq_set_irqchip_state(struct irq_data *d, 243 enum irqchip_irq_state which, bool val) 244 { 245 u32 reg; 246 247 switch (which) { 248 case IRQCHIP_STATE_PENDING: 249 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 250 break; 251 252 case IRQCHIP_STATE_ACTIVE: 253 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 254 break; 255 256 case IRQCHIP_STATE_MASKED: 257 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 258 break; 259 260 default: 261 return -EINVAL; 262 } 263 264 gic_poke_irq(d, reg); 265 return 0; 266 } 267 268 static int gic_irq_get_irqchip_state(struct irq_data *d, 269 enum irqchip_irq_state which, bool *val) 270 { 271 switch (which) { 272 case IRQCHIP_STATE_PENDING: 273 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 274 break; 275 276 case IRQCHIP_STATE_ACTIVE: 277 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 278 break; 279 280 case IRQCHIP_STATE_MASKED: 281 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 282 break; 283 284 default: 285 return -EINVAL; 286 } 287 288 return 0; 289 } 290 291 static int gic_set_type(struct irq_data *d, unsigned int type) 292 { 293 void __iomem *base = gic_dist_base(d); 294 unsigned int gicirq = gic_irq(d); 295 int ret; 296 297 /* Interrupt configuration for SGIs can't be changed */ 298 if (gicirq < 16) 299 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; 300 301 /* SPIs have restrictions on the supported types */ 302 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 303 type != IRQ_TYPE_EDGE_RISING) 304 return -EINVAL; 305 306 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL); 307 if (ret && gicirq < 32) { 308 /* Misconfigured PPIs are usually not fatal */ 309 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); 310 ret = 0; 311 } 312 313 return ret; 314 } 315 316 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 317 { 318 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ 319 if (cascading_gic_irq(d) || gic_irq(d) < 16) 320 return -EINVAL; 321 322 if (vcpu) 323 irqd_set_forwarded_to_vcpu(d); 324 else 325 irqd_clr_forwarded_to_vcpu(d); 326 return 0; 327 } 328 329 static int gic_retrigger(struct irq_data *data) 330 { 331 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); 332 } 333 334 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 335 { 336 u32 irqstat, irqnr; 337 struct gic_chip_data *gic = &gic_data[0]; 338 void __iomem *cpu_base = gic_data_cpu_base(gic); 339 340 do { 341 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 342 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 343 344 if (unlikely(irqnr >= 1020)) 345 break; 346 347 if (static_branch_likely(&supports_deactivate_key)) 348 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 349 isb(); 350 351 /* 352 * Ensure any shared data written by the CPU sending the IPI 353 * is read after we've read the ACK register on the GIC. 354 * 355 * Pairs with the write barrier in gic_ipi_send_mask 356 */ 357 if (irqnr <= 15) { 358 smp_rmb(); 359 360 /* 361 * The GIC encodes the source CPU in GICC_IAR, 362 * leading to the deactivation to fail if not 363 * written back as is to GICC_EOI. Stash the INTID 364 * away for gic_eoi_irq() to write back. This only 365 * works because we don't nest SGIs... 366 */ 367 this_cpu_write(sgi_intid, irqstat); 368 } 369 370 handle_domain_irq(gic->domain, irqnr, regs); 371 } while (1); 372 } 373 374 static void gic_handle_cascade_irq(struct irq_desc *desc) 375 { 376 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); 377 struct irq_chip *chip = irq_desc_get_chip(desc); 378 unsigned int cascade_irq, gic_irq; 379 unsigned long status; 380 381 chained_irq_enter(chip, desc); 382 383 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 384 385 gic_irq = (status & GICC_IAR_INT_ID_MASK); 386 if (gic_irq == GICC_INT_SPURIOUS) 387 goto out; 388 389 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 390 if (unlikely(gic_irq < 32 || gic_irq > 1020)) { 391 handle_bad_irq(desc); 392 } else { 393 isb(); 394 generic_handle_irq(cascade_irq); 395 } 396 397 out: 398 chained_irq_exit(chip, desc); 399 } 400 401 static const struct irq_chip gic_chip = { 402 .irq_mask = gic_mask_irq, 403 .irq_unmask = gic_unmask_irq, 404 .irq_eoi = gic_eoi_irq, 405 .irq_set_type = gic_set_type, 406 .irq_retrigger = gic_retrigger, 407 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 408 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 409 .flags = IRQCHIP_SET_TYPE_MASKED | 410 IRQCHIP_SKIP_SET_WAKE | 411 IRQCHIP_MASK_ON_SUSPEND, 412 }; 413 414 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 415 { 416 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 417 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, 418 &gic_data[gic_nr]); 419 } 420 421 static u8 gic_get_cpumask(struct gic_chip_data *gic) 422 { 423 void __iomem *base = gic_data_dist_base(gic); 424 u32 mask, i; 425 426 for (i = mask = 0; i < 32; i += 4) { 427 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 428 mask |= mask >> 16; 429 mask |= mask >> 8; 430 if (mask) 431 break; 432 } 433 434 if (!mask && num_possible_cpus() > 1) 435 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 436 437 return mask; 438 } 439 440 static bool gic_check_gicv2(void __iomem *base) 441 { 442 u32 val = readl_relaxed(base + GIC_CPU_IDENT); 443 return (val & 0xff0fff) == 0x02043B; 444 } 445 446 static void gic_cpu_if_up(struct gic_chip_data *gic) 447 { 448 void __iomem *cpu_base = gic_data_cpu_base(gic); 449 u32 bypass = 0; 450 u32 mode = 0; 451 int i; 452 453 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) 454 mode = GIC_CPU_CTRL_EOImodeNS; 455 456 if (gic_check_gicv2(cpu_base)) 457 for (i = 0; i < 4; i++) 458 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4); 459 460 /* 461 * Preserve bypass disable bits to be written back later 462 */ 463 bypass = readl(cpu_base + GIC_CPU_CTRL); 464 bypass &= GICC_DIS_BYPASS_MASK; 465 466 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 467 } 468 469 470 static void gic_dist_init(struct gic_chip_data *gic) 471 { 472 unsigned int i; 473 u32 cpumask; 474 unsigned int gic_irqs = gic->gic_irqs; 475 void __iomem *base = gic_data_dist_base(gic); 476 477 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 478 479 /* 480 * Set all global interrupts to this CPU only. 481 */ 482 cpumask = gic_get_cpumask(gic); 483 cpumask |= cpumask << 8; 484 cpumask |= cpumask << 16; 485 for (i = 32; i < gic_irqs; i += 4) 486 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 487 488 gic_dist_config(base, gic_irqs, NULL); 489 490 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 491 } 492 493 static int gic_cpu_init(struct gic_chip_data *gic) 494 { 495 void __iomem *dist_base = gic_data_dist_base(gic); 496 void __iomem *base = gic_data_cpu_base(gic); 497 unsigned int cpu_mask, cpu = smp_processor_id(); 498 int i; 499 500 /* 501 * Setting up the CPU map is only relevant for the primary GIC 502 * because any nested/secondary GICs do not directly interface 503 * with the CPU(s). 504 */ 505 if (gic == &gic_data[0]) { 506 /* 507 * Get what the GIC says our CPU mask is. 508 */ 509 if (WARN_ON(cpu >= NR_GIC_CPU_IF)) 510 return -EINVAL; 511 512 gic_check_cpu_features(); 513 cpu_mask = gic_get_cpumask(gic); 514 gic_cpu_map[cpu] = cpu_mask; 515 516 /* 517 * Clear our mask from the other map entries in case they're 518 * still undefined. 519 */ 520 for (i = 0; i < NR_GIC_CPU_IF; i++) 521 if (i != cpu) 522 gic_cpu_map[i] &= ~cpu_mask; 523 } 524 525 gic_cpu_config(dist_base, 32, NULL); 526 527 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 528 gic_cpu_if_up(gic); 529 530 return 0; 531 } 532 533 int gic_cpu_if_down(unsigned int gic_nr) 534 { 535 void __iomem *cpu_base; 536 u32 val = 0; 537 538 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) 539 return -EINVAL; 540 541 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 542 val = readl(cpu_base + GIC_CPU_CTRL); 543 val &= ~GICC_ENABLE; 544 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 545 546 return 0; 547 } 548 549 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 550 /* 551 * Saves the GIC distributor registers during suspend or idle. Must be called 552 * with interrupts disabled but before powering down the GIC. After calling 553 * this function, no interrupts will be delivered by the GIC, and another 554 * platform-specific wakeup source must be enabled. 555 */ 556 void gic_dist_save(struct gic_chip_data *gic) 557 { 558 unsigned int gic_irqs; 559 void __iomem *dist_base; 560 int i; 561 562 if (WARN_ON(!gic)) 563 return; 564 565 gic_irqs = gic->gic_irqs; 566 dist_base = gic_data_dist_base(gic); 567 568 if (!dist_base) 569 return; 570 571 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 572 gic->saved_spi_conf[i] = 573 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 574 575 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 576 gic->saved_spi_target[i] = 577 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 578 579 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 580 gic->saved_spi_enable[i] = 581 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 582 583 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 584 gic->saved_spi_active[i] = 585 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 586 } 587 588 /* 589 * Restores the GIC distributor registers during resume or when coming out of 590 * idle. Must be called before enabling interrupts. If a level interrupt 591 * that occurred while the GIC was suspended is still present, it will be 592 * handled normally, but any edge interrupts that occurred will not be seen by 593 * the GIC and need to be handled by the platform-specific wakeup source. 594 */ 595 void gic_dist_restore(struct gic_chip_data *gic) 596 { 597 unsigned int gic_irqs; 598 unsigned int i; 599 void __iomem *dist_base; 600 601 if (WARN_ON(!gic)) 602 return; 603 604 gic_irqs = gic->gic_irqs; 605 dist_base = gic_data_dist_base(gic); 606 607 if (!dist_base) 608 return; 609 610 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 611 612 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 613 writel_relaxed(gic->saved_spi_conf[i], 614 dist_base + GIC_DIST_CONFIG + i * 4); 615 616 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 617 writel_relaxed(GICD_INT_DEF_PRI_X4, 618 dist_base + GIC_DIST_PRI + i * 4); 619 620 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 621 writel_relaxed(gic->saved_spi_target[i], 622 dist_base + GIC_DIST_TARGET + i * 4); 623 624 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 625 writel_relaxed(GICD_INT_EN_CLR_X32, 626 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 627 writel_relaxed(gic->saved_spi_enable[i], 628 dist_base + GIC_DIST_ENABLE_SET + i * 4); 629 } 630 631 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 632 writel_relaxed(GICD_INT_EN_CLR_X32, 633 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 634 writel_relaxed(gic->saved_spi_active[i], 635 dist_base + GIC_DIST_ACTIVE_SET + i * 4); 636 } 637 638 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 639 } 640 641 void gic_cpu_save(struct gic_chip_data *gic) 642 { 643 int i; 644 u32 *ptr; 645 void __iomem *dist_base; 646 void __iomem *cpu_base; 647 648 if (WARN_ON(!gic)) 649 return; 650 651 dist_base = gic_data_dist_base(gic); 652 cpu_base = gic_data_cpu_base(gic); 653 654 if (!dist_base || !cpu_base) 655 return; 656 657 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 658 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 659 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 660 661 ptr = raw_cpu_ptr(gic->saved_ppi_active); 662 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 663 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 664 665 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 666 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 667 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 668 669 } 670 671 void gic_cpu_restore(struct gic_chip_data *gic) 672 { 673 int i; 674 u32 *ptr; 675 void __iomem *dist_base; 676 void __iomem *cpu_base; 677 678 if (WARN_ON(!gic)) 679 return; 680 681 dist_base = gic_data_dist_base(gic); 682 cpu_base = gic_data_cpu_base(gic); 683 684 if (!dist_base || !cpu_base) 685 return; 686 687 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 688 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 689 writel_relaxed(GICD_INT_EN_CLR_X32, 690 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 691 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 692 } 693 694 ptr = raw_cpu_ptr(gic->saved_ppi_active); 695 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 696 writel_relaxed(GICD_INT_EN_CLR_X32, 697 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 698 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); 699 } 700 701 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 702 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 703 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 704 705 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 706 writel_relaxed(GICD_INT_DEF_PRI_X4, 707 dist_base + GIC_DIST_PRI + i * 4); 708 709 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 710 gic_cpu_if_up(gic); 711 } 712 713 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 714 { 715 int i; 716 717 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { 718 switch (cmd) { 719 case CPU_PM_ENTER: 720 gic_cpu_save(&gic_data[i]); 721 break; 722 case CPU_PM_ENTER_FAILED: 723 case CPU_PM_EXIT: 724 gic_cpu_restore(&gic_data[i]); 725 break; 726 case CPU_CLUSTER_PM_ENTER: 727 gic_dist_save(&gic_data[i]); 728 break; 729 case CPU_CLUSTER_PM_ENTER_FAILED: 730 case CPU_CLUSTER_PM_EXIT: 731 gic_dist_restore(&gic_data[i]); 732 break; 733 } 734 } 735 736 return NOTIFY_OK; 737 } 738 739 static struct notifier_block gic_notifier_block = { 740 .notifier_call = gic_notifier, 741 }; 742 743 static int gic_pm_init(struct gic_chip_data *gic) 744 { 745 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 746 sizeof(u32)); 747 if (WARN_ON(!gic->saved_ppi_enable)) 748 return -ENOMEM; 749 750 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 751 sizeof(u32)); 752 if (WARN_ON(!gic->saved_ppi_active)) 753 goto free_ppi_enable; 754 755 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 756 sizeof(u32)); 757 if (WARN_ON(!gic->saved_ppi_conf)) 758 goto free_ppi_active; 759 760 if (gic == &gic_data[0]) 761 cpu_pm_register_notifier(&gic_notifier_block); 762 763 return 0; 764 765 free_ppi_active: 766 free_percpu(gic->saved_ppi_active); 767 free_ppi_enable: 768 free_percpu(gic->saved_ppi_enable); 769 770 return -ENOMEM; 771 } 772 #else 773 static int gic_pm_init(struct gic_chip_data *gic) 774 { 775 return 0; 776 } 777 #endif 778 779 #ifdef CONFIG_SMP 780 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 781 bool force) 782 { 783 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d); 784 unsigned int cpu; 785 786 if (!force) 787 cpu = cpumask_any_and(mask_val, cpu_online_mask); 788 else 789 cpu = cpumask_first(mask_val); 790 791 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 792 return -EINVAL; 793 794 writeb_relaxed(gic_cpu_map[cpu], reg); 795 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 796 797 return IRQ_SET_MASK_OK_DONE; 798 } 799 800 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) 801 { 802 int cpu; 803 unsigned long flags, map = 0; 804 805 if (unlikely(nr_cpu_ids == 1)) { 806 /* Only one CPU? let's do a self-IPI... */ 807 writel_relaxed(2 << 24 | d->hwirq, 808 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 809 return; 810 } 811 812 gic_lock_irqsave(flags); 813 814 /* Convert our logical CPU mask into a physical one. */ 815 for_each_cpu(cpu, mask) 816 map |= gic_cpu_map[cpu]; 817 818 /* 819 * Ensure that stores to Normal memory are visible to the 820 * other CPUs before they observe us issuing the IPI. 821 */ 822 dmb(ishst); 823 824 /* this always happens on GIC0 */ 825 writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 826 827 gic_unlock_irqrestore(flags); 828 } 829 830 static int gic_starting_cpu(unsigned int cpu) 831 { 832 gic_cpu_init(&gic_data[0]); 833 return 0; 834 } 835 836 static __init void gic_smp_init(void) 837 { 838 struct irq_fwspec sgi_fwspec = { 839 .fwnode = gic_data[0].domain->fwnode, 840 .param_count = 1, 841 }; 842 int base_sgi; 843 844 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 845 "irqchip/arm/gic:starting", 846 gic_starting_cpu, NULL); 847 848 base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8, 849 NUMA_NO_NODE, &sgi_fwspec, 850 false, NULL); 851 if (WARN_ON(base_sgi <= 0)) 852 return; 853 854 set_smp_ipi_range(base_sgi, 8); 855 } 856 #else 857 #define gic_smp_init() do { } while(0) 858 #define gic_set_affinity NULL 859 #define gic_ipi_send_mask NULL 860 #endif 861 862 #ifdef CONFIG_BL_SWITCHER 863 /* 864 * gic_send_sgi - send a SGI directly to given CPU interface number 865 * 866 * cpu_id: the ID for the destination CPU interface 867 * irq: the IPI number to send a SGI for 868 */ 869 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 870 { 871 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 872 cpu_id = 1 << cpu_id; 873 /* this always happens on GIC0 */ 874 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 875 } 876 877 /* 878 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 879 * 880 * @cpu: the logical CPU number to get the GIC ID for. 881 * 882 * Return the CPU interface ID for the given logical CPU number, 883 * or -1 if the CPU number is too large or the interface ID is 884 * unknown (more than one bit set). 885 */ 886 int gic_get_cpu_id(unsigned int cpu) 887 { 888 unsigned int cpu_bit; 889 890 if (cpu >= NR_GIC_CPU_IF) 891 return -1; 892 cpu_bit = gic_cpu_map[cpu]; 893 if (cpu_bit & (cpu_bit - 1)) 894 return -1; 895 return __ffs(cpu_bit); 896 } 897 898 /* 899 * gic_migrate_target - migrate IRQs to another CPU interface 900 * 901 * @new_cpu_id: the CPU target ID to migrate IRQs to 902 * 903 * Migrate all peripheral interrupts with a target matching the current CPU 904 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 905 * is also updated. Targets to other CPU interfaces are unchanged. 906 * This must be called with IRQs locally disabled. 907 */ 908 void gic_migrate_target(unsigned int new_cpu_id) 909 { 910 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 911 void __iomem *dist_base; 912 int i, ror_val, cpu = smp_processor_id(); 913 u32 val, cur_target_mask, active_mask; 914 915 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 916 917 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 918 if (!dist_base) 919 return; 920 gic_irqs = gic_data[gic_nr].gic_irqs; 921 922 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 923 cur_target_mask = 0x01010101 << cur_cpu_id; 924 ror_val = (cur_cpu_id - new_cpu_id) & 31; 925 926 gic_lock(); 927 928 /* Update the target interface for this logical CPU */ 929 gic_cpu_map[cpu] = 1 << new_cpu_id; 930 931 /* 932 * Find all the peripheral interrupts targeting the current 933 * CPU interface and migrate them to the new CPU interface. 934 * We skip DIST_TARGET 0 to 7 as they are read-only. 935 */ 936 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 937 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 938 active_mask = val & cur_target_mask; 939 if (active_mask) { 940 val &= ~active_mask; 941 val |= ror32(active_mask, ror_val); 942 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 943 } 944 } 945 946 gic_unlock(); 947 948 /* 949 * Now let's migrate and clear any potential SGIs that might be 950 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 951 * is a banked register, we can only forward the SGI using 952 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 953 * doesn't use that information anyway. 954 * 955 * For the same reason we do not adjust SGI source information 956 * for previously sent SGIs by us to other CPUs either. 957 */ 958 for (i = 0; i < 16; i += 4) { 959 int j; 960 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 961 if (!val) 962 continue; 963 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 964 for (j = i; j < i + 4; j++) { 965 if (val & 0xff) 966 writel_relaxed((1 << (new_cpu_id + 16)) | j, 967 dist_base + GIC_DIST_SOFTINT); 968 val >>= 8; 969 } 970 } 971 } 972 973 /* 974 * gic_get_sgir_physaddr - get the physical address for the SGI register 975 * 976 * REturn the physical address of the SGI register to be used 977 * by some early assembly code when the kernel is not yet available. 978 */ 979 static unsigned long gic_dist_physaddr; 980 981 unsigned long gic_get_sgir_physaddr(void) 982 { 983 if (!gic_dist_physaddr) 984 return 0; 985 return gic_dist_physaddr + GIC_DIST_SOFTINT; 986 } 987 988 static void __init gic_init_physaddr(struct device_node *node) 989 { 990 struct resource res; 991 if (of_address_to_resource(node, 0, &res) == 0) { 992 gic_dist_physaddr = res.start; 993 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 994 } 995 } 996 997 #else 998 #define gic_init_physaddr(node) do { } while (0) 999 #endif 1000 1001 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 1002 irq_hw_number_t hw) 1003 { 1004 struct gic_chip_data *gic = d->host_data; 1005 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); 1006 1007 switch (hw) { 1008 case 0 ... 15: 1009 irq_set_percpu_devid(irq); 1010 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 1011 handle_percpu_devid_fasteoi_ipi, 1012 NULL, NULL); 1013 break; 1014 case 16 ... 31: 1015 irq_set_percpu_devid(irq); 1016 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 1017 handle_percpu_devid_irq, NULL, NULL); 1018 break; 1019 default: 1020 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 1021 handle_fasteoi_irq, NULL, NULL); 1022 irq_set_probe(irq); 1023 irqd_set_single_target(irqd); 1024 break; 1025 } 1026 1027 /* Prevents SW retriggers which mess up the ACK/EOI ordering */ 1028 irqd_set_handle_enforce_irqctx(irqd); 1029 return 0; 1030 } 1031 1032 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 1033 { 1034 } 1035 1036 static int gic_irq_domain_translate(struct irq_domain *d, 1037 struct irq_fwspec *fwspec, 1038 unsigned long *hwirq, 1039 unsigned int *type) 1040 { 1041 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { 1042 *hwirq = fwspec->param[0]; 1043 *type = IRQ_TYPE_EDGE_RISING; 1044 return 0; 1045 } 1046 1047 if (is_of_node(fwspec->fwnode)) { 1048 if (fwspec->param_count < 3) 1049 return -EINVAL; 1050 1051 switch (fwspec->param[0]) { 1052 case 0: /* SPI */ 1053 *hwirq = fwspec->param[1] + 32; 1054 break; 1055 case 1: /* PPI */ 1056 *hwirq = fwspec->param[1] + 16; 1057 break; 1058 default: 1059 return -EINVAL; 1060 } 1061 1062 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1063 1064 /* Make it clear that broken DTs are... broken */ 1065 WARN_ON(*type == IRQ_TYPE_NONE); 1066 return 0; 1067 } 1068 1069 if (is_fwnode_irqchip(fwspec->fwnode)) { 1070 if(fwspec->param_count != 2) 1071 return -EINVAL; 1072 1073 *hwirq = fwspec->param[0]; 1074 *type = fwspec->param[1]; 1075 1076 WARN_ON(*type == IRQ_TYPE_NONE); 1077 return 0; 1078 } 1079 1080 return -EINVAL; 1081 } 1082 1083 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1084 unsigned int nr_irqs, void *arg) 1085 { 1086 int i, ret; 1087 irq_hw_number_t hwirq; 1088 unsigned int type = IRQ_TYPE_NONE; 1089 struct irq_fwspec *fwspec = arg; 1090 1091 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1092 if (ret) 1093 return ret; 1094 1095 for (i = 0; i < nr_irqs; i++) { 1096 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 1097 if (ret) 1098 return ret; 1099 } 1100 1101 return 0; 1102 } 1103 1104 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 1105 .translate = gic_irq_domain_translate, 1106 .alloc = gic_irq_domain_alloc, 1107 .free = irq_domain_free_irqs_top, 1108 }; 1109 1110 static const struct irq_domain_ops gic_irq_domain_ops = { 1111 .map = gic_irq_domain_map, 1112 .unmap = gic_irq_domain_unmap, 1113 }; 1114 1115 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, 1116 const char *name, bool use_eoimode1) 1117 { 1118 /* Initialize irq_chip */ 1119 gic->chip = gic_chip; 1120 gic->chip.name = name; 1121 gic->chip.parent_device = dev; 1122 1123 if (use_eoimode1) { 1124 gic->chip.irq_mask = gic_eoimode1_mask_irq; 1125 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; 1126 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; 1127 } 1128 1129 if (gic == &gic_data[0]) { 1130 gic->chip.irq_set_affinity = gic_set_affinity; 1131 gic->chip.ipi_send_mask = gic_ipi_send_mask; 1132 } 1133 } 1134 1135 static int gic_init_bases(struct gic_chip_data *gic, 1136 struct fwnode_handle *handle) 1137 { 1138 int gic_irqs, ret; 1139 1140 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1141 /* Frankein-GIC without banked registers... */ 1142 unsigned int cpu; 1143 1144 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 1145 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 1146 if (WARN_ON(!gic->dist_base.percpu_base || 1147 !gic->cpu_base.percpu_base)) { 1148 ret = -ENOMEM; 1149 goto error; 1150 } 1151 1152 for_each_possible_cpu(cpu) { 1153 u32 mpidr = cpu_logical_map(cpu); 1154 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 1155 unsigned long offset = gic->percpu_offset * core_id; 1156 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 1157 gic->raw_dist_base + offset; 1158 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = 1159 gic->raw_cpu_base + offset; 1160 } 1161 1162 enable_frankengic(); 1163 } else { 1164 /* Normal, sane GIC... */ 1165 WARN(gic->percpu_offset, 1166 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 1167 gic->percpu_offset); 1168 gic->dist_base.common_base = gic->raw_dist_base; 1169 gic->cpu_base.common_base = gic->raw_cpu_base; 1170 } 1171 1172 /* 1173 * Find out how many interrupts are supported. 1174 * The GIC only supports up to 1020 interrupt sources. 1175 */ 1176 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1177 gic_irqs = (gic_irqs + 1) * 32; 1178 if (gic_irqs > 1020) 1179 gic_irqs = 1020; 1180 gic->gic_irqs = gic_irqs; 1181 1182 if (handle) { /* DT/ACPI */ 1183 gic->domain = irq_domain_create_linear(handle, gic_irqs, 1184 &gic_irq_domain_hierarchy_ops, 1185 gic); 1186 } else { /* Legacy support */ 1187 /* 1188 * For primary GICs, skip over SGIs. 1189 * No secondary GIC support whatsoever. 1190 */ 1191 int irq_base; 1192 1193 gic_irqs -= 16; /* calculate # of irqs to allocate */ 1194 1195 irq_base = irq_alloc_descs(16, 16, gic_irqs, 1196 numa_node_id()); 1197 if (irq_base < 0) { 1198 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n"); 1199 irq_base = 16; 1200 } 1201 1202 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, 1203 16, &gic_irq_domain_ops, gic); 1204 } 1205 1206 if (WARN_ON(!gic->domain)) { 1207 ret = -ENODEV; 1208 goto error; 1209 } 1210 1211 gic_dist_init(gic); 1212 ret = gic_cpu_init(gic); 1213 if (ret) 1214 goto error; 1215 1216 ret = gic_pm_init(gic); 1217 if (ret) 1218 goto error; 1219 1220 return 0; 1221 1222 error: 1223 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1224 free_percpu(gic->dist_base.percpu_base); 1225 free_percpu(gic->cpu_base.percpu_base); 1226 } 1227 1228 return ret; 1229 } 1230 1231 static int __init __gic_init_bases(struct gic_chip_data *gic, 1232 struct fwnode_handle *handle) 1233 { 1234 char *name; 1235 int i, ret; 1236 1237 if (WARN_ON(!gic || gic->domain)) 1238 return -EINVAL; 1239 1240 if (gic == &gic_data[0]) { 1241 /* 1242 * Initialize the CPU interface map to all CPUs. 1243 * It will be refined as each CPU probes its ID. 1244 * This is only necessary for the primary GIC. 1245 */ 1246 for (i = 0; i < NR_GIC_CPU_IF; i++) 1247 gic_cpu_map[i] = 0xff; 1248 1249 set_handle_irq(gic_handle_irq); 1250 if (static_branch_likely(&supports_deactivate_key)) 1251 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1252 } 1253 1254 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { 1255 name = kasprintf(GFP_KERNEL, "GICv2"); 1256 gic_init_chip(gic, NULL, name, true); 1257 } else { 1258 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); 1259 gic_init_chip(gic, NULL, name, false); 1260 } 1261 1262 ret = gic_init_bases(gic, handle); 1263 if (ret) 1264 kfree(name); 1265 else if (gic == &gic_data[0]) 1266 gic_smp_init(); 1267 1268 return ret; 1269 } 1270 1271 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base) 1272 { 1273 struct gic_chip_data *gic; 1274 1275 /* 1276 * Non-DT/ACPI systems won't run a hypervisor, so let's not 1277 * bother with these... 1278 */ 1279 static_branch_disable(&supports_deactivate_key); 1280 1281 gic = &gic_data[0]; 1282 gic->raw_dist_base = dist_base; 1283 gic->raw_cpu_base = cpu_base; 1284 1285 __gic_init_bases(gic, NULL); 1286 } 1287 1288 static void gic_teardown(struct gic_chip_data *gic) 1289 { 1290 if (WARN_ON(!gic)) 1291 return; 1292 1293 if (gic->raw_dist_base) 1294 iounmap(gic->raw_dist_base); 1295 if (gic->raw_cpu_base) 1296 iounmap(gic->raw_cpu_base); 1297 } 1298 1299 #ifdef CONFIG_OF 1300 static int gic_cnt __initdata; 1301 static bool gicv2_force_probe; 1302 1303 static int __init gicv2_force_probe_cfg(char *buf) 1304 { 1305 return strtobool(buf, &gicv2_force_probe); 1306 } 1307 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg); 1308 1309 static bool gic_check_eoimode(struct device_node *node, void __iomem **base) 1310 { 1311 struct resource cpuif_res; 1312 1313 of_address_to_resource(node, 1, &cpuif_res); 1314 1315 if (!is_hyp_mode_available()) 1316 return false; 1317 if (resource_size(&cpuif_res) < SZ_8K) { 1318 void __iomem *alt; 1319 /* 1320 * Check for a stupid firmware that only exposes the 1321 * first page of a GICv2. 1322 */ 1323 if (!gic_check_gicv2(*base)) 1324 return false; 1325 1326 if (!gicv2_force_probe) { 1327 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); 1328 return false; 1329 } 1330 1331 alt = ioremap(cpuif_res.start, SZ_8K); 1332 if (!alt) 1333 return false; 1334 if (!gic_check_gicv2(alt + SZ_4K)) { 1335 /* 1336 * The first page was that of a GICv2, and 1337 * the second was *something*. Let's trust it 1338 * to be a GICv2, and update the mapping. 1339 */ 1340 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", 1341 &cpuif_res.start); 1342 iounmap(*base); 1343 *base = alt; 1344 return true; 1345 } 1346 1347 /* 1348 * We detected *two* initial GICv2 pages in a 1349 * row. Could be a GICv2 aliased over two 64kB 1350 * pages. Update the resource, map the iospace, and 1351 * pray. 1352 */ 1353 iounmap(alt); 1354 alt = ioremap(cpuif_res.start, SZ_128K); 1355 if (!alt) 1356 return false; 1357 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", 1358 &cpuif_res.start); 1359 cpuif_res.end = cpuif_res.start + SZ_128K -1; 1360 iounmap(*base); 1361 *base = alt; 1362 } 1363 if (resource_size(&cpuif_res) == SZ_128K) { 1364 /* 1365 * Verify that we have the first 4kB of a GICv2 1366 * aliased over the first 64kB by checking the 1367 * GICC_IIDR register on both ends. 1368 */ 1369 if (!gic_check_gicv2(*base) || 1370 !gic_check_gicv2(*base + 0xf000)) 1371 return false; 1372 1373 /* 1374 * Move the base up by 60kB, so that we have a 8kB 1375 * contiguous region, which allows us to use GICC_DIR 1376 * at its normal offset. Please pass me that bucket. 1377 */ 1378 *base += 0xf000; 1379 cpuif_res.start += 0xf000; 1380 pr_warn("GIC: Adjusting CPU interface base to %pa\n", 1381 &cpuif_res.start); 1382 } 1383 1384 return true; 1385 } 1386 1387 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) 1388 { 1389 if (!gic || !node) 1390 return -EINVAL; 1391 1392 gic->raw_dist_base = of_iomap(node, 0); 1393 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) 1394 goto error; 1395 1396 gic->raw_cpu_base = of_iomap(node, 1); 1397 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) 1398 goto error; 1399 1400 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) 1401 gic->percpu_offset = 0; 1402 1403 return 0; 1404 1405 error: 1406 gic_teardown(gic); 1407 1408 return -ENOMEM; 1409 } 1410 1411 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1412 { 1413 int ret; 1414 1415 if (!dev || !dev->of_node || !gic || !irq) 1416 return -EINVAL; 1417 1418 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); 1419 if (!*gic) 1420 return -ENOMEM; 1421 1422 gic_init_chip(*gic, dev, dev->of_node->name, false); 1423 1424 ret = gic_of_setup(*gic, dev->of_node); 1425 if (ret) 1426 return ret; 1427 1428 ret = gic_init_bases(*gic, &dev->of_node->fwnode); 1429 if (ret) { 1430 gic_teardown(*gic); 1431 return ret; 1432 } 1433 1434 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); 1435 1436 return 0; 1437 } 1438 1439 static void __init gic_of_setup_kvm_info(struct device_node *node) 1440 { 1441 int ret; 1442 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1443 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1444 1445 gic_v2_kvm_info.type = GIC_V2; 1446 1447 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1448 if (!gic_v2_kvm_info.maint_irq) 1449 return; 1450 1451 ret = of_address_to_resource(node, 2, vctrl_res); 1452 if (ret) 1453 return; 1454 1455 ret = of_address_to_resource(node, 3, vcpu_res); 1456 if (ret) 1457 return; 1458 1459 if (static_branch_likely(&supports_deactivate_key)) 1460 gic_set_kvm_info(&gic_v2_kvm_info); 1461 } 1462 1463 int __init 1464 gic_of_init(struct device_node *node, struct device_node *parent) 1465 { 1466 struct gic_chip_data *gic; 1467 int irq, ret; 1468 1469 if (WARN_ON(!node)) 1470 return -ENODEV; 1471 1472 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) 1473 return -EINVAL; 1474 1475 gic = &gic_data[gic_cnt]; 1476 1477 ret = gic_of_setup(gic, node); 1478 if (ret) 1479 return ret; 1480 1481 /* 1482 * Disable split EOI/Deactivate if either HYP is not available 1483 * or the CPU interface is too small. 1484 */ 1485 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) 1486 static_branch_disable(&supports_deactivate_key); 1487 1488 ret = __gic_init_bases(gic, &node->fwnode); 1489 if (ret) { 1490 gic_teardown(gic); 1491 return ret; 1492 } 1493 1494 if (!gic_cnt) { 1495 gic_init_physaddr(node); 1496 gic_of_setup_kvm_info(node); 1497 } 1498 1499 if (parent) { 1500 irq = irq_of_parse_and_map(node, 0); 1501 gic_cascade_irq(gic_cnt, irq); 1502 } 1503 1504 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1505 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); 1506 1507 gic_cnt++; 1508 return 0; 1509 } 1510 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1511 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1512 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1513 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1514 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1515 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1516 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1517 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1518 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1519 #else 1520 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1521 { 1522 return -ENOTSUPP; 1523 } 1524 #endif 1525 1526 #ifdef CONFIG_ACPI 1527 static struct 1528 { 1529 phys_addr_t cpu_phys_base; 1530 u32 maint_irq; 1531 int maint_irq_mode; 1532 phys_addr_t vctrl_base; 1533 phys_addr_t vcpu_base; 1534 } acpi_data __initdata; 1535 1536 static int __init 1537 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header, 1538 const unsigned long end) 1539 { 1540 struct acpi_madt_generic_interrupt *processor; 1541 phys_addr_t gic_cpu_base; 1542 static int cpu_base_assigned; 1543 1544 processor = (struct acpi_madt_generic_interrupt *)header; 1545 1546 if (BAD_MADT_GICC_ENTRY(processor, end)) 1547 return -EINVAL; 1548 1549 /* 1550 * There is no support for non-banked GICv1/2 register in ACPI spec. 1551 * All CPU interface addresses have to be the same. 1552 */ 1553 gic_cpu_base = processor->base_address; 1554 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) 1555 return -EINVAL; 1556 1557 acpi_data.cpu_phys_base = gic_cpu_base; 1558 acpi_data.maint_irq = processor->vgic_interrupt; 1559 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1560 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1561 acpi_data.vctrl_base = processor->gich_base_address; 1562 acpi_data.vcpu_base = processor->gicv_base_address; 1563 1564 cpu_base_assigned = 1; 1565 return 0; 1566 } 1567 1568 /* The things you have to do to just *count* something... */ 1569 static int __init acpi_dummy_func(union acpi_subtable_headers *header, 1570 const unsigned long end) 1571 { 1572 return 0; 1573 } 1574 1575 static bool __init acpi_gic_redist_is_present(void) 1576 { 1577 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1578 acpi_dummy_func, 0) > 0; 1579 } 1580 1581 static bool __init gic_validate_dist(struct acpi_subtable_header *header, 1582 struct acpi_probe_entry *ape) 1583 { 1584 struct acpi_madt_generic_distributor *dist; 1585 dist = (struct acpi_madt_generic_distributor *)header; 1586 1587 return (dist->version == ape->driver_data && 1588 (dist->version != ACPI_MADT_GIC_VERSION_NONE || 1589 !acpi_gic_redist_is_present())); 1590 } 1591 1592 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) 1593 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) 1594 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1595 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1596 1597 static void __init gic_acpi_setup_kvm_info(void) 1598 { 1599 int irq; 1600 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1601 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1602 1603 gic_v2_kvm_info.type = GIC_V2; 1604 1605 if (!acpi_data.vctrl_base) 1606 return; 1607 1608 vctrl_res->flags = IORESOURCE_MEM; 1609 vctrl_res->start = acpi_data.vctrl_base; 1610 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; 1611 1612 if (!acpi_data.vcpu_base) 1613 return; 1614 1615 vcpu_res->flags = IORESOURCE_MEM; 1616 vcpu_res->start = acpi_data.vcpu_base; 1617 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1618 1619 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1620 acpi_data.maint_irq_mode, 1621 ACPI_ACTIVE_HIGH); 1622 if (irq <= 0) 1623 return; 1624 1625 gic_v2_kvm_info.maint_irq = irq; 1626 1627 gic_set_kvm_info(&gic_v2_kvm_info); 1628 } 1629 1630 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header, 1631 const unsigned long end) 1632 { 1633 struct acpi_madt_generic_distributor *dist; 1634 struct fwnode_handle *domain_handle; 1635 struct gic_chip_data *gic = &gic_data[0]; 1636 int count, ret; 1637 1638 /* Collect CPU base addresses */ 1639 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1640 gic_acpi_parse_madt_cpu, 0); 1641 if (count <= 0) { 1642 pr_err("No valid GICC entries exist\n"); 1643 return -EINVAL; 1644 } 1645 1646 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1647 if (!gic->raw_cpu_base) { 1648 pr_err("Unable to map GICC registers\n"); 1649 return -ENOMEM; 1650 } 1651 1652 dist = (struct acpi_madt_generic_distributor *)header; 1653 gic->raw_dist_base = ioremap(dist->base_address, 1654 ACPI_GICV2_DIST_MEM_SIZE); 1655 if (!gic->raw_dist_base) { 1656 pr_err("Unable to map GICD registers\n"); 1657 gic_teardown(gic); 1658 return -ENOMEM; 1659 } 1660 1661 /* 1662 * Disable split EOI/Deactivate if HYP is not available. ACPI 1663 * guarantees that we'll always have a GICv2, so the CPU 1664 * interface will always be the right size. 1665 */ 1666 if (!is_hyp_mode_available()) 1667 static_branch_disable(&supports_deactivate_key); 1668 1669 /* 1670 * Initialize GIC instance zero (no multi-GIC support). 1671 */ 1672 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 1673 if (!domain_handle) { 1674 pr_err("Unable to allocate domain handle\n"); 1675 gic_teardown(gic); 1676 return -ENOMEM; 1677 } 1678 1679 ret = __gic_init_bases(gic, domain_handle); 1680 if (ret) { 1681 pr_err("Failed to initialise GIC\n"); 1682 irq_domain_free_fwnode(domain_handle); 1683 gic_teardown(gic); 1684 return ret; 1685 } 1686 1687 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1688 1689 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1690 gicv2m_init(NULL, gic_data[0].domain); 1691 1692 if (static_branch_likely(&supports_deactivate_key)) 1693 gic_acpi_setup_kvm_info(); 1694 1695 return 0; 1696 } 1697 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1698 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, 1699 gic_v2_acpi_init); 1700 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1701 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, 1702 gic_v2_acpi_init); 1703 #endif 1704