1 /* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Interrupt architecture for the GIC: 9 * 10 * o There is one Interrupt Distributor, which receives interrupts 11 * from system devices and sends them to the Interrupt Controllers. 12 * 13 * o There is one CPU Interface per CPU, which sends interrupts sent 14 * by the Distributor, and interrupts generated locally, to the 15 * associated CPU. The base address of the CPU interface is usually 16 * aliased so that the same address points to different chips depending 17 * on the CPU it is accessed from. 18 * 19 * Note that IRQs 0-31 are special - they are local to each CPU. 20 * As such, the enable set/clear, pending set/clear and active bit 21 * registers are banked per-cpu for these sources. 22 */ 23 #include <linux/init.h> 24 #include <linux/kernel.h> 25 #include <linux/err.h> 26 #include <linux/module.h> 27 #include <linux/list.h> 28 #include <linux/smp.h> 29 #include <linux/cpu.h> 30 #include <linux/cpu_pm.h> 31 #include <linux/cpumask.h> 32 #include <linux/io.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/acpi.h> 37 #include <linux/irqdomain.h> 38 #include <linux/interrupt.h> 39 #include <linux/percpu.h> 40 #include <linux/slab.h> 41 #include <linux/irqchip/chained_irq.h> 42 #include <linux/irqchip/arm-gic.h> 43 #include <linux/irqchip/arm-gic-acpi.h> 44 45 #include <asm/cputype.h> 46 #include <asm/irq.h> 47 #include <asm/exception.h> 48 #include <asm/smp_plat.h> 49 50 #include "irq-gic-common.h" 51 #include "irqchip.h" 52 53 union gic_base { 54 void __iomem *common_base; 55 void __percpu * __iomem *percpu_base; 56 }; 57 58 struct gic_chip_data { 59 union gic_base dist_base; 60 union gic_base cpu_base; 61 #ifdef CONFIG_CPU_PM 62 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 63 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 64 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 65 u32 __percpu *saved_ppi_enable; 66 u32 __percpu *saved_ppi_conf; 67 #endif 68 struct irq_domain *domain; 69 unsigned int gic_irqs; 70 #ifdef CONFIG_GIC_NON_BANKED 71 void __iomem *(*get_base)(union gic_base *); 72 #endif 73 }; 74 75 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 76 77 /* 78 * The GIC mapping of CPU interfaces does not necessarily match 79 * the logical CPU numbering. Let's use a mapping as returned 80 * by the GIC itself. 81 */ 82 #define NR_GIC_CPU_IF 8 83 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 84 85 #ifndef MAX_GIC_NR 86 #define MAX_GIC_NR 1 87 #endif 88 89 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; 90 91 #ifdef CONFIG_GIC_NON_BANKED 92 static void __iomem *gic_get_percpu_base(union gic_base *base) 93 { 94 return raw_cpu_read(*base->percpu_base); 95 } 96 97 static void __iomem *gic_get_common_base(union gic_base *base) 98 { 99 return base->common_base; 100 } 101 102 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 103 { 104 return data->get_base(&data->dist_base); 105 } 106 107 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 108 { 109 return data->get_base(&data->cpu_base); 110 } 111 112 static inline void gic_set_base_accessor(struct gic_chip_data *data, 113 void __iomem *(*f)(union gic_base *)) 114 { 115 data->get_base = f; 116 } 117 #else 118 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 119 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 120 #define gic_set_base_accessor(d, f) 121 #endif 122 123 static inline void __iomem *gic_dist_base(struct irq_data *d) 124 { 125 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 126 return gic_data_dist_base(gic_data); 127 } 128 129 static inline void __iomem *gic_cpu_base(struct irq_data *d) 130 { 131 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 132 return gic_data_cpu_base(gic_data); 133 } 134 135 static inline unsigned int gic_irq(struct irq_data *d) 136 { 137 return d->hwirq; 138 } 139 140 /* 141 * Routines to acknowledge, disable and enable interrupts 142 */ 143 static void gic_poke_irq(struct irq_data *d, u32 offset) 144 { 145 u32 mask = 1 << (gic_irq(d) % 32); 146 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 147 } 148 149 static int gic_peek_irq(struct irq_data *d, u32 offset) 150 { 151 u32 mask = 1 << (gic_irq(d) % 32); 152 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 153 } 154 155 static void gic_mask_irq(struct irq_data *d) 156 { 157 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 158 } 159 160 static void gic_unmask_irq(struct irq_data *d) 161 { 162 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 163 } 164 165 static void gic_eoi_irq(struct irq_data *d) 166 { 167 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 168 } 169 170 static int gic_irq_set_irqchip_state(struct irq_data *d, 171 enum irqchip_irq_state which, bool val) 172 { 173 u32 reg; 174 175 switch (which) { 176 case IRQCHIP_STATE_PENDING: 177 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 178 break; 179 180 case IRQCHIP_STATE_ACTIVE: 181 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 182 break; 183 184 case IRQCHIP_STATE_MASKED: 185 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 186 break; 187 188 default: 189 return -EINVAL; 190 } 191 192 gic_poke_irq(d, reg); 193 return 0; 194 } 195 196 static int gic_irq_get_irqchip_state(struct irq_data *d, 197 enum irqchip_irq_state which, bool *val) 198 { 199 switch (which) { 200 case IRQCHIP_STATE_PENDING: 201 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 202 break; 203 204 case IRQCHIP_STATE_ACTIVE: 205 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 206 break; 207 208 case IRQCHIP_STATE_MASKED: 209 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 210 break; 211 212 default: 213 return -EINVAL; 214 } 215 216 return 0; 217 } 218 219 static int gic_set_type(struct irq_data *d, unsigned int type) 220 { 221 void __iomem *base = gic_dist_base(d); 222 unsigned int gicirq = gic_irq(d); 223 224 /* Interrupt configuration for SGIs can't be changed */ 225 if (gicirq < 16) 226 return -EINVAL; 227 228 /* SPIs have restrictions on the supported types */ 229 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 230 type != IRQ_TYPE_EDGE_RISING) 231 return -EINVAL; 232 233 return gic_configure_irq(gicirq, type, base, NULL); 234 } 235 236 #ifdef CONFIG_SMP 237 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 238 bool force) 239 { 240 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 241 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 242 u32 val, mask, bit; 243 unsigned long flags; 244 245 if (!force) 246 cpu = cpumask_any_and(mask_val, cpu_online_mask); 247 else 248 cpu = cpumask_first(mask_val); 249 250 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 251 return -EINVAL; 252 253 raw_spin_lock_irqsave(&irq_controller_lock, flags); 254 mask = 0xff << shift; 255 bit = gic_cpu_map[cpu] << shift; 256 val = readl_relaxed(reg) & ~mask; 257 writel_relaxed(val | bit, reg); 258 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 259 260 return IRQ_SET_MASK_OK; 261 } 262 #endif 263 264 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 265 { 266 u32 irqstat, irqnr; 267 struct gic_chip_data *gic = &gic_data[0]; 268 void __iomem *cpu_base = gic_data_cpu_base(gic); 269 270 do { 271 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 272 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 273 274 if (likely(irqnr > 15 && irqnr < 1021)) { 275 handle_domain_irq(gic->domain, irqnr, regs); 276 continue; 277 } 278 if (irqnr < 16) { 279 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 280 #ifdef CONFIG_SMP 281 handle_IPI(irqnr, regs); 282 #endif 283 continue; 284 } 285 break; 286 } while (1); 287 } 288 289 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 290 { 291 struct gic_chip_data *chip_data = irq_get_handler_data(irq); 292 struct irq_chip *chip = irq_get_chip(irq); 293 unsigned int cascade_irq, gic_irq; 294 unsigned long status; 295 296 chained_irq_enter(chip, desc); 297 298 raw_spin_lock(&irq_controller_lock); 299 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 300 raw_spin_unlock(&irq_controller_lock); 301 302 gic_irq = (status & GICC_IAR_INT_ID_MASK); 303 if (gic_irq == GICC_INT_SPURIOUS) 304 goto out; 305 306 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 307 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 308 handle_bad_irq(cascade_irq, desc); 309 else 310 generic_handle_irq(cascade_irq); 311 312 out: 313 chained_irq_exit(chip, desc); 314 } 315 316 static struct irq_chip gic_chip = { 317 .name = "GIC", 318 .irq_mask = gic_mask_irq, 319 .irq_unmask = gic_unmask_irq, 320 .irq_eoi = gic_eoi_irq, 321 .irq_set_type = gic_set_type, 322 #ifdef CONFIG_SMP 323 .irq_set_affinity = gic_set_affinity, 324 #endif 325 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 326 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 327 }; 328 329 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 330 { 331 if (gic_nr >= MAX_GIC_NR) 332 BUG(); 333 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) 334 BUG(); 335 irq_set_chained_handler(irq, gic_handle_cascade_irq); 336 } 337 338 static u8 gic_get_cpumask(struct gic_chip_data *gic) 339 { 340 void __iomem *base = gic_data_dist_base(gic); 341 u32 mask, i; 342 343 for (i = mask = 0; i < 32; i += 4) { 344 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 345 mask |= mask >> 16; 346 mask |= mask >> 8; 347 if (mask) 348 break; 349 } 350 351 if (!mask && num_possible_cpus() > 1) 352 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 353 354 return mask; 355 } 356 357 static void gic_cpu_if_up(void) 358 { 359 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 360 u32 bypass = 0; 361 362 /* 363 * Preserve bypass disable bits to be written back later 364 */ 365 bypass = readl(cpu_base + GIC_CPU_CTRL); 366 bypass &= GICC_DIS_BYPASS_MASK; 367 368 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 369 } 370 371 372 static void __init gic_dist_init(struct gic_chip_data *gic) 373 { 374 unsigned int i; 375 u32 cpumask; 376 unsigned int gic_irqs = gic->gic_irqs; 377 void __iomem *base = gic_data_dist_base(gic); 378 379 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 380 381 /* 382 * Set all global interrupts to this CPU only. 383 */ 384 cpumask = gic_get_cpumask(gic); 385 cpumask |= cpumask << 8; 386 cpumask |= cpumask << 16; 387 for (i = 32; i < gic_irqs; i += 4) 388 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 389 390 gic_dist_config(base, gic_irqs, NULL); 391 392 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 393 } 394 395 static void gic_cpu_init(struct gic_chip_data *gic) 396 { 397 void __iomem *dist_base = gic_data_dist_base(gic); 398 void __iomem *base = gic_data_cpu_base(gic); 399 unsigned int cpu_mask, cpu = smp_processor_id(); 400 int i; 401 402 /* 403 * Get what the GIC says our CPU mask is. 404 */ 405 BUG_ON(cpu >= NR_GIC_CPU_IF); 406 cpu_mask = gic_get_cpumask(gic); 407 gic_cpu_map[cpu] = cpu_mask; 408 409 /* 410 * Clear our mask from the other map entries in case they're 411 * still undefined. 412 */ 413 for (i = 0; i < NR_GIC_CPU_IF; i++) 414 if (i != cpu) 415 gic_cpu_map[i] &= ~cpu_mask; 416 417 gic_cpu_config(dist_base, NULL); 418 419 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 420 gic_cpu_if_up(); 421 } 422 423 void gic_cpu_if_down(void) 424 { 425 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 426 u32 val = 0; 427 428 val = readl(cpu_base + GIC_CPU_CTRL); 429 val &= ~GICC_ENABLE; 430 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 431 } 432 433 #ifdef CONFIG_CPU_PM 434 /* 435 * Saves the GIC distributor registers during suspend or idle. Must be called 436 * with interrupts disabled but before powering down the GIC. After calling 437 * this function, no interrupts will be delivered by the GIC, and another 438 * platform-specific wakeup source must be enabled. 439 */ 440 static void gic_dist_save(unsigned int gic_nr) 441 { 442 unsigned int gic_irqs; 443 void __iomem *dist_base; 444 int i; 445 446 if (gic_nr >= MAX_GIC_NR) 447 BUG(); 448 449 gic_irqs = gic_data[gic_nr].gic_irqs; 450 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 451 452 if (!dist_base) 453 return; 454 455 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 456 gic_data[gic_nr].saved_spi_conf[i] = 457 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 458 459 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 460 gic_data[gic_nr].saved_spi_target[i] = 461 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 462 463 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 464 gic_data[gic_nr].saved_spi_enable[i] = 465 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 466 } 467 468 /* 469 * Restores the GIC distributor registers during resume or when coming out of 470 * idle. Must be called before enabling interrupts. If a level interrupt 471 * that occured while the GIC was suspended is still present, it will be 472 * handled normally, but any edge interrupts that occured will not be seen by 473 * the GIC and need to be handled by the platform-specific wakeup source. 474 */ 475 static void gic_dist_restore(unsigned int gic_nr) 476 { 477 unsigned int gic_irqs; 478 unsigned int i; 479 void __iomem *dist_base; 480 481 if (gic_nr >= MAX_GIC_NR) 482 BUG(); 483 484 gic_irqs = gic_data[gic_nr].gic_irqs; 485 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 486 487 if (!dist_base) 488 return; 489 490 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 491 492 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 493 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], 494 dist_base + GIC_DIST_CONFIG + i * 4); 495 496 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 497 writel_relaxed(GICD_INT_DEF_PRI_X4, 498 dist_base + GIC_DIST_PRI + i * 4); 499 500 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 501 writel_relaxed(gic_data[gic_nr].saved_spi_target[i], 502 dist_base + GIC_DIST_TARGET + i * 4); 503 504 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 505 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], 506 dist_base + GIC_DIST_ENABLE_SET + i * 4); 507 508 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 509 } 510 511 static void gic_cpu_save(unsigned int gic_nr) 512 { 513 int i; 514 u32 *ptr; 515 void __iomem *dist_base; 516 void __iomem *cpu_base; 517 518 if (gic_nr >= MAX_GIC_NR) 519 BUG(); 520 521 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 522 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 523 524 if (!dist_base || !cpu_base) 525 return; 526 527 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 528 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 529 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 530 531 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 532 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 533 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 534 535 } 536 537 static void gic_cpu_restore(unsigned int gic_nr) 538 { 539 int i; 540 u32 *ptr; 541 void __iomem *dist_base; 542 void __iomem *cpu_base; 543 544 if (gic_nr >= MAX_GIC_NR) 545 BUG(); 546 547 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 548 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 549 550 if (!dist_base || !cpu_base) 551 return; 552 553 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 554 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 555 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 556 557 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 558 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 559 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 560 561 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 562 writel_relaxed(GICD_INT_DEF_PRI_X4, 563 dist_base + GIC_DIST_PRI + i * 4); 564 565 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 566 gic_cpu_if_up(); 567 } 568 569 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 570 { 571 int i; 572 573 for (i = 0; i < MAX_GIC_NR; i++) { 574 #ifdef CONFIG_GIC_NON_BANKED 575 /* Skip over unused GICs */ 576 if (!gic_data[i].get_base) 577 continue; 578 #endif 579 switch (cmd) { 580 case CPU_PM_ENTER: 581 gic_cpu_save(i); 582 break; 583 case CPU_PM_ENTER_FAILED: 584 case CPU_PM_EXIT: 585 gic_cpu_restore(i); 586 break; 587 case CPU_CLUSTER_PM_ENTER: 588 gic_dist_save(i); 589 break; 590 case CPU_CLUSTER_PM_ENTER_FAILED: 591 case CPU_CLUSTER_PM_EXIT: 592 gic_dist_restore(i); 593 break; 594 } 595 } 596 597 return NOTIFY_OK; 598 } 599 600 static struct notifier_block gic_notifier_block = { 601 .notifier_call = gic_notifier, 602 }; 603 604 static void __init gic_pm_init(struct gic_chip_data *gic) 605 { 606 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 607 sizeof(u32)); 608 BUG_ON(!gic->saved_ppi_enable); 609 610 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 611 sizeof(u32)); 612 BUG_ON(!gic->saved_ppi_conf); 613 614 if (gic == &gic_data[0]) 615 cpu_pm_register_notifier(&gic_notifier_block); 616 } 617 #else 618 static void __init gic_pm_init(struct gic_chip_data *gic) 619 { 620 } 621 #endif 622 623 #ifdef CONFIG_SMP 624 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 625 { 626 int cpu; 627 unsigned long flags, map = 0; 628 629 raw_spin_lock_irqsave(&irq_controller_lock, flags); 630 631 /* Convert our logical CPU mask into a physical one. */ 632 for_each_cpu(cpu, mask) 633 map |= gic_cpu_map[cpu]; 634 635 /* 636 * Ensure that stores to Normal memory are visible to the 637 * other CPUs before they observe us issuing the IPI. 638 */ 639 dmb(ishst); 640 641 /* this always happens on GIC0 */ 642 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 643 644 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 645 } 646 #endif 647 648 #ifdef CONFIG_BL_SWITCHER 649 /* 650 * gic_send_sgi - send a SGI directly to given CPU interface number 651 * 652 * cpu_id: the ID for the destination CPU interface 653 * irq: the IPI number to send a SGI for 654 */ 655 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 656 { 657 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 658 cpu_id = 1 << cpu_id; 659 /* this always happens on GIC0 */ 660 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 661 } 662 663 /* 664 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 665 * 666 * @cpu: the logical CPU number to get the GIC ID for. 667 * 668 * Return the CPU interface ID for the given logical CPU number, 669 * or -1 if the CPU number is too large or the interface ID is 670 * unknown (more than one bit set). 671 */ 672 int gic_get_cpu_id(unsigned int cpu) 673 { 674 unsigned int cpu_bit; 675 676 if (cpu >= NR_GIC_CPU_IF) 677 return -1; 678 cpu_bit = gic_cpu_map[cpu]; 679 if (cpu_bit & (cpu_bit - 1)) 680 return -1; 681 return __ffs(cpu_bit); 682 } 683 684 /* 685 * gic_migrate_target - migrate IRQs to another CPU interface 686 * 687 * @new_cpu_id: the CPU target ID to migrate IRQs to 688 * 689 * Migrate all peripheral interrupts with a target matching the current CPU 690 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 691 * is also updated. Targets to other CPU interfaces are unchanged. 692 * This must be called with IRQs locally disabled. 693 */ 694 void gic_migrate_target(unsigned int new_cpu_id) 695 { 696 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 697 void __iomem *dist_base; 698 int i, ror_val, cpu = smp_processor_id(); 699 u32 val, cur_target_mask, active_mask; 700 701 if (gic_nr >= MAX_GIC_NR) 702 BUG(); 703 704 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 705 if (!dist_base) 706 return; 707 gic_irqs = gic_data[gic_nr].gic_irqs; 708 709 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 710 cur_target_mask = 0x01010101 << cur_cpu_id; 711 ror_val = (cur_cpu_id - new_cpu_id) & 31; 712 713 raw_spin_lock(&irq_controller_lock); 714 715 /* Update the target interface for this logical CPU */ 716 gic_cpu_map[cpu] = 1 << new_cpu_id; 717 718 /* 719 * Find all the peripheral interrupts targetting the current 720 * CPU interface and migrate them to the new CPU interface. 721 * We skip DIST_TARGET 0 to 7 as they are read-only. 722 */ 723 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 724 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 725 active_mask = val & cur_target_mask; 726 if (active_mask) { 727 val &= ~active_mask; 728 val |= ror32(active_mask, ror_val); 729 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 730 } 731 } 732 733 raw_spin_unlock(&irq_controller_lock); 734 735 /* 736 * Now let's migrate and clear any potential SGIs that might be 737 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 738 * is a banked register, we can only forward the SGI using 739 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 740 * doesn't use that information anyway. 741 * 742 * For the same reason we do not adjust SGI source information 743 * for previously sent SGIs by us to other CPUs either. 744 */ 745 for (i = 0; i < 16; i += 4) { 746 int j; 747 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 748 if (!val) 749 continue; 750 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 751 for (j = i; j < i + 4; j++) { 752 if (val & 0xff) 753 writel_relaxed((1 << (new_cpu_id + 16)) | j, 754 dist_base + GIC_DIST_SOFTINT); 755 val >>= 8; 756 } 757 } 758 } 759 760 /* 761 * gic_get_sgir_physaddr - get the physical address for the SGI register 762 * 763 * REturn the physical address of the SGI register to be used 764 * by some early assembly code when the kernel is not yet available. 765 */ 766 static unsigned long gic_dist_physaddr; 767 768 unsigned long gic_get_sgir_physaddr(void) 769 { 770 if (!gic_dist_physaddr) 771 return 0; 772 return gic_dist_physaddr + GIC_DIST_SOFTINT; 773 } 774 775 void __init gic_init_physaddr(struct device_node *node) 776 { 777 struct resource res; 778 if (of_address_to_resource(node, 0, &res) == 0) { 779 gic_dist_physaddr = res.start; 780 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 781 } 782 } 783 784 #else 785 #define gic_init_physaddr(node) do { } while (0) 786 #endif 787 788 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 789 irq_hw_number_t hw) 790 { 791 if (hw < 32) { 792 irq_set_percpu_devid(irq); 793 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 794 handle_percpu_devid_irq, NULL, NULL); 795 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 796 } else { 797 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 798 handle_fasteoi_irq, NULL, NULL); 799 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 800 } 801 return 0; 802 } 803 804 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 805 { 806 } 807 808 static int gic_irq_domain_xlate(struct irq_domain *d, 809 struct device_node *controller, 810 const u32 *intspec, unsigned int intsize, 811 unsigned long *out_hwirq, unsigned int *out_type) 812 { 813 unsigned long ret = 0; 814 815 if (d->of_node != controller) 816 return -EINVAL; 817 if (intsize < 3) 818 return -EINVAL; 819 820 /* Get the interrupt number and add 16 to skip over SGIs */ 821 *out_hwirq = intspec[1] + 16; 822 823 /* For SPIs, we need to add 16 more to get the GIC irq ID number */ 824 if (!intspec[0]) 825 *out_hwirq += 16; 826 827 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 828 829 return ret; 830 } 831 832 #ifdef CONFIG_SMP 833 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, 834 void *hcpu) 835 { 836 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 837 gic_cpu_init(&gic_data[0]); 838 return NOTIFY_OK; 839 } 840 841 /* 842 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 843 * priority because the GIC needs to be up before the ARM generic timers. 844 */ 845 static struct notifier_block gic_cpu_notifier = { 846 .notifier_call = gic_secondary_init, 847 .priority = 100, 848 }; 849 #endif 850 851 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 852 unsigned int nr_irqs, void *arg) 853 { 854 int i, ret; 855 irq_hw_number_t hwirq; 856 unsigned int type = IRQ_TYPE_NONE; 857 struct of_phandle_args *irq_data = arg; 858 859 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 860 irq_data->args_count, &hwirq, &type); 861 if (ret) 862 return ret; 863 864 for (i = 0; i < nr_irqs; i++) 865 gic_irq_domain_map(domain, virq + i, hwirq + i); 866 867 return 0; 868 } 869 870 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 871 .xlate = gic_irq_domain_xlate, 872 .alloc = gic_irq_domain_alloc, 873 .free = irq_domain_free_irqs_top, 874 }; 875 876 static const struct irq_domain_ops gic_irq_domain_ops = { 877 .map = gic_irq_domain_map, 878 .unmap = gic_irq_domain_unmap, 879 .xlate = gic_irq_domain_xlate, 880 }; 881 882 void gic_set_irqchip_flags(unsigned long flags) 883 { 884 gic_chip.flags |= flags; 885 } 886 887 void __init gic_init_bases(unsigned int gic_nr, int irq_start, 888 void __iomem *dist_base, void __iomem *cpu_base, 889 u32 percpu_offset, struct device_node *node) 890 { 891 irq_hw_number_t hwirq_base; 892 struct gic_chip_data *gic; 893 int gic_irqs, irq_base, i; 894 895 BUG_ON(gic_nr >= MAX_GIC_NR); 896 897 gic = &gic_data[gic_nr]; 898 #ifdef CONFIG_GIC_NON_BANKED 899 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 900 unsigned int cpu; 901 902 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 903 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 904 if (WARN_ON(!gic->dist_base.percpu_base || 905 !gic->cpu_base.percpu_base)) { 906 free_percpu(gic->dist_base.percpu_base); 907 free_percpu(gic->cpu_base.percpu_base); 908 return; 909 } 910 911 for_each_possible_cpu(cpu) { 912 u32 mpidr = cpu_logical_map(cpu); 913 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 914 unsigned long offset = percpu_offset * core_id; 915 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; 916 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; 917 } 918 919 gic_set_base_accessor(gic, gic_get_percpu_base); 920 } else 921 #endif 922 { /* Normal, sane GIC... */ 923 WARN(percpu_offset, 924 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 925 percpu_offset); 926 gic->dist_base.common_base = dist_base; 927 gic->cpu_base.common_base = cpu_base; 928 gic_set_base_accessor(gic, gic_get_common_base); 929 } 930 931 /* 932 * Initialize the CPU interface map to all CPUs. 933 * It will be refined as each CPU probes its ID. 934 */ 935 for (i = 0; i < NR_GIC_CPU_IF; i++) 936 gic_cpu_map[i] = 0xff; 937 938 /* 939 * Find out how many interrupts are supported. 940 * The GIC only supports up to 1020 interrupt sources. 941 */ 942 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 943 gic_irqs = (gic_irqs + 1) * 32; 944 if (gic_irqs > 1020) 945 gic_irqs = 1020; 946 gic->gic_irqs = gic_irqs; 947 948 if (node) { /* DT case */ 949 gic->domain = irq_domain_add_linear(node, gic_irqs, 950 &gic_irq_domain_hierarchy_ops, 951 gic); 952 } else { /* Non-DT case */ 953 /* 954 * For primary GICs, skip over SGIs. 955 * For secondary GICs, skip over PPIs, too. 956 */ 957 if (gic_nr == 0 && (irq_start & 31) > 0) { 958 hwirq_base = 16; 959 if (irq_start != -1) 960 irq_start = (irq_start & ~31) + 16; 961 } else { 962 hwirq_base = 32; 963 } 964 965 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 966 967 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 968 numa_node_id()); 969 if (IS_ERR_VALUE(irq_base)) { 970 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 971 irq_start); 972 irq_base = irq_start; 973 } 974 975 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, 976 hwirq_base, &gic_irq_domain_ops, gic); 977 } 978 979 if (WARN_ON(!gic->domain)) 980 return; 981 982 if (gic_nr == 0) { 983 #ifdef CONFIG_SMP 984 set_smp_cross_call(gic_raise_softirq); 985 register_cpu_notifier(&gic_cpu_notifier); 986 #endif 987 set_handle_irq(gic_handle_irq); 988 } 989 990 gic_dist_init(gic); 991 gic_cpu_init(gic); 992 gic_pm_init(gic); 993 } 994 995 #ifdef CONFIG_OF 996 static int gic_cnt __initdata; 997 998 static int __init 999 gic_of_init(struct device_node *node, struct device_node *parent) 1000 { 1001 void __iomem *cpu_base; 1002 void __iomem *dist_base; 1003 u32 percpu_offset; 1004 int irq; 1005 1006 if (WARN_ON(!node)) 1007 return -ENODEV; 1008 1009 dist_base = of_iomap(node, 0); 1010 WARN(!dist_base, "unable to map gic dist registers\n"); 1011 1012 cpu_base = of_iomap(node, 1); 1013 WARN(!cpu_base, "unable to map gic cpu registers\n"); 1014 1015 if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) 1016 percpu_offset = 0; 1017 1018 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); 1019 if (!gic_cnt) 1020 gic_init_physaddr(node); 1021 1022 if (parent) { 1023 irq = irq_of_parse_and_map(node, 0); 1024 gic_cascade_irq(gic_cnt, irq); 1025 } 1026 1027 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1028 gicv2m_of_init(node, gic_data[gic_cnt].domain); 1029 1030 gic_cnt++; 1031 return 0; 1032 } 1033 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1034 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1035 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1036 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1037 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1038 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1039 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1040 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1041 1042 #endif 1043 1044 #ifdef CONFIG_ACPI 1045 static phys_addr_t dist_phy_base, cpu_phy_base __initdata; 1046 1047 static int __init 1048 gic_acpi_parse_madt_cpu(struct acpi_subtable_header *header, 1049 const unsigned long end) 1050 { 1051 struct acpi_madt_generic_interrupt *processor; 1052 phys_addr_t gic_cpu_base; 1053 static int cpu_base_assigned; 1054 1055 processor = (struct acpi_madt_generic_interrupt *)header; 1056 1057 if (BAD_MADT_ENTRY(processor, end)) 1058 return -EINVAL; 1059 1060 /* 1061 * There is no support for non-banked GICv1/2 register in ACPI spec. 1062 * All CPU interface addresses have to be the same. 1063 */ 1064 gic_cpu_base = processor->base_address; 1065 if (cpu_base_assigned && gic_cpu_base != cpu_phy_base) 1066 return -EINVAL; 1067 1068 cpu_phy_base = gic_cpu_base; 1069 cpu_base_assigned = 1; 1070 return 0; 1071 } 1072 1073 static int __init 1074 gic_acpi_parse_madt_distributor(struct acpi_subtable_header *header, 1075 const unsigned long end) 1076 { 1077 struct acpi_madt_generic_distributor *dist; 1078 1079 dist = (struct acpi_madt_generic_distributor *)header; 1080 1081 if (BAD_MADT_ENTRY(dist, end)) 1082 return -EINVAL; 1083 1084 dist_phy_base = dist->base_address; 1085 return 0; 1086 } 1087 1088 int __init 1089 gic_v2_acpi_init(struct acpi_table_header *table) 1090 { 1091 void __iomem *cpu_base, *dist_base; 1092 int count; 1093 1094 /* Collect CPU base addresses */ 1095 count = acpi_parse_entries(ACPI_SIG_MADT, 1096 sizeof(struct acpi_table_madt), 1097 gic_acpi_parse_madt_cpu, table, 1098 ACPI_MADT_TYPE_GENERIC_INTERRUPT, 0); 1099 if (count <= 0) { 1100 pr_err("No valid GICC entries exist\n"); 1101 return -EINVAL; 1102 } 1103 1104 /* 1105 * Find distributor base address. We expect one distributor entry since 1106 * ACPI 5.1 spec neither support multi-GIC instances nor GIC cascade. 1107 */ 1108 count = acpi_parse_entries(ACPI_SIG_MADT, 1109 sizeof(struct acpi_table_madt), 1110 gic_acpi_parse_madt_distributor, table, 1111 ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 0); 1112 if (count <= 0) { 1113 pr_err("No valid GICD entries exist\n"); 1114 return -EINVAL; 1115 } else if (count > 1) { 1116 pr_err("More than one GICD entry detected\n"); 1117 return -EINVAL; 1118 } 1119 1120 cpu_base = ioremap(cpu_phy_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1121 if (!cpu_base) { 1122 pr_err("Unable to map GICC registers\n"); 1123 return -ENOMEM; 1124 } 1125 1126 dist_base = ioremap(dist_phy_base, ACPI_GICV2_DIST_MEM_SIZE); 1127 if (!dist_base) { 1128 pr_err("Unable to map GICD registers\n"); 1129 iounmap(cpu_base); 1130 return -ENOMEM; 1131 } 1132 1133 /* 1134 * Initialize zero GIC instance (no multi-GIC support). Also, set GIC 1135 * as default IRQ domain to allow for GSI registration and GSI to IRQ 1136 * number translation (see acpi_register_gsi() and acpi_gsi_to_irq()). 1137 */ 1138 gic_init_bases(0, -1, dist_base, cpu_base, 0, NULL); 1139 irq_set_default_host(gic_data[0].domain); 1140 1141 acpi_irq_model = ACPI_IRQ_MODEL_GIC; 1142 return 0; 1143 } 1144 #endif 1145