1 /* 2 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * Interrupt architecture for the GIC: 9 * 10 * o There is one Interrupt Distributor, which receives interrupts 11 * from system devices and sends them to the Interrupt Controllers. 12 * 13 * o There is one CPU Interface per CPU, which sends interrupts sent 14 * by the Distributor, and interrupts generated locally, to the 15 * associated CPU. The base address of the CPU interface is usually 16 * aliased so that the same address points to different chips depending 17 * on the CPU it is accessed from. 18 * 19 * Note that IRQs 0-31 are special - they are local to each CPU. 20 * As such, the enable set/clear, pending set/clear and active bit 21 * registers are banked per-cpu for these sources. 22 */ 23 #include <linux/init.h> 24 #include <linux/kernel.h> 25 #include <linux/err.h> 26 #include <linux/module.h> 27 #include <linux/list.h> 28 #include <linux/smp.h> 29 #include <linux/cpu.h> 30 #include <linux/cpu_pm.h> 31 #include <linux/cpumask.h> 32 #include <linux/io.h> 33 #include <linux/of.h> 34 #include <linux/of_address.h> 35 #include <linux/of_irq.h> 36 #include <linux/irqdomain.h> 37 #include <linux/interrupt.h> 38 #include <linux/percpu.h> 39 #include <linux/slab.h> 40 #include <linux/irqchip/chained_irq.h> 41 #include <linux/irqchip/arm-gic.h> 42 43 #include <asm/cputype.h> 44 #include <asm/irq.h> 45 #include <asm/exception.h> 46 #include <asm/smp_plat.h> 47 48 #include "irq-gic-common.h" 49 #include "irqchip.h" 50 51 union gic_base { 52 void __iomem *common_base; 53 void __percpu * __iomem *percpu_base; 54 }; 55 56 struct gic_chip_data { 57 union gic_base dist_base; 58 union gic_base cpu_base; 59 #ifdef CONFIG_CPU_PM 60 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 61 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 62 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 63 u32 __percpu *saved_ppi_enable; 64 u32 __percpu *saved_ppi_conf; 65 #endif 66 struct irq_domain *domain; 67 unsigned int gic_irqs; 68 #ifdef CONFIG_GIC_NON_BANKED 69 void __iomem *(*get_base)(union gic_base *); 70 #endif 71 }; 72 73 static DEFINE_RAW_SPINLOCK(irq_controller_lock); 74 75 /* 76 * The GIC mapping of CPU interfaces does not necessarily match 77 * the logical CPU numbering. Let's use a mapping as returned 78 * by the GIC itself. 79 */ 80 #define NR_GIC_CPU_IF 8 81 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 82 83 /* 84 * Supported arch specific GIC irq extension. 85 * Default make them NULL. 86 */ 87 struct irq_chip gic_arch_extn = { 88 .irq_eoi = NULL, 89 .irq_mask = NULL, 90 .irq_unmask = NULL, 91 .irq_retrigger = NULL, 92 .irq_set_type = NULL, 93 .irq_set_wake = NULL, 94 }; 95 96 #ifndef MAX_GIC_NR 97 #define MAX_GIC_NR 1 98 #endif 99 100 static struct gic_chip_data gic_data[MAX_GIC_NR] __read_mostly; 101 102 #ifdef CONFIG_GIC_NON_BANKED 103 static void __iomem *gic_get_percpu_base(union gic_base *base) 104 { 105 return raw_cpu_read(*base->percpu_base); 106 } 107 108 static void __iomem *gic_get_common_base(union gic_base *base) 109 { 110 return base->common_base; 111 } 112 113 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 114 { 115 return data->get_base(&data->dist_base); 116 } 117 118 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 119 { 120 return data->get_base(&data->cpu_base); 121 } 122 123 static inline void gic_set_base_accessor(struct gic_chip_data *data, 124 void __iomem *(*f)(union gic_base *)) 125 { 126 data->get_base = f; 127 } 128 #else 129 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 130 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 131 #define gic_set_base_accessor(d, f) 132 #endif 133 134 static inline void __iomem *gic_dist_base(struct irq_data *d) 135 { 136 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 137 return gic_data_dist_base(gic_data); 138 } 139 140 static inline void __iomem *gic_cpu_base(struct irq_data *d) 141 { 142 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 143 return gic_data_cpu_base(gic_data); 144 } 145 146 static inline unsigned int gic_irq(struct irq_data *d) 147 { 148 return d->hwirq; 149 } 150 151 /* 152 * Routines to acknowledge, disable and enable interrupts 153 */ 154 static void gic_poke_irq(struct irq_data *d, u32 offset) 155 { 156 u32 mask = 1 << (gic_irq(d) % 32); 157 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 158 } 159 160 static int gic_peek_irq(struct irq_data *d, u32 offset) 161 { 162 u32 mask = 1 << (gic_irq(d) % 32); 163 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 164 } 165 166 static void gic_mask_irq(struct irq_data *d) 167 { 168 unsigned long flags; 169 170 raw_spin_lock_irqsave(&irq_controller_lock, flags); 171 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 172 if (gic_arch_extn.irq_mask) 173 gic_arch_extn.irq_mask(d); 174 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 175 } 176 177 static void gic_unmask_irq(struct irq_data *d) 178 { 179 unsigned long flags; 180 181 raw_spin_lock_irqsave(&irq_controller_lock, flags); 182 if (gic_arch_extn.irq_unmask) 183 gic_arch_extn.irq_unmask(d); 184 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 185 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 186 } 187 188 static void gic_eoi_irq(struct irq_data *d) 189 { 190 if (gic_arch_extn.irq_eoi) { 191 raw_spin_lock(&irq_controller_lock); 192 gic_arch_extn.irq_eoi(d); 193 raw_spin_unlock(&irq_controller_lock); 194 } 195 196 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 197 } 198 199 static int gic_irq_set_irqchip_state(struct irq_data *d, 200 enum irqchip_irq_state which, bool val) 201 { 202 u32 reg; 203 204 switch (which) { 205 case IRQCHIP_STATE_PENDING: 206 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 207 break; 208 209 case IRQCHIP_STATE_ACTIVE: 210 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 211 break; 212 213 case IRQCHIP_STATE_MASKED: 214 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 215 break; 216 217 default: 218 return -EINVAL; 219 } 220 221 gic_poke_irq(d, reg); 222 return 0; 223 } 224 225 static int gic_irq_get_irqchip_state(struct irq_data *d, 226 enum irqchip_irq_state which, bool *val) 227 { 228 switch (which) { 229 case IRQCHIP_STATE_PENDING: 230 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 231 break; 232 233 case IRQCHIP_STATE_ACTIVE: 234 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 235 break; 236 237 case IRQCHIP_STATE_MASKED: 238 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 239 break; 240 241 default: 242 return -EINVAL; 243 } 244 245 return 0; 246 } 247 248 static int gic_set_type(struct irq_data *d, unsigned int type) 249 { 250 void __iomem *base = gic_dist_base(d); 251 unsigned int gicirq = gic_irq(d); 252 unsigned long flags; 253 int ret; 254 255 /* Interrupt configuration for SGIs can't be changed */ 256 if (gicirq < 16) 257 return -EINVAL; 258 259 /* SPIs have restrictions on the supported types */ 260 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 261 type != IRQ_TYPE_EDGE_RISING) 262 return -EINVAL; 263 264 raw_spin_lock_irqsave(&irq_controller_lock, flags); 265 266 if (gic_arch_extn.irq_set_type) 267 gic_arch_extn.irq_set_type(d, type); 268 269 ret = gic_configure_irq(gicirq, type, base, NULL); 270 271 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 272 273 return ret; 274 } 275 276 static int gic_retrigger(struct irq_data *d) 277 { 278 if (gic_arch_extn.irq_retrigger) 279 return gic_arch_extn.irq_retrigger(d); 280 281 /* the genirq layer expects 0 if we can't retrigger in hardware */ 282 return 0; 283 } 284 285 #ifdef CONFIG_SMP 286 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 287 bool force) 288 { 289 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 290 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 291 u32 val, mask, bit; 292 unsigned long flags; 293 294 if (!force) 295 cpu = cpumask_any_and(mask_val, cpu_online_mask); 296 else 297 cpu = cpumask_first(mask_val); 298 299 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 300 return -EINVAL; 301 302 raw_spin_lock_irqsave(&irq_controller_lock, flags); 303 mask = 0xff << shift; 304 bit = gic_cpu_map[cpu] << shift; 305 val = readl_relaxed(reg) & ~mask; 306 writel_relaxed(val | bit, reg); 307 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 308 309 return IRQ_SET_MASK_OK; 310 } 311 #endif 312 313 #ifdef CONFIG_PM 314 static int gic_set_wake(struct irq_data *d, unsigned int on) 315 { 316 int ret = -ENXIO; 317 318 if (gic_arch_extn.irq_set_wake) 319 ret = gic_arch_extn.irq_set_wake(d, on); 320 321 return ret; 322 } 323 324 #else 325 #define gic_set_wake NULL 326 #endif 327 328 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 329 { 330 u32 irqstat, irqnr; 331 struct gic_chip_data *gic = &gic_data[0]; 332 void __iomem *cpu_base = gic_data_cpu_base(gic); 333 334 do { 335 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 336 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 337 338 if (likely(irqnr > 15 && irqnr < 1021)) { 339 handle_domain_irq(gic->domain, irqnr, regs); 340 continue; 341 } 342 if (irqnr < 16) { 343 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 344 #ifdef CONFIG_SMP 345 handle_IPI(irqnr, regs); 346 #endif 347 continue; 348 } 349 break; 350 } while (1); 351 } 352 353 static void gic_handle_cascade_irq(unsigned int irq, struct irq_desc *desc) 354 { 355 struct gic_chip_data *chip_data = irq_get_handler_data(irq); 356 struct irq_chip *chip = irq_get_chip(irq); 357 unsigned int cascade_irq, gic_irq; 358 unsigned long status; 359 360 chained_irq_enter(chip, desc); 361 362 raw_spin_lock(&irq_controller_lock); 363 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 364 raw_spin_unlock(&irq_controller_lock); 365 366 gic_irq = (status & GICC_IAR_INT_ID_MASK); 367 if (gic_irq == GICC_INT_SPURIOUS) 368 goto out; 369 370 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 371 if (unlikely(gic_irq < 32 || gic_irq > 1020)) 372 handle_bad_irq(cascade_irq, desc); 373 else 374 generic_handle_irq(cascade_irq); 375 376 out: 377 chained_irq_exit(chip, desc); 378 } 379 380 static struct irq_chip gic_chip = { 381 .name = "GIC", 382 .irq_mask = gic_mask_irq, 383 .irq_unmask = gic_unmask_irq, 384 .irq_eoi = gic_eoi_irq, 385 .irq_set_type = gic_set_type, 386 .irq_retrigger = gic_retrigger, 387 #ifdef CONFIG_SMP 388 .irq_set_affinity = gic_set_affinity, 389 #endif 390 .irq_set_wake = gic_set_wake, 391 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 392 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 393 }; 394 395 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 396 { 397 if (gic_nr >= MAX_GIC_NR) 398 BUG(); 399 if (irq_set_handler_data(irq, &gic_data[gic_nr]) != 0) 400 BUG(); 401 irq_set_chained_handler(irq, gic_handle_cascade_irq); 402 } 403 404 static u8 gic_get_cpumask(struct gic_chip_data *gic) 405 { 406 void __iomem *base = gic_data_dist_base(gic); 407 u32 mask, i; 408 409 for (i = mask = 0; i < 32; i += 4) { 410 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 411 mask |= mask >> 16; 412 mask |= mask >> 8; 413 if (mask) 414 break; 415 } 416 417 if (!mask && num_possible_cpus() > 1) 418 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 419 420 return mask; 421 } 422 423 static void gic_cpu_if_up(void) 424 { 425 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 426 u32 bypass = 0; 427 428 /* 429 * Preserve bypass disable bits to be written back later 430 */ 431 bypass = readl(cpu_base + GIC_CPU_CTRL); 432 bypass &= GICC_DIS_BYPASS_MASK; 433 434 writel_relaxed(bypass | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 435 } 436 437 438 static void __init gic_dist_init(struct gic_chip_data *gic) 439 { 440 unsigned int i; 441 u32 cpumask; 442 unsigned int gic_irqs = gic->gic_irqs; 443 void __iomem *base = gic_data_dist_base(gic); 444 445 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 446 447 /* 448 * Set all global interrupts to this CPU only. 449 */ 450 cpumask = gic_get_cpumask(gic); 451 cpumask |= cpumask << 8; 452 cpumask |= cpumask << 16; 453 for (i = 32; i < gic_irqs; i += 4) 454 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 455 456 gic_dist_config(base, gic_irqs, NULL); 457 458 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 459 } 460 461 static void gic_cpu_init(struct gic_chip_data *gic) 462 { 463 void __iomem *dist_base = gic_data_dist_base(gic); 464 void __iomem *base = gic_data_cpu_base(gic); 465 unsigned int cpu_mask, cpu = smp_processor_id(); 466 int i; 467 468 /* 469 * Get what the GIC says our CPU mask is. 470 */ 471 BUG_ON(cpu >= NR_GIC_CPU_IF); 472 cpu_mask = gic_get_cpumask(gic); 473 gic_cpu_map[cpu] = cpu_mask; 474 475 /* 476 * Clear our mask from the other map entries in case they're 477 * still undefined. 478 */ 479 for (i = 0; i < NR_GIC_CPU_IF; i++) 480 if (i != cpu) 481 gic_cpu_map[i] &= ~cpu_mask; 482 483 gic_cpu_config(dist_base, NULL); 484 485 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 486 gic_cpu_if_up(); 487 } 488 489 void gic_cpu_if_down(void) 490 { 491 void __iomem *cpu_base = gic_data_cpu_base(&gic_data[0]); 492 u32 val = 0; 493 494 val = readl(cpu_base + GIC_CPU_CTRL); 495 val &= ~GICC_ENABLE; 496 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 497 } 498 499 #ifdef CONFIG_CPU_PM 500 /* 501 * Saves the GIC distributor registers during suspend or idle. Must be called 502 * with interrupts disabled but before powering down the GIC. After calling 503 * this function, no interrupts will be delivered by the GIC, and another 504 * platform-specific wakeup source must be enabled. 505 */ 506 static void gic_dist_save(unsigned int gic_nr) 507 { 508 unsigned int gic_irqs; 509 void __iomem *dist_base; 510 int i; 511 512 if (gic_nr >= MAX_GIC_NR) 513 BUG(); 514 515 gic_irqs = gic_data[gic_nr].gic_irqs; 516 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 517 518 if (!dist_base) 519 return; 520 521 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 522 gic_data[gic_nr].saved_spi_conf[i] = 523 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 524 525 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 526 gic_data[gic_nr].saved_spi_target[i] = 527 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 528 529 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 530 gic_data[gic_nr].saved_spi_enable[i] = 531 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 532 } 533 534 /* 535 * Restores the GIC distributor registers during resume or when coming out of 536 * idle. Must be called before enabling interrupts. If a level interrupt 537 * that occured while the GIC was suspended is still present, it will be 538 * handled normally, but any edge interrupts that occured will not be seen by 539 * the GIC and need to be handled by the platform-specific wakeup source. 540 */ 541 static void gic_dist_restore(unsigned int gic_nr) 542 { 543 unsigned int gic_irqs; 544 unsigned int i; 545 void __iomem *dist_base; 546 547 if (gic_nr >= MAX_GIC_NR) 548 BUG(); 549 550 gic_irqs = gic_data[gic_nr].gic_irqs; 551 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 552 553 if (!dist_base) 554 return; 555 556 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 557 558 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 559 writel_relaxed(gic_data[gic_nr].saved_spi_conf[i], 560 dist_base + GIC_DIST_CONFIG + i * 4); 561 562 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 563 writel_relaxed(GICD_INT_DEF_PRI_X4, 564 dist_base + GIC_DIST_PRI + i * 4); 565 566 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 567 writel_relaxed(gic_data[gic_nr].saved_spi_target[i], 568 dist_base + GIC_DIST_TARGET + i * 4); 569 570 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 571 writel_relaxed(gic_data[gic_nr].saved_spi_enable[i], 572 dist_base + GIC_DIST_ENABLE_SET + i * 4); 573 574 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 575 } 576 577 static void gic_cpu_save(unsigned int gic_nr) 578 { 579 int i; 580 u32 *ptr; 581 void __iomem *dist_base; 582 void __iomem *cpu_base; 583 584 if (gic_nr >= MAX_GIC_NR) 585 BUG(); 586 587 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 588 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 589 590 if (!dist_base || !cpu_base) 591 return; 592 593 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 594 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 595 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 596 597 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 598 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 599 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 600 601 } 602 603 static void gic_cpu_restore(unsigned int gic_nr) 604 { 605 int i; 606 u32 *ptr; 607 void __iomem *dist_base; 608 void __iomem *cpu_base; 609 610 if (gic_nr >= MAX_GIC_NR) 611 BUG(); 612 613 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 614 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 615 616 if (!dist_base || !cpu_base) 617 return; 618 619 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_enable); 620 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 621 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 622 623 ptr = raw_cpu_ptr(gic_data[gic_nr].saved_ppi_conf); 624 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 625 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 626 627 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 628 writel_relaxed(GICD_INT_DEF_PRI_X4, 629 dist_base + GIC_DIST_PRI + i * 4); 630 631 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 632 gic_cpu_if_up(); 633 } 634 635 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 636 { 637 int i; 638 639 for (i = 0; i < MAX_GIC_NR; i++) { 640 #ifdef CONFIG_GIC_NON_BANKED 641 /* Skip over unused GICs */ 642 if (!gic_data[i].get_base) 643 continue; 644 #endif 645 switch (cmd) { 646 case CPU_PM_ENTER: 647 gic_cpu_save(i); 648 break; 649 case CPU_PM_ENTER_FAILED: 650 case CPU_PM_EXIT: 651 gic_cpu_restore(i); 652 break; 653 case CPU_CLUSTER_PM_ENTER: 654 gic_dist_save(i); 655 break; 656 case CPU_CLUSTER_PM_ENTER_FAILED: 657 case CPU_CLUSTER_PM_EXIT: 658 gic_dist_restore(i); 659 break; 660 } 661 } 662 663 return NOTIFY_OK; 664 } 665 666 static struct notifier_block gic_notifier_block = { 667 .notifier_call = gic_notifier, 668 }; 669 670 static void __init gic_pm_init(struct gic_chip_data *gic) 671 { 672 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 673 sizeof(u32)); 674 BUG_ON(!gic->saved_ppi_enable); 675 676 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 677 sizeof(u32)); 678 BUG_ON(!gic->saved_ppi_conf); 679 680 if (gic == &gic_data[0]) 681 cpu_pm_register_notifier(&gic_notifier_block); 682 } 683 #else 684 static void __init gic_pm_init(struct gic_chip_data *gic) 685 { 686 } 687 #endif 688 689 #ifdef CONFIG_SMP 690 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 691 { 692 int cpu; 693 unsigned long flags, map = 0; 694 695 raw_spin_lock_irqsave(&irq_controller_lock, flags); 696 697 /* Convert our logical CPU mask into a physical one. */ 698 for_each_cpu(cpu, mask) 699 map |= gic_cpu_map[cpu]; 700 701 /* 702 * Ensure that stores to Normal memory are visible to the 703 * other CPUs before they observe us issuing the IPI. 704 */ 705 dmb(ishst); 706 707 /* this always happens on GIC0 */ 708 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 709 710 raw_spin_unlock_irqrestore(&irq_controller_lock, flags); 711 } 712 #endif 713 714 #ifdef CONFIG_BL_SWITCHER 715 /* 716 * gic_send_sgi - send a SGI directly to given CPU interface number 717 * 718 * cpu_id: the ID for the destination CPU interface 719 * irq: the IPI number to send a SGI for 720 */ 721 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 722 { 723 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 724 cpu_id = 1 << cpu_id; 725 /* this always happens on GIC0 */ 726 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 727 } 728 729 /* 730 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 731 * 732 * @cpu: the logical CPU number to get the GIC ID for. 733 * 734 * Return the CPU interface ID for the given logical CPU number, 735 * or -1 if the CPU number is too large or the interface ID is 736 * unknown (more than one bit set). 737 */ 738 int gic_get_cpu_id(unsigned int cpu) 739 { 740 unsigned int cpu_bit; 741 742 if (cpu >= NR_GIC_CPU_IF) 743 return -1; 744 cpu_bit = gic_cpu_map[cpu]; 745 if (cpu_bit & (cpu_bit - 1)) 746 return -1; 747 return __ffs(cpu_bit); 748 } 749 750 /* 751 * gic_migrate_target - migrate IRQs to another CPU interface 752 * 753 * @new_cpu_id: the CPU target ID to migrate IRQs to 754 * 755 * Migrate all peripheral interrupts with a target matching the current CPU 756 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 757 * is also updated. Targets to other CPU interfaces are unchanged. 758 * This must be called with IRQs locally disabled. 759 */ 760 void gic_migrate_target(unsigned int new_cpu_id) 761 { 762 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 763 void __iomem *dist_base; 764 int i, ror_val, cpu = smp_processor_id(); 765 u32 val, cur_target_mask, active_mask; 766 767 if (gic_nr >= MAX_GIC_NR) 768 BUG(); 769 770 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 771 if (!dist_base) 772 return; 773 gic_irqs = gic_data[gic_nr].gic_irqs; 774 775 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 776 cur_target_mask = 0x01010101 << cur_cpu_id; 777 ror_val = (cur_cpu_id - new_cpu_id) & 31; 778 779 raw_spin_lock(&irq_controller_lock); 780 781 /* Update the target interface for this logical CPU */ 782 gic_cpu_map[cpu] = 1 << new_cpu_id; 783 784 /* 785 * Find all the peripheral interrupts targetting the current 786 * CPU interface and migrate them to the new CPU interface. 787 * We skip DIST_TARGET 0 to 7 as they are read-only. 788 */ 789 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 790 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 791 active_mask = val & cur_target_mask; 792 if (active_mask) { 793 val &= ~active_mask; 794 val |= ror32(active_mask, ror_val); 795 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 796 } 797 } 798 799 raw_spin_unlock(&irq_controller_lock); 800 801 /* 802 * Now let's migrate and clear any potential SGIs that might be 803 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 804 * is a banked register, we can only forward the SGI using 805 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 806 * doesn't use that information anyway. 807 * 808 * For the same reason we do not adjust SGI source information 809 * for previously sent SGIs by us to other CPUs either. 810 */ 811 for (i = 0; i < 16; i += 4) { 812 int j; 813 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 814 if (!val) 815 continue; 816 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 817 for (j = i; j < i + 4; j++) { 818 if (val & 0xff) 819 writel_relaxed((1 << (new_cpu_id + 16)) | j, 820 dist_base + GIC_DIST_SOFTINT); 821 val >>= 8; 822 } 823 } 824 } 825 826 /* 827 * gic_get_sgir_physaddr - get the physical address for the SGI register 828 * 829 * REturn the physical address of the SGI register to be used 830 * by some early assembly code when the kernel is not yet available. 831 */ 832 static unsigned long gic_dist_physaddr; 833 834 unsigned long gic_get_sgir_physaddr(void) 835 { 836 if (!gic_dist_physaddr) 837 return 0; 838 return gic_dist_physaddr + GIC_DIST_SOFTINT; 839 } 840 841 void __init gic_init_physaddr(struct device_node *node) 842 { 843 struct resource res; 844 if (of_address_to_resource(node, 0, &res) == 0) { 845 gic_dist_physaddr = res.start; 846 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 847 } 848 } 849 850 #else 851 #define gic_init_physaddr(node) do { } while (0) 852 #endif 853 854 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 855 irq_hw_number_t hw) 856 { 857 if (hw < 32) { 858 irq_set_percpu_devid(irq); 859 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 860 handle_percpu_devid_irq, NULL, NULL); 861 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 862 } else { 863 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 864 handle_fasteoi_irq, NULL, NULL); 865 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 866 } 867 return 0; 868 } 869 870 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 871 { 872 } 873 874 static int gic_irq_domain_xlate(struct irq_domain *d, 875 struct device_node *controller, 876 const u32 *intspec, unsigned int intsize, 877 unsigned long *out_hwirq, unsigned int *out_type) 878 { 879 unsigned long ret = 0; 880 881 if (d->of_node != controller) 882 return -EINVAL; 883 if (intsize < 3) 884 return -EINVAL; 885 886 /* Get the interrupt number and add 16 to skip over SGIs */ 887 *out_hwirq = intspec[1] + 16; 888 889 /* For SPIs, we need to add 16 more to get the GIC irq ID number */ 890 if (!intspec[0]) 891 *out_hwirq += 16; 892 893 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 894 895 return ret; 896 } 897 898 #ifdef CONFIG_SMP 899 static int gic_secondary_init(struct notifier_block *nfb, unsigned long action, 900 void *hcpu) 901 { 902 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 903 gic_cpu_init(&gic_data[0]); 904 return NOTIFY_OK; 905 } 906 907 /* 908 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 909 * priority because the GIC needs to be up before the ARM generic timers. 910 */ 911 static struct notifier_block gic_cpu_notifier = { 912 .notifier_call = gic_secondary_init, 913 .priority = 100, 914 }; 915 #endif 916 917 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 918 unsigned int nr_irqs, void *arg) 919 { 920 int i, ret; 921 irq_hw_number_t hwirq; 922 unsigned int type = IRQ_TYPE_NONE; 923 struct of_phandle_args *irq_data = arg; 924 925 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 926 irq_data->args_count, &hwirq, &type); 927 if (ret) 928 return ret; 929 930 for (i = 0; i < nr_irqs; i++) 931 gic_irq_domain_map(domain, virq + i, hwirq + i); 932 933 return 0; 934 } 935 936 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 937 .xlate = gic_irq_domain_xlate, 938 .alloc = gic_irq_domain_alloc, 939 .free = irq_domain_free_irqs_top, 940 }; 941 942 static const struct irq_domain_ops gic_irq_domain_ops = { 943 .map = gic_irq_domain_map, 944 .unmap = gic_irq_domain_unmap, 945 .xlate = gic_irq_domain_xlate, 946 }; 947 948 void gic_set_irqchip_flags(unsigned long flags) 949 { 950 gic_chip.flags |= flags; 951 } 952 953 void __init gic_init_bases(unsigned int gic_nr, int irq_start, 954 void __iomem *dist_base, void __iomem *cpu_base, 955 u32 percpu_offset, struct device_node *node) 956 { 957 irq_hw_number_t hwirq_base; 958 struct gic_chip_data *gic; 959 int gic_irqs, irq_base, i; 960 961 BUG_ON(gic_nr >= MAX_GIC_NR); 962 963 gic = &gic_data[gic_nr]; 964 #ifdef CONFIG_GIC_NON_BANKED 965 if (percpu_offset) { /* Frankein-GIC without banked registers... */ 966 unsigned int cpu; 967 968 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 969 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 970 if (WARN_ON(!gic->dist_base.percpu_base || 971 !gic->cpu_base.percpu_base)) { 972 free_percpu(gic->dist_base.percpu_base); 973 free_percpu(gic->cpu_base.percpu_base); 974 return; 975 } 976 977 for_each_possible_cpu(cpu) { 978 u32 mpidr = cpu_logical_map(cpu); 979 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 980 unsigned long offset = percpu_offset * core_id; 981 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = dist_base + offset; 982 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = cpu_base + offset; 983 } 984 985 gic_set_base_accessor(gic, gic_get_percpu_base); 986 } else 987 #endif 988 { /* Normal, sane GIC... */ 989 WARN(percpu_offset, 990 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 991 percpu_offset); 992 gic->dist_base.common_base = dist_base; 993 gic->cpu_base.common_base = cpu_base; 994 gic_set_base_accessor(gic, gic_get_common_base); 995 } 996 997 /* 998 * Initialize the CPU interface map to all CPUs. 999 * It will be refined as each CPU probes its ID. 1000 */ 1001 for (i = 0; i < NR_GIC_CPU_IF; i++) 1002 gic_cpu_map[i] = 0xff; 1003 1004 /* 1005 * Find out how many interrupts are supported. 1006 * The GIC only supports up to 1020 interrupt sources. 1007 */ 1008 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1009 gic_irqs = (gic_irqs + 1) * 32; 1010 if (gic_irqs > 1020) 1011 gic_irqs = 1020; 1012 gic->gic_irqs = gic_irqs; 1013 1014 if (node) { /* DT case */ 1015 gic->domain = irq_domain_add_linear(node, gic_irqs, 1016 &gic_irq_domain_hierarchy_ops, 1017 gic); 1018 } else { /* Non-DT case */ 1019 /* 1020 * For primary GICs, skip over SGIs. 1021 * For secondary GICs, skip over PPIs, too. 1022 */ 1023 if (gic_nr == 0 && (irq_start & 31) > 0) { 1024 hwirq_base = 16; 1025 if (irq_start != -1) 1026 irq_start = (irq_start & ~31) + 16; 1027 } else { 1028 hwirq_base = 32; 1029 } 1030 1031 gic_irqs -= hwirq_base; /* calculate # of irqs to allocate */ 1032 1033 irq_base = irq_alloc_descs(irq_start, 16, gic_irqs, 1034 numa_node_id()); 1035 if (IS_ERR_VALUE(irq_base)) { 1036 WARN(1, "Cannot allocate irq_descs @ IRQ%d, assuming pre-allocated\n", 1037 irq_start); 1038 irq_base = irq_start; 1039 } 1040 1041 gic->domain = irq_domain_add_legacy(node, gic_irqs, irq_base, 1042 hwirq_base, &gic_irq_domain_ops, gic); 1043 } 1044 1045 if (WARN_ON(!gic->domain)) 1046 return; 1047 1048 if (gic_nr == 0) { 1049 #ifdef CONFIG_SMP 1050 set_smp_cross_call(gic_raise_softirq); 1051 register_cpu_notifier(&gic_cpu_notifier); 1052 #endif 1053 set_handle_irq(gic_handle_irq); 1054 } 1055 1056 gic_chip.flags |= gic_arch_extn.flags; 1057 gic_dist_init(gic); 1058 gic_cpu_init(gic); 1059 gic_pm_init(gic); 1060 } 1061 1062 #ifdef CONFIG_OF 1063 static int gic_cnt __initdata; 1064 1065 static int __init 1066 gic_of_init(struct device_node *node, struct device_node *parent) 1067 { 1068 void __iomem *cpu_base; 1069 void __iomem *dist_base; 1070 u32 percpu_offset; 1071 int irq; 1072 1073 if (WARN_ON(!node)) 1074 return -ENODEV; 1075 1076 dist_base = of_iomap(node, 0); 1077 WARN(!dist_base, "unable to map gic dist registers\n"); 1078 1079 cpu_base = of_iomap(node, 1); 1080 WARN(!cpu_base, "unable to map gic cpu registers\n"); 1081 1082 if (of_property_read_u32(node, "cpu-offset", &percpu_offset)) 1083 percpu_offset = 0; 1084 1085 gic_init_bases(gic_cnt, -1, dist_base, cpu_base, percpu_offset, node); 1086 if (!gic_cnt) 1087 gic_init_physaddr(node); 1088 1089 if (parent) { 1090 irq = irq_of_parse_and_map(node, 0); 1091 gic_cascade_irq(gic_cnt, irq); 1092 } 1093 1094 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1095 gicv2m_of_init(node, gic_data[gic_cnt].domain); 1096 1097 gic_cnt++; 1098 return 0; 1099 } 1100 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1101 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1102 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1103 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1104 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1105 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1106 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1107 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1108 1109 #endif 1110