1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 4 * 5 * Interrupt architecture for the GIC: 6 * 7 * o There is one Interrupt Distributor, which receives interrupts 8 * from system devices and sends them to the Interrupt Controllers. 9 * 10 * o There is one CPU Interface per CPU, which sends interrupts sent 11 * by the Distributor, and interrupts generated locally, to the 12 * associated CPU. The base address of the CPU interface is usually 13 * aliased so that the same address points to different chips depending 14 * on the CPU it is accessed from. 15 * 16 * Note that IRQs 0-31 are special - they are local to each CPU. 17 * As such, the enable set/clear, pending set/clear and active bit 18 * registers are banked per-cpu for these sources. 19 */ 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/err.h> 23 #include <linux/module.h> 24 #include <linux/list.h> 25 #include <linux/smp.h> 26 #include <linux/cpu.h> 27 #include <linux/cpu_pm.h> 28 #include <linux/cpumask.h> 29 #include <linux/io.h> 30 #include <linux/of.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/acpi.h> 34 #include <linux/irqdomain.h> 35 #include <linux/interrupt.h> 36 #include <linux/percpu.h> 37 #include <linux/slab.h> 38 #include <linux/irqchip.h> 39 #include <linux/irqchip/chained_irq.h> 40 #include <linux/irqchip/arm-gic.h> 41 42 #include <asm/cputype.h> 43 #include <asm/irq.h> 44 #include <asm/exception.h> 45 #include <asm/smp_plat.h> 46 #include <asm/virt.h> 47 48 #include "irq-gic-common.h" 49 50 #ifdef CONFIG_ARM64 51 #include <asm/cpufeature.h> 52 53 static void gic_check_cpu_features(void) 54 { 55 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), 56 TAINT_CPU_OUT_OF_SPEC, 57 "GICv3 system registers enabled, broken firmware!\n"); 58 } 59 #else 60 #define gic_check_cpu_features() do { } while(0) 61 #endif 62 63 union gic_base { 64 void __iomem *common_base; 65 void __percpu * __iomem *percpu_base; 66 }; 67 68 struct gic_chip_data { 69 struct irq_chip chip; 70 union gic_base dist_base; 71 union gic_base cpu_base; 72 void __iomem *raw_dist_base; 73 void __iomem *raw_cpu_base; 74 u32 percpu_offset; 75 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 77 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 78 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 79 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 80 u32 __percpu *saved_ppi_enable; 81 u32 __percpu *saved_ppi_active; 82 u32 __percpu *saved_ppi_conf; 83 #endif 84 struct irq_domain *domain; 85 unsigned int gic_irqs; 86 #ifdef CONFIG_GIC_NON_BANKED 87 void __iomem *(*get_base)(union gic_base *); 88 #endif 89 }; 90 91 #ifdef CONFIG_BL_SWITCHER 92 93 static DEFINE_RAW_SPINLOCK(cpu_map_lock); 94 95 #define gic_lock_irqsave(f) \ 96 raw_spin_lock_irqsave(&cpu_map_lock, (f)) 97 #define gic_unlock_irqrestore(f) \ 98 raw_spin_unlock_irqrestore(&cpu_map_lock, (f)) 99 100 #define gic_lock() raw_spin_lock(&cpu_map_lock) 101 #define gic_unlock() raw_spin_unlock(&cpu_map_lock) 102 103 #else 104 105 #define gic_lock_irqsave(f) do { (void)(f); } while(0) 106 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0) 107 108 #define gic_lock() do { } while(0) 109 #define gic_unlock() do { } while(0) 110 111 #endif 112 113 /* 114 * The GIC mapping of CPU interfaces does not necessarily match 115 * the logical CPU numbering. Let's use a mapping as returned 116 * by the GIC itself. 117 */ 118 #define NR_GIC_CPU_IF 8 119 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 120 121 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 122 123 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; 124 125 static struct gic_kvm_info gic_v2_kvm_info; 126 127 #ifdef CONFIG_GIC_NON_BANKED 128 static void __iomem *gic_get_percpu_base(union gic_base *base) 129 { 130 return raw_cpu_read(*base->percpu_base); 131 } 132 133 static void __iomem *gic_get_common_base(union gic_base *base) 134 { 135 return base->common_base; 136 } 137 138 static inline void __iomem *gic_data_dist_base(struct gic_chip_data *data) 139 { 140 return data->get_base(&data->dist_base); 141 } 142 143 static inline void __iomem *gic_data_cpu_base(struct gic_chip_data *data) 144 { 145 return data->get_base(&data->cpu_base); 146 } 147 148 static inline void gic_set_base_accessor(struct gic_chip_data *data, 149 void __iomem *(*f)(union gic_base *)) 150 { 151 data->get_base = f; 152 } 153 #else 154 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 155 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 156 #define gic_set_base_accessor(d, f) 157 #endif 158 159 static inline void __iomem *gic_dist_base(struct irq_data *d) 160 { 161 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 162 return gic_data_dist_base(gic_data); 163 } 164 165 static inline void __iomem *gic_cpu_base(struct irq_data *d) 166 { 167 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 168 return gic_data_cpu_base(gic_data); 169 } 170 171 static inline unsigned int gic_irq(struct irq_data *d) 172 { 173 return d->hwirq; 174 } 175 176 static inline bool cascading_gic_irq(struct irq_data *d) 177 { 178 void *data = irq_data_get_irq_handler_data(d); 179 180 /* 181 * If handler_data is set, this is a cascading interrupt, and 182 * it cannot possibly be forwarded. 183 */ 184 return data != NULL; 185 } 186 187 /* 188 * Routines to acknowledge, disable and enable interrupts 189 */ 190 static void gic_poke_irq(struct irq_data *d, u32 offset) 191 { 192 u32 mask = 1 << (gic_irq(d) % 32); 193 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 194 } 195 196 static int gic_peek_irq(struct irq_data *d, u32 offset) 197 { 198 u32 mask = 1 << (gic_irq(d) % 32); 199 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 200 } 201 202 static void gic_mask_irq(struct irq_data *d) 203 { 204 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 205 } 206 207 static void gic_eoimode1_mask_irq(struct irq_data *d) 208 { 209 gic_mask_irq(d); 210 /* 211 * When masking a forwarded interrupt, make sure it is 212 * deactivated as well. 213 * 214 * This ensures that an interrupt that is getting 215 * disabled/masked will not get "stuck", because there is 216 * noone to deactivate it (guest is being terminated). 217 */ 218 if (irqd_is_forwarded_to_vcpu(d)) 219 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); 220 } 221 222 static void gic_unmask_irq(struct irq_data *d) 223 { 224 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 225 } 226 227 static void gic_eoi_irq(struct irq_data *d) 228 { 229 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_EOI); 230 } 231 232 static void gic_eoimode1_eoi_irq(struct irq_data *d) 233 { 234 /* Do not deactivate an IRQ forwarded to a vcpu. */ 235 if (irqd_is_forwarded_to_vcpu(d)) 236 return; 237 238 writel_relaxed(gic_irq(d), gic_cpu_base(d) + GIC_CPU_DEACTIVATE); 239 } 240 241 static int gic_irq_set_irqchip_state(struct irq_data *d, 242 enum irqchip_irq_state which, bool val) 243 { 244 u32 reg; 245 246 switch (which) { 247 case IRQCHIP_STATE_PENDING: 248 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 249 break; 250 251 case IRQCHIP_STATE_ACTIVE: 252 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 253 break; 254 255 case IRQCHIP_STATE_MASKED: 256 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 257 break; 258 259 default: 260 return -EINVAL; 261 } 262 263 gic_poke_irq(d, reg); 264 return 0; 265 } 266 267 static int gic_irq_get_irqchip_state(struct irq_data *d, 268 enum irqchip_irq_state which, bool *val) 269 { 270 switch (which) { 271 case IRQCHIP_STATE_PENDING: 272 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 273 break; 274 275 case IRQCHIP_STATE_ACTIVE: 276 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 277 break; 278 279 case IRQCHIP_STATE_MASKED: 280 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 281 break; 282 283 default: 284 return -EINVAL; 285 } 286 287 return 0; 288 } 289 290 static int gic_set_type(struct irq_data *d, unsigned int type) 291 { 292 void __iomem *base = gic_dist_base(d); 293 unsigned int gicirq = gic_irq(d); 294 295 /* Interrupt configuration for SGIs can't be changed */ 296 if (gicirq < 16) 297 return -EINVAL; 298 299 /* SPIs have restrictions on the supported types */ 300 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 301 type != IRQ_TYPE_EDGE_RISING) 302 return -EINVAL; 303 304 return gic_configure_irq(gicirq, type, base, NULL); 305 } 306 307 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 308 { 309 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ 310 if (cascading_gic_irq(d)) 311 return -EINVAL; 312 313 if (vcpu) 314 irqd_set_forwarded_to_vcpu(d); 315 else 316 irqd_clr_forwarded_to_vcpu(d); 317 return 0; 318 } 319 320 #ifdef CONFIG_SMP 321 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 322 bool force) 323 { 324 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3); 325 unsigned int cpu, shift = (gic_irq(d) % 4) * 8; 326 u32 val, mask, bit; 327 unsigned long flags; 328 329 if (!force) 330 cpu = cpumask_any_and(mask_val, cpu_online_mask); 331 else 332 cpu = cpumask_first(mask_val); 333 334 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 335 return -EINVAL; 336 337 gic_lock_irqsave(flags); 338 mask = 0xff << shift; 339 bit = gic_cpu_map[cpu] << shift; 340 val = readl_relaxed(reg) & ~mask; 341 writel_relaxed(val | bit, reg); 342 gic_unlock_irqrestore(flags); 343 344 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 345 346 return IRQ_SET_MASK_OK_DONE; 347 } 348 #endif 349 350 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 351 { 352 u32 irqstat, irqnr; 353 struct gic_chip_data *gic = &gic_data[0]; 354 void __iomem *cpu_base = gic_data_cpu_base(gic); 355 356 do { 357 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 358 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 359 360 if (likely(irqnr > 15 && irqnr < 1020)) { 361 if (static_branch_likely(&supports_deactivate_key)) 362 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 363 isb(); 364 handle_domain_irq(gic->domain, irqnr, regs); 365 continue; 366 } 367 if (irqnr < 16) { 368 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 369 if (static_branch_likely(&supports_deactivate_key)) 370 writel_relaxed(irqstat, cpu_base + GIC_CPU_DEACTIVATE); 371 #ifdef CONFIG_SMP 372 /* 373 * Ensure any shared data written by the CPU sending 374 * the IPI is read after we've read the ACK register 375 * on the GIC. 376 * 377 * Pairs with the write barrier in gic_raise_softirq 378 */ 379 smp_rmb(); 380 handle_IPI(irqnr, regs); 381 #endif 382 continue; 383 } 384 break; 385 } while (1); 386 } 387 388 static void gic_handle_cascade_irq(struct irq_desc *desc) 389 { 390 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); 391 struct irq_chip *chip = irq_desc_get_chip(desc); 392 unsigned int cascade_irq, gic_irq; 393 unsigned long status; 394 395 chained_irq_enter(chip, desc); 396 397 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 398 399 gic_irq = (status & GICC_IAR_INT_ID_MASK); 400 if (gic_irq == GICC_INT_SPURIOUS) 401 goto out; 402 403 cascade_irq = irq_find_mapping(chip_data->domain, gic_irq); 404 if (unlikely(gic_irq < 32 || gic_irq > 1020)) { 405 handle_bad_irq(desc); 406 } else { 407 isb(); 408 generic_handle_irq(cascade_irq); 409 } 410 411 out: 412 chained_irq_exit(chip, desc); 413 } 414 415 static const struct irq_chip gic_chip = { 416 .irq_mask = gic_mask_irq, 417 .irq_unmask = gic_unmask_irq, 418 .irq_eoi = gic_eoi_irq, 419 .irq_set_type = gic_set_type, 420 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 421 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 422 .flags = IRQCHIP_SET_TYPE_MASKED | 423 IRQCHIP_SKIP_SET_WAKE | 424 IRQCHIP_MASK_ON_SUSPEND, 425 }; 426 427 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 428 { 429 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 430 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, 431 &gic_data[gic_nr]); 432 } 433 434 static u8 gic_get_cpumask(struct gic_chip_data *gic) 435 { 436 void __iomem *base = gic_data_dist_base(gic); 437 u32 mask, i; 438 439 for (i = mask = 0; i < 32; i += 4) { 440 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 441 mask |= mask >> 16; 442 mask |= mask >> 8; 443 if (mask) 444 break; 445 } 446 447 if (!mask && num_possible_cpus() > 1) 448 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 449 450 return mask; 451 } 452 453 static bool gic_check_gicv2(void __iomem *base) 454 { 455 u32 val = readl_relaxed(base + GIC_CPU_IDENT); 456 return (val & 0xff0fff) == 0x02043B; 457 } 458 459 static void gic_cpu_if_up(struct gic_chip_data *gic) 460 { 461 void __iomem *cpu_base = gic_data_cpu_base(gic); 462 u32 bypass = 0; 463 u32 mode = 0; 464 int i; 465 466 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) 467 mode = GIC_CPU_CTRL_EOImodeNS; 468 469 if (gic_check_gicv2(cpu_base)) 470 for (i = 0; i < 4; i++) 471 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4); 472 473 /* 474 * Preserve bypass disable bits to be written back later 475 */ 476 bypass = readl(cpu_base + GIC_CPU_CTRL); 477 bypass &= GICC_DIS_BYPASS_MASK; 478 479 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 480 } 481 482 483 static void gic_dist_init(struct gic_chip_data *gic) 484 { 485 unsigned int i; 486 u32 cpumask; 487 unsigned int gic_irqs = gic->gic_irqs; 488 void __iomem *base = gic_data_dist_base(gic); 489 490 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 491 492 /* 493 * Set all global interrupts to this CPU only. 494 */ 495 cpumask = gic_get_cpumask(gic); 496 cpumask |= cpumask << 8; 497 cpumask |= cpumask << 16; 498 for (i = 32; i < gic_irqs; i += 4) 499 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 500 501 gic_dist_config(base, gic_irqs, NULL); 502 503 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 504 } 505 506 static int gic_cpu_init(struct gic_chip_data *gic) 507 { 508 void __iomem *dist_base = gic_data_dist_base(gic); 509 void __iomem *base = gic_data_cpu_base(gic); 510 unsigned int cpu_mask, cpu = smp_processor_id(); 511 int i; 512 513 /* 514 * Setting up the CPU map is only relevant for the primary GIC 515 * because any nested/secondary GICs do not directly interface 516 * with the CPU(s). 517 */ 518 if (gic == &gic_data[0]) { 519 /* 520 * Get what the GIC says our CPU mask is. 521 */ 522 if (WARN_ON(cpu >= NR_GIC_CPU_IF)) 523 return -EINVAL; 524 525 gic_check_cpu_features(); 526 cpu_mask = gic_get_cpumask(gic); 527 gic_cpu_map[cpu] = cpu_mask; 528 529 /* 530 * Clear our mask from the other map entries in case they're 531 * still undefined. 532 */ 533 for (i = 0; i < NR_GIC_CPU_IF; i++) 534 if (i != cpu) 535 gic_cpu_map[i] &= ~cpu_mask; 536 } 537 538 gic_cpu_config(dist_base, NULL); 539 540 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 541 gic_cpu_if_up(gic); 542 543 return 0; 544 } 545 546 int gic_cpu_if_down(unsigned int gic_nr) 547 { 548 void __iomem *cpu_base; 549 u32 val = 0; 550 551 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) 552 return -EINVAL; 553 554 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 555 val = readl(cpu_base + GIC_CPU_CTRL); 556 val &= ~GICC_ENABLE; 557 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 558 559 return 0; 560 } 561 562 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 563 /* 564 * Saves the GIC distributor registers during suspend or idle. Must be called 565 * with interrupts disabled but before powering down the GIC. After calling 566 * this function, no interrupts will be delivered by the GIC, and another 567 * platform-specific wakeup source must be enabled. 568 */ 569 void gic_dist_save(struct gic_chip_data *gic) 570 { 571 unsigned int gic_irqs; 572 void __iomem *dist_base; 573 int i; 574 575 if (WARN_ON(!gic)) 576 return; 577 578 gic_irqs = gic->gic_irqs; 579 dist_base = gic_data_dist_base(gic); 580 581 if (!dist_base) 582 return; 583 584 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 585 gic->saved_spi_conf[i] = 586 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 587 588 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 589 gic->saved_spi_target[i] = 590 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 591 592 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 593 gic->saved_spi_enable[i] = 594 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 595 596 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 597 gic->saved_spi_active[i] = 598 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 599 } 600 601 /* 602 * Restores the GIC distributor registers during resume or when coming out of 603 * idle. Must be called before enabling interrupts. If a level interrupt 604 * that occurred while the GIC was suspended is still present, it will be 605 * handled normally, but any edge interrupts that occurred will not be seen by 606 * the GIC and need to be handled by the platform-specific wakeup source. 607 */ 608 void gic_dist_restore(struct gic_chip_data *gic) 609 { 610 unsigned int gic_irqs; 611 unsigned int i; 612 void __iomem *dist_base; 613 614 if (WARN_ON(!gic)) 615 return; 616 617 gic_irqs = gic->gic_irqs; 618 dist_base = gic_data_dist_base(gic); 619 620 if (!dist_base) 621 return; 622 623 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 624 625 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 626 writel_relaxed(gic->saved_spi_conf[i], 627 dist_base + GIC_DIST_CONFIG + i * 4); 628 629 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 630 writel_relaxed(GICD_INT_DEF_PRI_X4, 631 dist_base + GIC_DIST_PRI + i * 4); 632 633 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 634 writel_relaxed(gic->saved_spi_target[i], 635 dist_base + GIC_DIST_TARGET + i * 4); 636 637 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 638 writel_relaxed(GICD_INT_EN_CLR_X32, 639 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 640 writel_relaxed(gic->saved_spi_enable[i], 641 dist_base + GIC_DIST_ENABLE_SET + i * 4); 642 } 643 644 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 645 writel_relaxed(GICD_INT_EN_CLR_X32, 646 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 647 writel_relaxed(gic->saved_spi_active[i], 648 dist_base + GIC_DIST_ACTIVE_SET + i * 4); 649 } 650 651 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 652 } 653 654 void gic_cpu_save(struct gic_chip_data *gic) 655 { 656 int i; 657 u32 *ptr; 658 void __iomem *dist_base; 659 void __iomem *cpu_base; 660 661 if (WARN_ON(!gic)) 662 return; 663 664 dist_base = gic_data_dist_base(gic); 665 cpu_base = gic_data_cpu_base(gic); 666 667 if (!dist_base || !cpu_base) 668 return; 669 670 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 671 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 672 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 673 674 ptr = raw_cpu_ptr(gic->saved_ppi_active); 675 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 676 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 677 678 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 679 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 680 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 681 682 } 683 684 void gic_cpu_restore(struct gic_chip_data *gic) 685 { 686 int i; 687 u32 *ptr; 688 void __iomem *dist_base; 689 void __iomem *cpu_base; 690 691 if (WARN_ON(!gic)) 692 return; 693 694 dist_base = gic_data_dist_base(gic); 695 cpu_base = gic_data_cpu_base(gic); 696 697 if (!dist_base || !cpu_base) 698 return; 699 700 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 701 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 702 writel_relaxed(GICD_INT_EN_CLR_X32, 703 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 704 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 705 } 706 707 ptr = raw_cpu_ptr(gic->saved_ppi_active); 708 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 709 writel_relaxed(GICD_INT_EN_CLR_X32, 710 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 711 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); 712 } 713 714 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 715 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 716 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 717 718 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 719 writel_relaxed(GICD_INT_DEF_PRI_X4, 720 dist_base + GIC_DIST_PRI + i * 4); 721 722 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 723 gic_cpu_if_up(gic); 724 } 725 726 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 727 { 728 int i; 729 730 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { 731 #ifdef CONFIG_GIC_NON_BANKED 732 /* Skip over unused GICs */ 733 if (!gic_data[i].get_base) 734 continue; 735 #endif 736 switch (cmd) { 737 case CPU_PM_ENTER: 738 gic_cpu_save(&gic_data[i]); 739 break; 740 case CPU_PM_ENTER_FAILED: 741 case CPU_PM_EXIT: 742 gic_cpu_restore(&gic_data[i]); 743 break; 744 case CPU_CLUSTER_PM_ENTER: 745 gic_dist_save(&gic_data[i]); 746 break; 747 case CPU_CLUSTER_PM_ENTER_FAILED: 748 case CPU_CLUSTER_PM_EXIT: 749 gic_dist_restore(&gic_data[i]); 750 break; 751 } 752 } 753 754 return NOTIFY_OK; 755 } 756 757 static struct notifier_block gic_notifier_block = { 758 .notifier_call = gic_notifier, 759 }; 760 761 static int gic_pm_init(struct gic_chip_data *gic) 762 { 763 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 764 sizeof(u32)); 765 if (WARN_ON(!gic->saved_ppi_enable)) 766 return -ENOMEM; 767 768 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 769 sizeof(u32)); 770 if (WARN_ON(!gic->saved_ppi_active)) 771 goto free_ppi_enable; 772 773 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 774 sizeof(u32)); 775 if (WARN_ON(!gic->saved_ppi_conf)) 776 goto free_ppi_active; 777 778 if (gic == &gic_data[0]) 779 cpu_pm_register_notifier(&gic_notifier_block); 780 781 return 0; 782 783 free_ppi_active: 784 free_percpu(gic->saved_ppi_active); 785 free_ppi_enable: 786 free_percpu(gic->saved_ppi_enable); 787 788 return -ENOMEM; 789 } 790 #else 791 static int gic_pm_init(struct gic_chip_data *gic) 792 { 793 return 0; 794 } 795 #endif 796 797 #ifdef CONFIG_SMP 798 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 799 { 800 int cpu; 801 unsigned long flags, map = 0; 802 803 if (unlikely(nr_cpu_ids == 1)) { 804 /* Only one CPU? let's do a self-IPI... */ 805 writel_relaxed(2 << 24 | irq, 806 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 807 return; 808 } 809 810 gic_lock_irqsave(flags); 811 812 /* Convert our logical CPU mask into a physical one. */ 813 for_each_cpu(cpu, mask) 814 map |= gic_cpu_map[cpu]; 815 816 /* 817 * Ensure that stores to Normal memory are visible to the 818 * other CPUs before they observe us issuing the IPI. 819 */ 820 dmb(ishst); 821 822 /* this always happens on GIC0 */ 823 writel_relaxed(map << 16 | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 824 825 gic_unlock_irqrestore(flags); 826 } 827 #endif 828 829 #ifdef CONFIG_BL_SWITCHER 830 /* 831 * gic_send_sgi - send a SGI directly to given CPU interface number 832 * 833 * cpu_id: the ID for the destination CPU interface 834 * irq: the IPI number to send a SGI for 835 */ 836 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 837 { 838 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 839 cpu_id = 1 << cpu_id; 840 /* this always happens on GIC0 */ 841 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 842 } 843 844 /* 845 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 846 * 847 * @cpu: the logical CPU number to get the GIC ID for. 848 * 849 * Return the CPU interface ID for the given logical CPU number, 850 * or -1 if the CPU number is too large or the interface ID is 851 * unknown (more than one bit set). 852 */ 853 int gic_get_cpu_id(unsigned int cpu) 854 { 855 unsigned int cpu_bit; 856 857 if (cpu >= NR_GIC_CPU_IF) 858 return -1; 859 cpu_bit = gic_cpu_map[cpu]; 860 if (cpu_bit & (cpu_bit - 1)) 861 return -1; 862 return __ffs(cpu_bit); 863 } 864 865 /* 866 * gic_migrate_target - migrate IRQs to another CPU interface 867 * 868 * @new_cpu_id: the CPU target ID to migrate IRQs to 869 * 870 * Migrate all peripheral interrupts with a target matching the current CPU 871 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 872 * is also updated. Targets to other CPU interfaces are unchanged. 873 * This must be called with IRQs locally disabled. 874 */ 875 void gic_migrate_target(unsigned int new_cpu_id) 876 { 877 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 878 void __iomem *dist_base; 879 int i, ror_val, cpu = smp_processor_id(); 880 u32 val, cur_target_mask, active_mask; 881 882 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 883 884 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 885 if (!dist_base) 886 return; 887 gic_irqs = gic_data[gic_nr].gic_irqs; 888 889 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 890 cur_target_mask = 0x01010101 << cur_cpu_id; 891 ror_val = (cur_cpu_id - new_cpu_id) & 31; 892 893 gic_lock(); 894 895 /* Update the target interface for this logical CPU */ 896 gic_cpu_map[cpu] = 1 << new_cpu_id; 897 898 /* 899 * Find all the peripheral interrupts targeting the current 900 * CPU interface and migrate them to the new CPU interface. 901 * We skip DIST_TARGET 0 to 7 as they are read-only. 902 */ 903 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 904 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 905 active_mask = val & cur_target_mask; 906 if (active_mask) { 907 val &= ~active_mask; 908 val |= ror32(active_mask, ror_val); 909 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 910 } 911 } 912 913 gic_unlock(); 914 915 /* 916 * Now let's migrate and clear any potential SGIs that might be 917 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 918 * is a banked register, we can only forward the SGI using 919 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 920 * doesn't use that information anyway. 921 * 922 * For the same reason we do not adjust SGI source information 923 * for previously sent SGIs by us to other CPUs either. 924 */ 925 for (i = 0; i < 16; i += 4) { 926 int j; 927 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 928 if (!val) 929 continue; 930 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 931 for (j = i; j < i + 4; j++) { 932 if (val & 0xff) 933 writel_relaxed((1 << (new_cpu_id + 16)) | j, 934 dist_base + GIC_DIST_SOFTINT); 935 val >>= 8; 936 } 937 } 938 } 939 940 /* 941 * gic_get_sgir_physaddr - get the physical address for the SGI register 942 * 943 * REturn the physical address of the SGI register to be used 944 * by some early assembly code when the kernel is not yet available. 945 */ 946 static unsigned long gic_dist_physaddr; 947 948 unsigned long gic_get_sgir_physaddr(void) 949 { 950 if (!gic_dist_physaddr) 951 return 0; 952 return gic_dist_physaddr + GIC_DIST_SOFTINT; 953 } 954 955 static void __init gic_init_physaddr(struct device_node *node) 956 { 957 struct resource res; 958 if (of_address_to_resource(node, 0, &res) == 0) { 959 gic_dist_physaddr = res.start; 960 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 961 } 962 } 963 964 #else 965 #define gic_init_physaddr(node) do { } while (0) 966 #endif 967 968 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 969 irq_hw_number_t hw) 970 { 971 struct gic_chip_data *gic = d->host_data; 972 973 if (hw < 32) { 974 irq_set_percpu_devid(irq); 975 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 976 handle_percpu_devid_irq, NULL, NULL); 977 irq_set_status_flags(irq, IRQ_NOAUTOEN); 978 } else { 979 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 980 handle_fasteoi_irq, NULL, NULL); 981 irq_set_probe(irq); 982 irqd_set_single_target(irq_desc_get_irq_data(irq_to_desc(irq))); 983 } 984 return 0; 985 } 986 987 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 988 { 989 } 990 991 static int gic_irq_domain_translate(struct irq_domain *d, 992 struct irq_fwspec *fwspec, 993 unsigned long *hwirq, 994 unsigned int *type) 995 { 996 if (is_of_node(fwspec->fwnode)) { 997 if (fwspec->param_count < 3) 998 return -EINVAL; 999 1000 /* Get the interrupt number and add 16 to skip over SGIs */ 1001 *hwirq = fwspec->param[1] + 16; 1002 1003 /* 1004 * For SPIs, we need to add 16 more to get the GIC irq 1005 * ID number 1006 */ 1007 if (!fwspec->param[0]) 1008 *hwirq += 16; 1009 1010 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1011 1012 /* Make it clear that broken DTs are... broken */ 1013 WARN_ON(*type == IRQ_TYPE_NONE); 1014 return 0; 1015 } 1016 1017 if (is_fwnode_irqchip(fwspec->fwnode)) { 1018 if(fwspec->param_count != 2) 1019 return -EINVAL; 1020 1021 *hwirq = fwspec->param[0]; 1022 *type = fwspec->param[1]; 1023 1024 WARN_ON(*type == IRQ_TYPE_NONE); 1025 return 0; 1026 } 1027 1028 return -EINVAL; 1029 } 1030 1031 static int gic_starting_cpu(unsigned int cpu) 1032 { 1033 gic_cpu_init(&gic_data[0]); 1034 return 0; 1035 } 1036 1037 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1038 unsigned int nr_irqs, void *arg) 1039 { 1040 int i, ret; 1041 irq_hw_number_t hwirq; 1042 unsigned int type = IRQ_TYPE_NONE; 1043 struct irq_fwspec *fwspec = arg; 1044 1045 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1046 if (ret) 1047 return ret; 1048 1049 for (i = 0; i < nr_irqs; i++) { 1050 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 1051 if (ret) 1052 return ret; 1053 } 1054 1055 return 0; 1056 } 1057 1058 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 1059 .translate = gic_irq_domain_translate, 1060 .alloc = gic_irq_domain_alloc, 1061 .free = irq_domain_free_irqs_top, 1062 }; 1063 1064 static const struct irq_domain_ops gic_irq_domain_ops = { 1065 .map = gic_irq_domain_map, 1066 .unmap = gic_irq_domain_unmap, 1067 }; 1068 1069 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, 1070 const char *name, bool use_eoimode1) 1071 { 1072 /* Initialize irq_chip */ 1073 gic->chip = gic_chip; 1074 gic->chip.name = name; 1075 gic->chip.parent_device = dev; 1076 1077 if (use_eoimode1) { 1078 gic->chip.irq_mask = gic_eoimode1_mask_irq; 1079 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; 1080 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; 1081 } 1082 1083 #ifdef CONFIG_SMP 1084 if (gic == &gic_data[0]) 1085 gic->chip.irq_set_affinity = gic_set_affinity; 1086 #endif 1087 } 1088 1089 static int gic_init_bases(struct gic_chip_data *gic, 1090 struct fwnode_handle *handle) 1091 { 1092 int gic_irqs, ret; 1093 1094 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1095 /* Frankein-GIC without banked registers... */ 1096 unsigned int cpu; 1097 1098 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 1099 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 1100 if (WARN_ON(!gic->dist_base.percpu_base || 1101 !gic->cpu_base.percpu_base)) { 1102 ret = -ENOMEM; 1103 goto error; 1104 } 1105 1106 for_each_possible_cpu(cpu) { 1107 u32 mpidr = cpu_logical_map(cpu); 1108 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 1109 unsigned long offset = gic->percpu_offset * core_id; 1110 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 1111 gic->raw_dist_base + offset; 1112 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = 1113 gic->raw_cpu_base + offset; 1114 } 1115 1116 gic_set_base_accessor(gic, gic_get_percpu_base); 1117 } else { 1118 /* Normal, sane GIC... */ 1119 WARN(gic->percpu_offset, 1120 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 1121 gic->percpu_offset); 1122 gic->dist_base.common_base = gic->raw_dist_base; 1123 gic->cpu_base.common_base = gic->raw_cpu_base; 1124 gic_set_base_accessor(gic, gic_get_common_base); 1125 } 1126 1127 /* 1128 * Find out how many interrupts are supported. 1129 * The GIC only supports up to 1020 interrupt sources. 1130 */ 1131 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1132 gic_irqs = (gic_irqs + 1) * 32; 1133 if (gic_irqs > 1020) 1134 gic_irqs = 1020; 1135 gic->gic_irqs = gic_irqs; 1136 1137 if (handle) { /* DT/ACPI */ 1138 gic->domain = irq_domain_create_linear(handle, gic_irqs, 1139 &gic_irq_domain_hierarchy_ops, 1140 gic); 1141 } else { /* Legacy support */ 1142 /* 1143 * For primary GICs, skip over SGIs. 1144 * No secondary GIC support whatsoever. 1145 */ 1146 int irq_base; 1147 1148 gic_irqs -= 16; /* calculate # of irqs to allocate */ 1149 1150 irq_base = irq_alloc_descs(16, 16, gic_irqs, 1151 numa_node_id()); 1152 if (irq_base < 0) { 1153 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n"); 1154 irq_base = 16; 1155 } 1156 1157 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, 1158 16, &gic_irq_domain_ops, gic); 1159 } 1160 1161 if (WARN_ON(!gic->domain)) { 1162 ret = -ENODEV; 1163 goto error; 1164 } 1165 1166 gic_dist_init(gic); 1167 ret = gic_cpu_init(gic); 1168 if (ret) 1169 goto error; 1170 1171 ret = gic_pm_init(gic); 1172 if (ret) 1173 goto error; 1174 1175 return 0; 1176 1177 error: 1178 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1179 free_percpu(gic->dist_base.percpu_base); 1180 free_percpu(gic->cpu_base.percpu_base); 1181 } 1182 1183 return ret; 1184 } 1185 1186 static int __init __gic_init_bases(struct gic_chip_data *gic, 1187 struct fwnode_handle *handle) 1188 { 1189 char *name; 1190 int i, ret; 1191 1192 if (WARN_ON(!gic || gic->domain)) 1193 return -EINVAL; 1194 1195 if (gic == &gic_data[0]) { 1196 /* 1197 * Initialize the CPU interface map to all CPUs. 1198 * It will be refined as each CPU probes its ID. 1199 * This is only necessary for the primary GIC. 1200 */ 1201 for (i = 0; i < NR_GIC_CPU_IF; i++) 1202 gic_cpu_map[i] = 0xff; 1203 #ifdef CONFIG_SMP 1204 set_smp_cross_call(gic_raise_softirq); 1205 #endif 1206 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 1207 "irqchip/arm/gic:starting", 1208 gic_starting_cpu, NULL); 1209 set_handle_irq(gic_handle_irq); 1210 if (static_branch_likely(&supports_deactivate_key)) 1211 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1212 } 1213 1214 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { 1215 name = kasprintf(GFP_KERNEL, "GICv2"); 1216 gic_init_chip(gic, NULL, name, true); 1217 } else { 1218 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); 1219 gic_init_chip(gic, NULL, name, false); 1220 } 1221 1222 ret = gic_init_bases(gic, handle); 1223 if (ret) 1224 kfree(name); 1225 1226 return ret; 1227 } 1228 1229 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base) 1230 { 1231 struct gic_chip_data *gic; 1232 1233 /* 1234 * Non-DT/ACPI systems won't run a hypervisor, so let's not 1235 * bother with these... 1236 */ 1237 static_branch_disable(&supports_deactivate_key); 1238 1239 gic = &gic_data[0]; 1240 gic->raw_dist_base = dist_base; 1241 gic->raw_cpu_base = cpu_base; 1242 1243 __gic_init_bases(gic, NULL); 1244 } 1245 1246 static void gic_teardown(struct gic_chip_data *gic) 1247 { 1248 if (WARN_ON(!gic)) 1249 return; 1250 1251 if (gic->raw_dist_base) 1252 iounmap(gic->raw_dist_base); 1253 if (gic->raw_cpu_base) 1254 iounmap(gic->raw_cpu_base); 1255 } 1256 1257 #ifdef CONFIG_OF 1258 static int gic_cnt __initdata; 1259 static bool gicv2_force_probe; 1260 1261 static int __init gicv2_force_probe_cfg(char *buf) 1262 { 1263 return strtobool(buf, &gicv2_force_probe); 1264 } 1265 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg); 1266 1267 static bool gic_check_eoimode(struct device_node *node, void __iomem **base) 1268 { 1269 struct resource cpuif_res; 1270 1271 of_address_to_resource(node, 1, &cpuif_res); 1272 1273 if (!is_hyp_mode_available()) 1274 return false; 1275 if (resource_size(&cpuif_res) < SZ_8K) { 1276 void __iomem *alt; 1277 /* 1278 * Check for a stupid firmware that only exposes the 1279 * first page of a GICv2. 1280 */ 1281 if (!gic_check_gicv2(*base)) 1282 return false; 1283 1284 if (!gicv2_force_probe) { 1285 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); 1286 return false; 1287 } 1288 1289 alt = ioremap(cpuif_res.start, SZ_8K); 1290 if (!alt) 1291 return false; 1292 if (!gic_check_gicv2(alt + SZ_4K)) { 1293 /* 1294 * The first page was that of a GICv2, and 1295 * the second was *something*. Let's trust it 1296 * to be a GICv2, and update the mapping. 1297 */ 1298 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", 1299 &cpuif_res.start); 1300 iounmap(*base); 1301 *base = alt; 1302 return true; 1303 } 1304 1305 /* 1306 * We detected *two* initial GICv2 pages in a 1307 * row. Could be a GICv2 aliased over two 64kB 1308 * pages. Update the resource, map the iospace, and 1309 * pray. 1310 */ 1311 iounmap(alt); 1312 alt = ioremap(cpuif_res.start, SZ_128K); 1313 if (!alt) 1314 return false; 1315 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", 1316 &cpuif_res.start); 1317 cpuif_res.end = cpuif_res.start + SZ_128K -1; 1318 iounmap(*base); 1319 *base = alt; 1320 } 1321 if (resource_size(&cpuif_res) == SZ_128K) { 1322 /* 1323 * Verify that we have the first 4kB of a GICv2 1324 * aliased over the first 64kB by checking the 1325 * GICC_IIDR register on both ends. 1326 */ 1327 if (!gic_check_gicv2(*base) || 1328 !gic_check_gicv2(*base + 0xf000)) 1329 return false; 1330 1331 /* 1332 * Move the base up by 60kB, so that we have a 8kB 1333 * contiguous region, which allows us to use GICC_DIR 1334 * at its normal offset. Please pass me that bucket. 1335 */ 1336 *base += 0xf000; 1337 cpuif_res.start += 0xf000; 1338 pr_warn("GIC: Adjusting CPU interface base to %pa\n", 1339 &cpuif_res.start); 1340 } 1341 1342 return true; 1343 } 1344 1345 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) 1346 { 1347 if (!gic || !node) 1348 return -EINVAL; 1349 1350 gic->raw_dist_base = of_iomap(node, 0); 1351 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) 1352 goto error; 1353 1354 gic->raw_cpu_base = of_iomap(node, 1); 1355 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) 1356 goto error; 1357 1358 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) 1359 gic->percpu_offset = 0; 1360 1361 return 0; 1362 1363 error: 1364 gic_teardown(gic); 1365 1366 return -ENOMEM; 1367 } 1368 1369 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1370 { 1371 int ret; 1372 1373 if (!dev || !dev->of_node || !gic || !irq) 1374 return -EINVAL; 1375 1376 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); 1377 if (!*gic) 1378 return -ENOMEM; 1379 1380 gic_init_chip(*gic, dev, dev->of_node->name, false); 1381 1382 ret = gic_of_setup(*gic, dev->of_node); 1383 if (ret) 1384 return ret; 1385 1386 ret = gic_init_bases(*gic, &dev->of_node->fwnode); 1387 if (ret) { 1388 gic_teardown(*gic); 1389 return ret; 1390 } 1391 1392 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); 1393 1394 return 0; 1395 } 1396 1397 static void __init gic_of_setup_kvm_info(struct device_node *node) 1398 { 1399 int ret; 1400 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1401 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1402 1403 gic_v2_kvm_info.type = GIC_V2; 1404 1405 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1406 if (!gic_v2_kvm_info.maint_irq) 1407 return; 1408 1409 ret = of_address_to_resource(node, 2, vctrl_res); 1410 if (ret) 1411 return; 1412 1413 ret = of_address_to_resource(node, 3, vcpu_res); 1414 if (ret) 1415 return; 1416 1417 if (static_branch_likely(&supports_deactivate_key)) 1418 gic_set_kvm_info(&gic_v2_kvm_info); 1419 } 1420 1421 int __init 1422 gic_of_init(struct device_node *node, struct device_node *parent) 1423 { 1424 struct gic_chip_data *gic; 1425 int irq, ret; 1426 1427 if (WARN_ON(!node)) 1428 return -ENODEV; 1429 1430 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) 1431 return -EINVAL; 1432 1433 gic = &gic_data[gic_cnt]; 1434 1435 ret = gic_of_setup(gic, node); 1436 if (ret) 1437 return ret; 1438 1439 /* 1440 * Disable split EOI/Deactivate if either HYP is not available 1441 * or the CPU interface is too small. 1442 */ 1443 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) 1444 static_branch_disable(&supports_deactivate_key); 1445 1446 ret = __gic_init_bases(gic, &node->fwnode); 1447 if (ret) { 1448 gic_teardown(gic); 1449 return ret; 1450 } 1451 1452 if (!gic_cnt) { 1453 gic_init_physaddr(node); 1454 gic_of_setup_kvm_info(node); 1455 } 1456 1457 if (parent) { 1458 irq = irq_of_parse_and_map(node, 0); 1459 gic_cascade_irq(gic_cnt, irq); 1460 } 1461 1462 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1463 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); 1464 1465 gic_cnt++; 1466 return 0; 1467 } 1468 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1469 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1470 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1471 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1472 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1473 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1474 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1475 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1476 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1477 #else 1478 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1479 { 1480 return -ENOTSUPP; 1481 } 1482 #endif 1483 1484 #ifdef CONFIG_ACPI 1485 static struct 1486 { 1487 phys_addr_t cpu_phys_base; 1488 u32 maint_irq; 1489 int maint_irq_mode; 1490 phys_addr_t vctrl_base; 1491 phys_addr_t vcpu_base; 1492 } acpi_data __initdata; 1493 1494 static int __init 1495 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header, 1496 const unsigned long end) 1497 { 1498 struct acpi_madt_generic_interrupt *processor; 1499 phys_addr_t gic_cpu_base; 1500 static int cpu_base_assigned; 1501 1502 processor = (struct acpi_madt_generic_interrupt *)header; 1503 1504 if (BAD_MADT_GICC_ENTRY(processor, end)) 1505 return -EINVAL; 1506 1507 /* 1508 * There is no support for non-banked GICv1/2 register in ACPI spec. 1509 * All CPU interface addresses have to be the same. 1510 */ 1511 gic_cpu_base = processor->base_address; 1512 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) 1513 return -EINVAL; 1514 1515 acpi_data.cpu_phys_base = gic_cpu_base; 1516 acpi_data.maint_irq = processor->vgic_interrupt; 1517 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1518 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1519 acpi_data.vctrl_base = processor->gich_base_address; 1520 acpi_data.vcpu_base = processor->gicv_base_address; 1521 1522 cpu_base_assigned = 1; 1523 return 0; 1524 } 1525 1526 /* The things you have to do to just *count* something... */ 1527 static int __init acpi_dummy_func(union acpi_subtable_headers *header, 1528 const unsigned long end) 1529 { 1530 return 0; 1531 } 1532 1533 static bool __init acpi_gic_redist_is_present(void) 1534 { 1535 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1536 acpi_dummy_func, 0) > 0; 1537 } 1538 1539 static bool __init gic_validate_dist(struct acpi_subtable_header *header, 1540 struct acpi_probe_entry *ape) 1541 { 1542 struct acpi_madt_generic_distributor *dist; 1543 dist = (struct acpi_madt_generic_distributor *)header; 1544 1545 return (dist->version == ape->driver_data && 1546 (dist->version != ACPI_MADT_GIC_VERSION_NONE || 1547 !acpi_gic_redist_is_present())); 1548 } 1549 1550 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) 1551 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) 1552 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1553 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1554 1555 static void __init gic_acpi_setup_kvm_info(void) 1556 { 1557 int irq; 1558 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1559 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1560 1561 gic_v2_kvm_info.type = GIC_V2; 1562 1563 if (!acpi_data.vctrl_base) 1564 return; 1565 1566 vctrl_res->flags = IORESOURCE_MEM; 1567 vctrl_res->start = acpi_data.vctrl_base; 1568 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; 1569 1570 if (!acpi_data.vcpu_base) 1571 return; 1572 1573 vcpu_res->flags = IORESOURCE_MEM; 1574 vcpu_res->start = acpi_data.vcpu_base; 1575 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1576 1577 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1578 acpi_data.maint_irq_mode, 1579 ACPI_ACTIVE_HIGH); 1580 if (irq <= 0) 1581 return; 1582 1583 gic_v2_kvm_info.maint_irq = irq; 1584 1585 gic_set_kvm_info(&gic_v2_kvm_info); 1586 } 1587 1588 static int __init gic_v2_acpi_init(struct acpi_subtable_header *header, 1589 const unsigned long end) 1590 { 1591 struct acpi_madt_generic_distributor *dist; 1592 struct fwnode_handle *domain_handle; 1593 struct gic_chip_data *gic = &gic_data[0]; 1594 int count, ret; 1595 1596 /* Collect CPU base addresses */ 1597 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1598 gic_acpi_parse_madt_cpu, 0); 1599 if (count <= 0) { 1600 pr_err("No valid GICC entries exist\n"); 1601 return -EINVAL; 1602 } 1603 1604 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1605 if (!gic->raw_cpu_base) { 1606 pr_err("Unable to map GICC registers\n"); 1607 return -ENOMEM; 1608 } 1609 1610 dist = (struct acpi_madt_generic_distributor *)header; 1611 gic->raw_dist_base = ioremap(dist->base_address, 1612 ACPI_GICV2_DIST_MEM_SIZE); 1613 if (!gic->raw_dist_base) { 1614 pr_err("Unable to map GICD registers\n"); 1615 gic_teardown(gic); 1616 return -ENOMEM; 1617 } 1618 1619 /* 1620 * Disable split EOI/Deactivate if HYP is not available. ACPI 1621 * guarantees that we'll always have a GICv2, so the CPU 1622 * interface will always be the right size. 1623 */ 1624 if (!is_hyp_mode_available()) 1625 static_branch_disable(&supports_deactivate_key); 1626 1627 /* 1628 * Initialize GIC instance zero (no multi-GIC support). 1629 */ 1630 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base); 1631 if (!domain_handle) { 1632 pr_err("Unable to allocate domain handle\n"); 1633 gic_teardown(gic); 1634 return -ENOMEM; 1635 } 1636 1637 ret = __gic_init_bases(gic, domain_handle); 1638 if (ret) { 1639 pr_err("Failed to initialise GIC\n"); 1640 irq_domain_free_fwnode(domain_handle); 1641 gic_teardown(gic); 1642 return ret; 1643 } 1644 1645 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1646 1647 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1648 gicv2m_init(NULL, gic_data[0].domain); 1649 1650 if (static_branch_likely(&supports_deactivate_key)) 1651 gic_acpi_setup_kvm_info(); 1652 1653 return 0; 1654 } 1655 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1656 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, 1657 gic_v2_acpi_init); 1658 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1659 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, 1660 gic_v2_acpi_init); 1661 #endif 1662