1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2002 ARM Limited, All Rights Reserved. 4 * 5 * Interrupt architecture for the GIC: 6 * 7 * o There is one Interrupt Distributor, which receives interrupts 8 * from system devices and sends them to the Interrupt Controllers. 9 * 10 * o There is one CPU Interface per CPU, which sends interrupts sent 11 * by the Distributor, and interrupts generated locally, to the 12 * associated CPU. The base address of the CPU interface is usually 13 * aliased so that the same address points to different chips depending 14 * on the CPU it is accessed from. 15 * 16 * Note that IRQs 0-31 are special - they are local to each CPU. 17 * As such, the enable set/clear, pending set/clear and active bit 18 * registers are banked per-cpu for these sources. 19 */ 20 #include <linux/init.h> 21 #include <linux/kernel.h> 22 #include <linux/err.h> 23 #include <linux/module.h> 24 #include <linux/list.h> 25 #include <linux/smp.h> 26 #include <linux/cpu.h> 27 #include <linux/cpu_pm.h> 28 #include <linux/cpumask.h> 29 #include <linux/io.h> 30 #include <linux/of.h> 31 #include <linux/of_address.h> 32 #include <linux/of_irq.h> 33 #include <linux/acpi.h> 34 #include <linux/irqdomain.h> 35 #include <linux/interrupt.h> 36 #include <linux/percpu.h> 37 #include <linux/slab.h> 38 #include <linux/irqchip.h> 39 #include <linux/irqchip/chained_irq.h> 40 #include <linux/irqchip/arm-gic.h> 41 42 #include <asm/cputype.h> 43 #include <asm/irq.h> 44 #include <asm/exception.h> 45 #include <asm/smp_plat.h> 46 #include <asm/virt.h> 47 48 #include "irq-gic-common.h" 49 50 #ifdef CONFIG_ARM64 51 #include <asm/cpufeature.h> 52 53 static void gic_check_cpu_features(void) 54 { 55 WARN_TAINT_ONCE(this_cpu_has_cap(ARM64_HAS_SYSREG_GIC_CPUIF), 56 TAINT_CPU_OUT_OF_SPEC, 57 "GICv3 system registers enabled, broken firmware!\n"); 58 } 59 #else 60 #define gic_check_cpu_features() do { } while(0) 61 #endif 62 63 union gic_base { 64 void __iomem *common_base; 65 void __percpu * __iomem *percpu_base; 66 }; 67 68 struct gic_chip_data { 69 struct irq_chip chip; 70 union gic_base dist_base; 71 union gic_base cpu_base; 72 void __iomem *raw_dist_base; 73 void __iomem *raw_cpu_base; 74 u32 percpu_offset; 75 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 76 u32 saved_spi_enable[DIV_ROUND_UP(1020, 32)]; 77 u32 saved_spi_active[DIV_ROUND_UP(1020, 32)]; 78 u32 saved_spi_conf[DIV_ROUND_UP(1020, 16)]; 79 u32 saved_spi_target[DIV_ROUND_UP(1020, 4)]; 80 u32 __percpu *saved_ppi_enable; 81 u32 __percpu *saved_ppi_active; 82 u32 __percpu *saved_ppi_conf; 83 #endif 84 struct irq_domain *domain; 85 unsigned int gic_irqs; 86 }; 87 88 #ifdef CONFIG_BL_SWITCHER 89 90 static DEFINE_RAW_SPINLOCK(cpu_map_lock); 91 92 #define gic_lock_irqsave(f) \ 93 raw_spin_lock_irqsave(&cpu_map_lock, (f)) 94 #define gic_unlock_irqrestore(f) \ 95 raw_spin_unlock_irqrestore(&cpu_map_lock, (f)) 96 97 #define gic_lock() raw_spin_lock(&cpu_map_lock) 98 #define gic_unlock() raw_spin_unlock(&cpu_map_lock) 99 100 #else 101 102 #define gic_lock_irqsave(f) do { (void)(f); } while(0) 103 #define gic_unlock_irqrestore(f) do { (void)(f); } while(0) 104 105 #define gic_lock() do { } while(0) 106 #define gic_unlock() do { } while(0) 107 108 #endif 109 110 /* 111 * The GIC mapping of CPU interfaces does not necessarily match 112 * the logical CPU numbering. Let's use a mapping as returned 113 * by the GIC itself. 114 */ 115 #define NR_GIC_CPU_IF 8 116 static u8 gic_cpu_map[NR_GIC_CPU_IF] __read_mostly; 117 118 static DEFINE_STATIC_KEY_TRUE(supports_deactivate_key); 119 120 static struct gic_chip_data gic_data[CONFIG_ARM_GIC_MAX_NR] __read_mostly; 121 122 static struct gic_kvm_info gic_v2_kvm_info; 123 124 static DEFINE_PER_CPU(u32, sgi_intid); 125 126 #ifdef CONFIG_GIC_NON_BANKED 127 static DEFINE_STATIC_KEY_FALSE(frankengic_key); 128 129 static void enable_frankengic(void) 130 { 131 static_branch_enable(&frankengic_key); 132 } 133 134 static inline void __iomem *__get_base(union gic_base *base) 135 { 136 if (static_branch_unlikely(&frankengic_key)) 137 return raw_cpu_read(*base->percpu_base); 138 139 return base->common_base; 140 } 141 142 #define gic_data_dist_base(d) __get_base(&(d)->dist_base) 143 #define gic_data_cpu_base(d) __get_base(&(d)->cpu_base) 144 #else 145 #define gic_data_dist_base(d) ((d)->dist_base.common_base) 146 #define gic_data_cpu_base(d) ((d)->cpu_base.common_base) 147 #define enable_frankengic() do { } while(0) 148 #endif 149 150 static inline void __iomem *gic_dist_base(struct irq_data *d) 151 { 152 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 153 return gic_data_dist_base(gic_data); 154 } 155 156 static inline void __iomem *gic_cpu_base(struct irq_data *d) 157 { 158 struct gic_chip_data *gic_data = irq_data_get_irq_chip_data(d); 159 return gic_data_cpu_base(gic_data); 160 } 161 162 static inline unsigned int gic_irq(struct irq_data *d) 163 { 164 return d->hwirq; 165 } 166 167 static inline bool cascading_gic_irq(struct irq_data *d) 168 { 169 void *data = irq_data_get_irq_handler_data(d); 170 171 /* 172 * If handler_data is set, this is a cascading interrupt, and 173 * it cannot possibly be forwarded. 174 */ 175 return data != NULL; 176 } 177 178 /* 179 * Routines to acknowledge, disable and enable interrupts 180 */ 181 static void gic_poke_irq(struct irq_data *d, u32 offset) 182 { 183 u32 mask = 1 << (gic_irq(d) % 32); 184 writel_relaxed(mask, gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4); 185 } 186 187 static int gic_peek_irq(struct irq_data *d, u32 offset) 188 { 189 u32 mask = 1 << (gic_irq(d) % 32); 190 return !!(readl_relaxed(gic_dist_base(d) + offset + (gic_irq(d) / 32) * 4) & mask); 191 } 192 193 static void gic_mask_irq(struct irq_data *d) 194 { 195 gic_poke_irq(d, GIC_DIST_ENABLE_CLEAR); 196 } 197 198 static void gic_eoimode1_mask_irq(struct irq_data *d) 199 { 200 gic_mask_irq(d); 201 /* 202 * When masking a forwarded interrupt, make sure it is 203 * deactivated as well. 204 * 205 * This ensures that an interrupt that is getting 206 * disabled/masked will not get "stuck", because there is 207 * noone to deactivate it (guest is being terminated). 208 */ 209 if (irqd_is_forwarded_to_vcpu(d)) 210 gic_poke_irq(d, GIC_DIST_ACTIVE_CLEAR); 211 } 212 213 static void gic_unmask_irq(struct irq_data *d) 214 { 215 gic_poke_irq(d, GIC_DIST_ENABLE_SET); 216 } 217 218 static void gic_eoi_irq(struct irq_data *d) 219 { 220 u32 hwirq = gic_irq(d); 221 222 if (hwirq < 16) 223 hwirq = this_cpu_read(sgi_intid); 224 225 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_EOI); 226 } 227 228 static void gic_eoimode1_eoi_irq(struct irq_data *d) 229 { 230 u32 hwirq = gic_irq(d); 231 232 /* Do not deactivate an IRQ forwarded to a vcpu. */ 233 if (irqd_is_forwarded_to_vcpu(d)) 234 return; 235 236 if (hwirq < 16) 237 hwirq = this_cpu_read(sgi_intid); 238 239 writel_relaxed(hwirq, gic_cpu_base(d) + GIC_CPU_DEACTIVATE); 240 } 241 242 static int gic_irq_set_irqchip_state(struct irq_data *d, 243 enum irqchip_irq_state which, bool val) 244 { 245 u32 reg; 246 247 switch (which) { 248 case IRQCHIP_STATE_PENDING: 249 reg = val ? GIC_DIST_PENDING_SET : GIC_DIST_PENDING_CLEAR; 250 break; 251 252 case IRQCHIP_STATE_ACTIVE: 253 reg = val ? GIC_DIST_ACTIVE_SET : GIC_DIST_ACTIVE_CLEAR; 254 break; 255 256 case IRQCHIP_STATE_MASKED: 257 reg = val ? GIC_DIST_ENABLE_CLEAR : GIC_DIST_ENABLE_SET; 258 break; 259 260 default: 261 return -EINVAL; 262 } 263 264 gic_poke_irq(d, reg); 265 return 0; 266 } 267 268 static int gic_irq_get_irqchip_state(struct irq_data *d, 269 enum irqchip_irq_state which, bool *val) 270 { 271 switch (which) { 272 case IRQCHIP_STATE_PENDING: 273 *val = gic_peek_irq(d, GIC_DIST_PENDING_SET); 274 break; 275 276 case IRQCHIP_STATE_ACTIVE: 277 *val = gic_peek_irq(d, GIC_DIST_ACTIVE_SET); 278 break; 279 280 case IRQCHIP_STATE_MASKED: 281 *val = !gic_peek_irq(d, GIC_DIST_ENABLE_SET); 282 break; 283 284 default: 285 return -EINVAL; 286 } 287 288 return 0; 289 } 290 291 static int gic_set_type(struct irq_data *d, unsigned int type) 292 { 293 void __iomem *base = gic_dist_base(d); 294 unsigned int gicirq = gic_irq(d); 295 int ret; 296 297 /* Interrupt configuration for SGIs can't be changed */ 298 if (gicirq < 16) 299 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; 300 301 /* SPIs have restrictions on the supported types */ 302 if (gicirq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 303 type != IRQ_TYPE_EDGE_RISING) 304 return -EINVAL; 305 306 ret = gic_configure_irq(gicirq, type, base + GIC_DIST_CONFIG, NULL); 307 if (ret && gicirq < 32) { 308 /* Misconfigured PPIs are usually not fatal */ 309 pr_warn("GIC: PPI%d is secure or misconfigured\n", gicirq - 16); 310 ret = 0; 311 } 312 313 return ret; 314 } 315 316 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 317 { 318 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ 319 if (cascading_gic_irq(d) || gic_irq(d) < 16) 320 return -EINVAL; 321 322 if (vcpu) 323 irqd_set_forwarded_to_vcpu(d); 324 else 325 irqd_clr_forwarded_to_vcpu(d); 326 return 0; 327 } 328 329 static int gic_retrigger(struct irq_data *data) 330 { 331 return !gic_irq_set_irqchip_state(data, IRQCHIP_STATE_PENDING, true); 332 } 333 334 static void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 335 { 336 u32 irqstat, irqnr; 337 struct gic_chip_data *gic = &gic_data[0]; 338 void __iomem *cpu_base = gic_data_cpu_base(gic); 339 340 do { 341 irqstat = readl_relaxed(cpu_base + GIC_CPU_INTACK); 342 irqnr = irqstat & GICC_IAR_INT_ID_MASK; 343 344 if (unlikely(irqnr >= 1020)) 345 break; 346 347 if (static_branch_likely(&supports_deactivate_key)) 348 writel_relaxed(irqstat, cpu_base + GIC_CPU_EOI); 349 isb(); 350 351 /* 352 * Ensure any shared data written by the CPU sending the IPI 353 * is read after we've read the ACK register on the GIC. 354 * 355 * Pairs with the write barrier in gic_ipi_send_mask 356 */ 357 if (irqnr <= 15) { 358 smp_rmb(); 359 360 /* 361 * The GIC encodes the source CPU in GICC_IAR, 362 * leading to the deactivation to fail if not 363 * written back as is to GICC_EOI. Stash the INTID 364 * away for gic_eoi_irq() to write back. This only 365 * works because we don't nest SGIs... 366 */ 367 this_cpu_write(sgi_intid, irqstat); 368 } 369 370 handle_domain_irq(gic->domain, irqnr, regs); 371 } while (1); 372 } 373 374 static void gic_handle_cascade_irq(struct irq_desc *desc) 375 { 376 struct gic_chip_data *chip_data = irq_desc_get_handler_data(desc); 377 struct irq_chip *chip = irq_desc_get_chip(desc); 378 unsigned int gic_irq; 379 unsigned long status; 380 int ret; 381 382 chained_irq_enter(chip, desc); 383 384 status = readl_relaxed(gic_data_cpu_base(chip_data) + GIC_CPU_INTACK); 385 386 gic_irq = (status & GICC_IAR_INT_ID_MASK); 387 if (gic_irq == GICC_INT_SPURIOUS) 388 goto out; 389 390 isb(); 391 ret = generic_handle_domain_irq(chip_data->domain, gic_irq); 392 if (unlikely(ret)) 393 handle_bad_irq(desc); 394 out: 395 chained_irq_exit(chip, desc); 396 } 397 398 static const struct irq_chip gic_chip = { 399 .irq_mask = gic_mask_irq, 400 .irq_unmask = gic_unmask_irq, 401 .irq_eoi = gic_eoi_irq, 402 .irq_set_type = gic_set_type, 403 .irq_retrigger = gic_retrigger, 404 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 405 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 406 .flags = IRQCHIP_SET_TYPE_MASKED | 407 IRQCHIP_SKIP_SET_WAKE | 408 IRQCHIP_MASK_ON_SUSPEND, 409 }; 410 411 void __init gic_cascade_irq(unsigned int gic_nr, unsigned int irq) 412 { 413 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 414 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, 415 &gic_data[gic_nr]); 416 } 417 418 static u8 gic_get_cpumask(struct gic_chip_data *gic) 419 { 420 void __iomem *base = gic_data_dist_base(gic); 421 u32 mask, i; 422 423 for (i = mask = 0; i < 32; i += 4) { 424 mask = readl_relaxed(base + GIC_DIST_TARGET + i); 425 mask |= mask >> 16; 426 mask |= mask >> 8; 427 if (mask) 428 break; 429 } 430 431 if (!mask && num_possible_cpus() > 1) 432 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); 433 434 return mask; 435 } 436 437 static bool gic_check_gicv2(void __iomem *base) 438 { 439 u32 val = readl_relaxed(base + GIC_CPU_IDENT); 440 return (val & 0xff0fff) == 0x02043B; 441 } 442 443 static void gic_cpu_if_up(struct gic_chip_data *gic) 444 { 445 void __iomem *cpu_base = gic_data_cpu_base(gic); 446 u32 bypass = 0; 447 u32 mode = 0; 448 int i; 449 450 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) 451 mode = GIC_CPU_CTRL_EOImodeNS; 452 453 if (gic_check_gicv2(cpu_base)) 454 for (i = 0; i < 4; i++) 455 writel_relaxed(0, cpu_base + GIC_CPU_ACTIVEPRIO + i * 4); 456 457 /* 458 * Preserve bypass disable bits to be written back later 459 */ 460 bypass = readl(cpu_base + GIC_CPU_CTRL); 461 bypass &= GICC_DIS_BYPASS_MASK; 462 463 writel_relaxed(bypass | mode | GICC_ENABLE, cpu_base + GIC_CPU_CTRL); 464 } 465 466 467 static void gic_dist_init(struct gic_chip_data *gic) 468 { 469 unsigned int i; 470 u32 cpumask; 471 unsigned int gic_irqs = gic->gic_irqs; 472 void __iomem *base = gic_data_dist_base(gic); 473 474 writel_relaxed(GICD_DISABLE, base + GIC_DIST_CTRL); 475 476 /* 477 * Set all global interrupts to this CPU only. 478 */ 479 cpumask = gic_get_cpumask(gic); 480 cpumask |= cpumask << 8; 481 cpumask |= cpumask << 16; 482 for (i = 32; i < gic_irqs; i += 4) 483 writel_relaxed(cpumask, base + GIC_DIST_TARGET + i * 4 / 4); 484 485 gic_dist_config(base, gic_irqs, NULL); 486 487 writel_relaxed(GICD_ENABLE, base + GIC_DIST_CTRL); 488 } 489 490 static int gic_cpu_init(struct gic_chip_data *gic) 491 { 492 void __iomem *dist_base = gic_data_dist_base(gic); 493 void __iomem *base = gic_data_cpu_base(gic); 494 unsigned int cpu_mask, cpu = smp_processor_id(); 495 int i; 496 497 /* 498 * Setting up the CPU map is only relevant for the primary GIC 499 * because any nested/secondary GICs do not directly interface 500 * with the CPU(s). 501 */ 502 if (gic == &gic_data[0]) { 503 /* 504 * Get what the GIC says our CPU mask is. 505 */ 506 if (WARN_ON(cpu >= NR_GIC_CPU_IF)) 507 return -EINVAL; 508 509 gic_check_cpu_features(); 510 cpu_mask = gic_get_cpumask(gic); 511 gic_cpu_map[cpu] = cpu_mask; 512 513 /* 514 * Clear our mask from the other map entries in case they're 515 * still undefined. 516 */ 517 for (i = 0; i < NR_GIC_CPU_IF; i++) 518 if (i != cpu) 519 gic_cpu_map[i] &= ~cpu_mask; 520 } 521 522 gic_cpu_config(dist_base, 32, NULL); 523 524 writel_relaxed(GICC_INT_PRI_THRESHOLD, base + GIC_CPU_PRIMASK); 525 gic_cpu_if_up(gic); 526 527 return 0; 528 } 529 530 int gic_cpu_if_down(unsigned int gic_nr) 531 { 532 void __iomem *cpu_base; 533 u32 val = 0; 534 535 if (gic_nr >= CONFIG_ARM_GIC_MAX_NR) 536 return -EINVAL; 537 538 cpu_base = gic_data_cpu_base(&gic_data[gic_nr]); 539 val = readl(cpu_base + GIC_CPU_CTRL); 540 val &= ~GICC_ENABLE; 541 writel_relaxed(val, cpu_base + GIC_CPU_CTRL); 542 543 return 0; 544 } 545 546 #if defined(CONFIG_CPU_PM) || defined(CONFIG_ARM_GIC_PM) 547 /* 548 * Saves the GIC distributor registers during suspend or idle. Must be called 549 * with interrupts disabled but before powering down the GIC. After calling 550 * this function, no interrupts will be delivered by the GIC, and another 551 * platform-specific wakeup source must be enabled. 552 */ 553 void gic_dist_save(struct gic_chip_data *gic) 554 { 555 unsigned int gic_irqs; 556 void __iomem *dist_base; 557 int i; 558 559 if (WARN_ON(!gic)) 560 return; 561 562 gic_irqs = gic->gic_irqs; 563 dist_base = gic_data_dist_base(gic); 564 565 if (!dist_base) 566 return; 567 568 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 569 gic->saved_spi_conf[i] = 570 readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 571 572 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 573 gic->saved_spi_target[i] = 574 readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 575 576 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 577 gic->saved_spi_enable[i] = 578 readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 579 580 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) 581 gic->saved_spi_active[i] = 582 readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 583 } 584 585 /* 586 * Restores the GIC distributor registers during resume or when coming out of 587 * idle. Must be called before enabling interrupts. If a level interrupt 588 * that occurred while the GIC was suspended is still present, it will be 589 * handled normally, but any edge interrupts that occurred will not be seen by 590 * the GIC and need to be handled by the platform-specific wakeup source. 591 */ 592 void gic_dist_restore(struct gic_chip_data *gic) 593 { 594 unsigned int gic_irqs; 595 unsigned int i; 596 void __iomem *dist_base; 597 598 if (WARN_ON(!gic)) 599 return; 600 601 gic_irqs = gic->gic_irqs; 602 dist_base = gic_data_dist_base(gic); 603 604 if (!dist_base) 605 return; 606 607 writel_relaxed(GICD_DISABLE, dist_base + GIC_DIST_CTRL); 608 609 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 16); i++) 610 writel_relaxed(gic->saved_spi_conf[i], 611 dist_base + GIC_DIST_CONFIG + i * 4); 612 613 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 614 writel_relaxed(GICD_INT_DEF_PRI_X4, 615 dist_base + GIC_DIST_PRI + i * 4); 616 617 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 4); i++) 618 writel_relaxed(gic->saved_spi_target[i], 619 dist_base + GIC_DIST_TARGET + i * 4); 620 621 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 622 writel_relaxed(GICD_INT_EN_CLR_X32, 623 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 624 writel_relaxed(gic->saved_spi_enable[i], 625 dist_base + GIC_DIST_ENABLE_SET + i * 4); 626 } 627 628 for (i = 0; i < DIV_ROUND_UP(gic_irqs, 32); i++) { 629 writel_relaxed(GICD_INT_EN_CLR_X32, 630 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 631 writel_relaxed(gic->saved_spi_active[i], 632 dist_base + GIC_DIST_ACTIVE_SET + i * 4); 633 } 634 635 writel_relaxed(GICD_ENABLE, dist_base + GIC_DIST_CTRL); 636 } 637 638 void gic_cpu_save(struct gic_chip_data *gic) 639 { 640 int i; 641 u32 *ptr; 642 void __iomem *dist_base; 643 void __iomem *cpu_base; 644 645 if (WARN_ON(!gic)) 646 return; 647 648 dist_base = gic_data_dist_base(gic); 649 cpu_base = gic_data_cpu_base(gic); 650 651 if (!dist_base || !cpu_base) 652 return; 653 654 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 655 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 656 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ENABLE_SET + i * 4); 657 658 ptr = raw_cpu_ptr(gic->saved_ppi_active); 659 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) 660 ptr[i] = readl_relaxed(dist_base + GIC_DIST_ACTIVE_SET + i * 4); 661 662 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 663 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 664 ptr[i] = readl_relaxed(dist_base + GIC_DIST_CONFIG + i * 4); 665 666 } 667 668 void gic_cpu_restore(struct gic_chip_data *gic) 669 { 670 int i; 671 u32 *ptr; 672 void __iomem *dist_base; 673 void __iomem *cpu_base; 674 675 if (WARN_ON(!gic)) 676 return; 677 678 dist_base = gic_data_dist_base(gic); 679 cpu_base = gic_data_cpu_base(gic); 680 681 if (!dist_base || !cpu_base) 682 return; 683 684 ptr = raw_cpu_ptr(gic->saved_ppi_enable); 685 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 686 writel_relaxed(GICD_INT_EN_CLR_X32, 687 dist_base + GIC_DIST_ENABLE_CLEAR + i * 4); 688 writel_relaxed(ptr[i], dist_base + GIC_DIST_ENABLE_SET + i * 4); 689 } 690 691 ptr = raw_cpu_ptr(gic->saved_ppi_active); 692 for (i = 0; i < DIV_ROUND_UP(32, 32); i++) { 693 writel_relaxed(GICD_INT_EN_CLR_X32, 694 dist_base + GIC_DIST_ACTIVE_CLEAR + i * 4); 695 writel_relaxed(ptr[i], dist_base + GIC_DIST_ACTIVE_SET + i * 4); 696 } 697 698 ptr = raw_cpu_ptr(gic->saved_ppi_conf); 699 for (i = 0; i < DIV_ROUND_UP(32, 16); i++) 700 writel_relaxed(ptr[i], dist_base + GIC_DIST_CONFIG + i * 4); 701 702 for (i = 0; i < DIV_ROUND_UP(32, 4); i++) 703 writel_relaxed(GICD_INT_DEF_PRI_X4, 704 dist_base + GIC_DIST_PRI + i * 4); 705 706 writel_relaxed(GICC_INT_PRI_THRESHOLD, cpu_base + GIC_CPU_PRIMASK); 707 gic_cpu_if_up(gic); 708 } 709 710 static int gic_notifier(struct notifier_block *self, unsigned long cmd, void *v) 711 { 712 int i; 713 714 for (i = 0; i < CONFIG_ARM_GIC_MAX_NR; i++) { 715 switch (cmd) { 716 case CPU_PM_ENTER: 717 gic_cpu_save(&gic_data[i]); 718 break; 719 case CPU_PM_ENTER_FAILED: 720 case CPU_PM_EXIT: 721 gic_cpu_restore(&gic_data[i]); 722 break; 723 case CPU_CLUSTER_PM_ENTER: 724 gic_dist_save(&gic_data[i]); 725 break; 726 case CPU_CLUSTER_PM_ENTER_FAILED: 727 case CPU_CLUSTER_PM_EXIT: 728 gic_dist_restore(&gic_data[i]); 729 break; 730 } 731 } 732 733 return NOTIFY_OK; 734 } 735 736 static struct notifier_block gic_notifier_block = { 737 .notifier_call = gic_notifier, 738 }; 739 740 static int gic_pm_init(struct gic_chip_data *gic) 741 { 742 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 743 sizeof(u32)); 744 if (WARN_ON(!gic->saved_ppi_enable)) 745 return -ENOMEM; 746 747 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, 748 sizeof(u32)); 749 if (WARN_ON(!gic->saved_ppi_active)) 750 goto free_ppi_enable; 751 752 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, 753 sizeof(u32)); 754 if (WARN_ON(!gic->saved_ppi_conf)) 755 goto free_ppi_active; 756 757 if (gic == &gic_data[0]) 758 cpu_pm_register_notifier(&gic_notifier_block); 759 760 return 0; 761 762 free_ppi_active: 763 free_percpu(gic->saved_ppi_active); 764 free_ppi_enable: 765 free_percpu(gic->saved_ppi_enable); 766 767 return -ENOMEM; 768 } 769 #else 770 static int gic_pm_init(struct gic_chip_data *gic) 771 { 772 return 0; 773 } 774 #endif 775 776 #ifdef CONFIG_SMP 777 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 778 bool force) 779 { 780 void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d); 781 unsigned int cpu; 782 783 if (!force) 784 cpu = cpumask_any_and(mask_val, cpu_online_mask); 785 else 786 cpu = cpumask_first(mask_val); 787 788 if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids) 789 return -EINVAL; 790 791 writeb_relaxed(gic_cpu_map[cpu], reg); 792 irq_data_update_effective_affinity(d, cpumask_of(cpu)); 793 794 return IRQ_SET_MASK_OK_DONE; 795 } 796 797 static void gic_ipi_send_mask(struct irq_data *d, const struct cpumask *mask) 798 { 799 int cpu; 800 unsigned long flags, map = 0; 801 802 if (unlikely(nr_cpu_ids == 1)) { 803 /* Only one CPU? let's do a self-IPI... */ 804 writel_relaxed(2 << 24 | d->hwirq, 805 gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 806 return; 807 } 808 809 gic_lock_irqsave(flags); 810 811 /* Convert our logical CPU mask into a physical one. */ 812 for_each_cpu(cpu, mask) 813 map |= gic_cpu_map[cpu]; 814 815 /* 816 * Ensure that stores to Normal memory are visible to the 817 * other CPUs before they observe us issuing the IPI. 818 */ 819 dmb(ishst); 820 821 /* this always happens on GIC0 */ 822 writel_relaxed(map << 16 | d->hwirq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 823 824 gic_unlock_irqrestore(flags); 825 } 826 827 static int gic_starting_cpu(unsigned int cpu) 828 { 829 gic_cpu_init(&gic_data[0]); 830 return 0; 831 } 832 833 static __init void gic_smp_init(void) 834 { 835 struct irq_fwspec sgi_fwspec = { 836 .fwnode = gic_data[0].domain->fwnode, 837 .param_count = 1, 838 }; 839 int base_sgi; 840 841 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 842 "irqchip/arm/gic:starting", 843 gic_starting_cpu, NULL); 844 845 base_sgi = __irq_domain_alloc_irqs(gic_data[0].domain, -1, 8, 846 NUMA_NO_NODE, &sgi_fwspec, 847 false, NULL); 848 if (WARN_ON(base_sgi <= 0)) 849 return; 850 851 set_smp_ipi_range(base_sgi, 8); 852 } 853 #else 854 #define gic_smp_init() do { } while(0) 855 #define gic_set_affinity NULL 856 #define gic_ipi_send_mask NULL 857 #endif 858 859 #ifdef CONFIG_BL_SWITCHER 860 /* 861 * gic_send_sgi - send a SGI directly to given CPU interface number 862 * 863 * cpu_id: the ID for the destination CPU interface 864 * irq: the IPI number to send a SGI for 865 */ 866 void gic_send_sgi(unsigned int cpu_id, unsigned int irq) 867 { 868 BUG_ON(cpu_id >= NR_GIC_CPU_IF); 869 cpu_id = 1 << cpu_id; 870 /* this always happens on GIC0 */ 871 writel_relaxed((cpu_id << 16) | irq, gic_data_dist_base(&gic_data[0]) + GIC_DIST_SOFTINT); 872 } 873 874 /* 875 * gic_get_cpu_id - get the CPU interface ID for the specified CPU 876 * 877 * @cpu: the logical CPU number to get the GIC ID for. 878 * 879 * Return the CPU interface ID for the given logical CPU number, 880 * or -1 if the CPU number is too large or the interface ID is 881 * unknown (more than one bit set). 882 */ 883 int gic_get_cpu_id(unsigned int cpu) 884 { 885 unsigned int cpu_bit; 886 887 if (cpu >= NR_GIC_CPU_IF) 888 return -1; 889 cpu_bit = gic_cpu_map[cpu]; 890 if (cpu_bit & (cpu_bit - 1)) 891 return -1; 892 return __ffs(cpu_bit); 893 } 894 895 /* 896 * gic_migrate_target - migrate IRQs to another CPU interface 897 * 898 * @new_cpu_id: the CPU target ID to migrate IRQs to 899 * 900 * Migrate all peripheral interrupts with a target matching the current CPU 901 * to the interface corresponding to @new_cpu_id. The CPU interface mapping 902 * is also updated. Targets to other CPU interfaces are unchanged. 903 * This must be called with IRQs locally disabled. 904 */ 905 void gic_migrate_target(unsigned int new_cpu_id) 906 { 907 unsigned int cur_cpu_id, gic_irqs, gic_nr = 0; 908 void __iomem *dist_base; 909 int i, ror_val, cpu = smp_processor_id(); 910 u32 val, cur_target_mask, active_mask; 911 912 BUG_ON(gic_nr >= CONFIG_ARM_GIC_MAX_NR); 913 914 dist_base = gic_data_dist_base(&gic_data[gic_nr]); 915 if (!dist_base) 916 return; 917 gic_irqs = gic_data[gic_nr].gic_irqs; 918 919 cur_cpu_id = __ffs(gic_cpu_map[cpu]); 920 cur_target_mask = 0x01010101 << cur_cpu_id; 921 ror_val = (cur_cpu_id - new_cpu_id) & 31; 922 923 gic_lock(); 924 925 /* Update the target interface for this logical CPU */ 926 gic_cpu_map[cpu] = 1 << new_cpu_id; 927 928 /* 929 * Find all the peripheral interrupts targeting the current 930 * CPU interface and migrate them to the new CPU interface. 931 * We skip DIST_TARGET 0 to 7 as they are read-only. 932 */ 933 for (i = 8; i < DIV_ROUND_UP(gic_irqs, 4); i++) { 934 val = readl_relaxed(dist_base + GIC_DIST_TARGET + i * 4); 935 active_mask = val & cur_target_mask; 936 if (active_mask) { 937 val &= ~active_mask; 938 val |= ror32(active_mask, ror_val); 939 writel_relaxed(val, dist_base + GIC_DIST_TARGET + i*4); 940 } 941 } 942 943 gic_unlock(); 944 945 /* 946 * Now let's migrate and clear any potential SGIs that might be 947 * pending for us (cur_cpu_id). Since GIC_DIST_SGI_PENDING_SET 948 * is a banked register, we can only forward the SGI using 949 * GIC_DIST_SOFTINT. The original SGI source is lost but Linux 950 * doesn't use that information anyway. 951 * 952 * For the same reason we do not adjust SGI source information 953 * for previously sent SGIs by us to other CPUs either. 954 */ 955 for (i = 0; i < 16; i += 4) { 956 int j; 957 val = readl_relaxed(dist_base + GIC_DIST_SGI_PENDING_SET + i); 958 if (!val) 959 continue; 960 writel_relaxed(val, dist_base + GIC_DIST_SGI_PENDING_CLEAR + i); 961 for (j = i; j < i + 4; j++) { 962 if (val & 0xff) 963 writel_relaxed((1 << (new_cpu_id + 16)) | j, 964 dist_base + GIC_DIST_SOFTINT); 965 val >>= 8; 966 } 967 } 968 } 969 970 /* 971 * gic_get_sgir_physaddr - get the physical address for the SGI register 972 * 973 * Return the physical address of the SGI register to be used 974 * by some early assembly code when the kernel is not yet available. 975 */ 976 static unsigned long gic_dist_physaddr; 977 978 unsigned long gic_get_sgir_physaddr(void) 979 { 980 if (!gic_dist_physaddr) 981 return 0; 982 return gic_dist_physaddr + GIC_DIST_SOFTINT; 983 } 984 985 static void __init gic_init_physaddr(struct device_node *node) 986 { 987 struct resource res; 988 if (of_address_to_resource(node, 0, &res) == 0) { 989 gic_dist_physaddr = res.start; 990 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); 991 } 992 } 993 994 #else 995 #define gic_init_physaddr(node) do { } while (0) 996 #endif 997 998 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 999 irq_hw_number_t hw) 1000 { 1001 struct gic_chip_data *gic = d->host_data; 1002 struct irq_data *irqd = irq_desc_get_irq_data(irq_to_desc(irq)); 1003 1004 switch (hw) { 1005 case 0 ... 31: 1006 irq_set_percpu_devid(irq); 1007 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 1008 handle_percpu_devid_irq, NULL, NULL); 1009 break; 1010 default: 1011 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, 1012 handle_fasteoi_irq, NULL, NULL); 1013 irq_set_probe(irq); 1014 irqd_set_single_target(irqd); 1015 break; 1016 } 1017 1018 /* Prevents SW retriggers which mess up the ACK/EOI ordering */ 1019 irqd_set_handle_enforce_irqctx(irqd); 1020 return 0; 1021 } 1022 1023 static void gic_irq_domain_unmap(struct irq_domain *d, unsigned int irq) 1024 { 1025 } 1026 1027 static int gic_irq_domain_translate(struct irq_domain *d, 1028 struct irq_fwspec *fwspec, 1029 unsigned long *hwirq, 1030 unsigned int *type) 1031 { 1032 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { 1033 *hwirq = fwspec->param[0]; 1034 *type = IRQ_TYPE_EDGE_RISING; 1035 return 0; 1036 } 1037 1038 if (is_of_node(fwspec->fwnode)) { 1039 if (fwspec->param_count < 3) 1040 return -EINVAL; 1041 1042 switch (fwspec->param[0]) { 1043 case 0: /* SPI */ 1044 *hwirq = fwspec->param[1] + 32; 1045 break; 1046 case 1: /* PPI */ 1047 *hwirq = fwspec->param[1] + 16; 1048 break; 1049 default: 1050 return -EINVAL; 1051 } 1052 1053 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 1054 1055 /* Make it clear that broken DTs are... broken */ 1056 WARN_ON(*type == IRQ_TYPE_NONE); 1057 return 0; 1058 } 1059 1060 if (is_fwnode_irqchip(fwspec->fwnode)) { 1061 if(fwspec->param_count != 2) 1062 return -EINVAL; 1063 1064 *hwirq = fwspec->param[0]; 1065 *type = fwspec->param[1]; 1066 1067 WARN_ON(*type == IRQ_TYPE_NONE); 1068 return 0; 1069 } 1070 1071 return -EINVAL; 1072 } 1073 1074 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 1075 unsigned int nr_irqs, void *arg) 1076 { 1077 int i, ret; 1078 irq_hw_number_t hwirq; 1079 unsigned int type = IRQ_TYPE_NONE; 1080 struct irq_fwspec *fwspec = arg; 1081 1082 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 1083 if (ret) 1084 return ret; 1085 1086 for (i = 0; i < nr_irqs; i++) { 1087 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 1088 if (ret) 1089 return ret; 1090 } 1091 1092 return 0; 1093 } 1094 1095 static const struct irq_domain_ops gic_irq_domain_hierarchy_ops = { 1096 .translate = gic_irq_domain_translate, 1097 .alloc = gic_irq_domain_alloc, 1098 .free = irq_domain_free_irqs_top, 1099 }; 1100 1101 static const struct irq_domain_ops gic_irq_domain_ops = { 1102 .map = gic_irq_domain_map, 1103 .unmap = gic_irq_domain_unmap, 1104 }; 1105 1106 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, 1107 const char *name, bool use_eoimode1) 1108 { 1109 /* Initialize irq_chip */ 1110 gic->chip = gic_chip; 1111 gic->chip.name = name; 1112 gic->chip.parent_device = dev; 1113 1114 if (use_eoimode1) { 1115 gic->chip.irq_mask = gic_eoimode1_mask_irq; 1116 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; 1117 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; 1118 } 1119 1120 if (gic == &gic_data[0]) { 1121 gic->chip.irq_set_affinity = gic_set_affinity; 1122 gic->chip.ipi_send_mask = gic_ipi_send_mask; 1123 } 1124 } 1125 1126 static int gic_init_bases(struct gic_chip_data *gic, 1127 struct fwnode_handle *handle) 1128 { 1129 int gic_irqs, ret; 1130 1131 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1132 /* Frankein-GIC without banked registers... */ 1133 unsigned int cpu; 1134 1135 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); 1136 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); 1137 if (WARN_ON(!gic->dist_base.percpu_base || 1138 !gic->cpu_base.percpu_base)) { 1139 ret = -ENOMEM; 1140 goto error; 1141 } 1142 1143 for_each_possible_cpu(cpu) { 1144 u32 mpidr = cpu_logical_map(cpu); 1145 u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0); 1146 unsigned long offset = gic->percpu_offset * core_id; 1147 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = 1148 gic->raw_dist_base + offset; 1149 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = 1150 gic->raw_cpu_base + offset; 1151 } 1152 1153 enable_frankengic(); 1154 } else { 1155 /* Normal, sane GIC... */ 1156 WARN(gic->percpu_offset, 1157 "GIC_NON_BANKED not enabled, ignoring %08x offset!", 1158 gic->percpu_offset); 1159 gic->dist_base.common_base = gic->raw_dist_base; 1160 gic->cpu_base.common_base = gic->raw_cpu_base; 1161 } 1162 1163 /* 1164 * Find out how many interrupts are supported. 1165 * The GIC only supports up to 1020 interrupt sources. 1166 */ 1167 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; 1168 gic_irqs = (gic_irqs + 1) * 32; 1169 if (gic_irqs > 1020) 1170 gic_irqs = 1020; 1171 gic->gic_irqs = gic_irqs; 1172 1173 if (handle) { /* DT/ACPI */ 1174 gic->domain = irq_domain_create_linear(handle, gic_irqs, 1175 &gic_irq_domain_hierarchy_ops, 1176 gic); 1177 } else { /* Legacy support */ 1178 /* 1179 * For primary GICs, skip over SGIs. 1180 * No secondary GIC support whatsoever. 1181 */ 1182 int irq_base; 1183 1184 gic_irqs -= 16; /* calculate # of irqs to allocate */ 1185 1186 irq_base = irq_alloc_descs(16, 16, gic_irqs, 1187 numa_node_id()); 1188 if (irq_base < 0) { 1189 WARN(1, "Cannot allocate irq_descs @ IRQ16, assuming pre-allocated\n"); 1190 irq_base = 16; 1191 } 1192 1193 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, 1194 16, &gic_irq_domain_ops, gic); 1195 } 1196 1197 if (WARN_ON(!gic->domain)) { 1198 ret = -ENODEV; 1199 goto error; 1200 } 1201 1202 gic_dist_init(gic); 1203 ret = gic_cpu_init(gic); 1204 if (ret) 1205 goto error; 1206 1207 ret = gic_pm_init(gic); 1208 if (ret) 1209 goto error; 1210 1211 return 0; 1212 1213 error: 1214 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { 1215 free_percpu(gic->dist_base.percpu_base); 1216 free_percpu(gic->cpu_base.percpu_base); 1217 } 1218 1219 return ret; 1220 } 1221 1222 static int __init __gic_init_bases(struct gic_chip_data *gic, 1223 struct fwnode_handle *handle) 1224 { 1225 char *name; 1226 int i, ret; 1227 1228 if (WARN_ON(!gic || gic->domain)) 1229 return -EINVAL; 1230 1231 if (gic == &gic_data[0]) { 1232 /* 1233 * Initialize the CPU interface map to all CPUs. 1234 * It will be refined as each CPU probes its ID. 1235 * This is only necessary for the primary GIC. 1236 */ 1237 for (i = 0; i < NR_GIC_CPU_IF; i++) 1238 gic_cpu_map[i] = 0xff; 1239 1240 set_handle_irq(gic_handle_irq); 1241 if (static_branch_likely(&supports_deactivate_key)) 1242 pr_info("GIC: Using split EOI/Deactivate mode\n"); 1243 } 1244 1245 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { 1246 name = kasprintf(GFP_KERNEL, "GICv2"); 1247 gic_init_chip(gic, NULL, name, true); 1248 } else { 1249 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); 1250 gic_init_chip(gic, NULL, name, false); 1251 } 1252 1253 ret = gic_init_bases(gic, handle); 1254 if (ret) 1255 kfree(name); 1256 else if (gic == &gic_data[0]) 1257 gic_smp_init(); 1258 1259 return ret; 1260 } 1261 1262 void __init gic_init(void __iomem *dist_base, void __iomem *cpu_base) 1263 { 1264 struct gic_chip_data *gic; 1265 1266 /* 1267 * Non-DT/ACPI systems won't run a hypervisor, so let's not 1268 * bother with these... 1269 */ 1270 static_branch_disable(&supports_deactivate_key); 1271 1272 gic = &gic_data[0]; 1273 gic->raw_dist_base = dist_base; 1274 gic->raw_cpu_base = cpu_base; 1275 1276 __gic_init_bases(gic, NULL); 1277 } 1278 1279 static void gic_teardown(struct gic_chip_data *gic) 1280 { 1281 if (WARN_ON(!gic)) 1282 return; 1283 1284 if (gic->raw_dist_base) 1285 iounmap(gic->raw_dist_base); 1286 if (gic->raw_cpu_base) 1287 iounmap(gic->raw_cpu_base); 1288 } 1289 1290 #ifdef CONFIG_OF 1291 static int gic_cnt __initdata; 1292 static bool gicv2_force_probe; 1293 1294 static int __init gicv2_force_probe_cfg(char *buf) 1295 { 1296 return strtobool(buf, &gicv2_force_probe); 1297 } 1298 early_param("irqchip.gicv2_force_probe", gicv2_force_probe_cfg); 1299 1300 static bool gic_check_eoimode(struct device_node *node, void __iomem **base) 1301 { 1302 struct resource cpuif_res; 1303 1304 of_address_to_resource(node, 1, &cpuif_res); 1305 1306 if (!is_hyp_mode_available()) 1307 return false; 1308 if (resource_size(&cpuif_res) < SZ_8K) { 1309 void __iomem *alt; 1310 /* 1311 * Check for a stupid firmware that only exposes the 1312 * first page of a GICv2. 1313 */ 1314 if (!gic_check_gicv2(*base)) 1315 return false; 1316 1317 if (!gicv2_force_probe) { 1318 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); 1319 return false; 1320 } 1321 1322 alt = ioremap(cpuif_res.start, SZ_8K); 1323 if (!alt) 1324 return false; 1325 if (!gic_check_gicv2(alt + SZ_4K)) { 1326 /* 1327 * The first page was that of a GICv2, and 1328 * the second was *something*. Let's trust it 1329 * to be a GICv2, and update the mapping. 1330 */ 1331 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", 1332 &cpuif_res.start); 1333 iounmap(*base); 1334 *base = alt; 1335 return true; 1336 } 1337 1338 /* 1339 * We detected *two* initial GICv2 pages in a 1340 * row. Could be a GICv2 aliased over two 64kB 1341 * pages. Update the resource, map the iospace, and 1342 * pray. 1343 */ 1344 iounmap(alt); 1345 alt = ioremap(cpuif_res.start, SZ_128K); 1346 if (!alt) 1347 return false; 1348 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", 1349 &cpuif_res.start); 1350 cpuif_res.end = cpuif_res.start + SZ_128K -1; 1351 iounmap(*base); 1352 *base = alt; 1353 } 1354 if (resource_size(&cpuif_res) == SZ_128K) { 1355 /* 1356 * Verify that we have the first 4kB of a GICv2 1357 * aliased over the first 64kB by checking the 1358 * GICC_IIDR register on both ends. 1359 */ 1360 if (!gic_check_gicv2(*base) || 1361 !gic_check_gicv2(*base + 0xf000)) 1362 return false; 1363 1364 /* 1365 * Move the base up by 60kB, so that we have a 8kB 1366 * contiguous region, which allows us to use GICC_DIR 1367 * at its normal offset. Please pass me that bucket. 1368 */ 1369 *base += 0xf000; 1370 cpuif_res.start += 0xf000; 1371 pr_warn("GIC: Adjusting CPU interface base to %pa\n", 1372 &cpuif_res.start); 1373 } 1374 1375 return true; 1376 } 1377 1378 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) 1379 { 1380 if (!gic || !node) 1381 return -EINVAL; 1382 1383 gic->raw_dist_base = of_iomap(node, 0); 1384 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) 1385 goto error; 1386 1387 gic->raw_cpu_base = of_iomap(node, 1); 1388 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) 1389 goto error; 1390 1391 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) 1392 gic->percpu_offset = 0; 1393 1394 return 0; 1395 1396 error: 1397 gic_teardown(gic); 1398 1399 return -ENOMEM; 1400 } 1401 1402 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1403 { 1404 int ret; 1405 1406 if (!dev || !dev->of_node || !gic || !irq) 1407 return -EINVAL; 1408 1409 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); 1410 if (!*gic) 1411 return -ENOMEM; 1412 1413 gic_init_chip(*gic, dev, dev->of_node->name, false); 1414 1415 ret = gic_of_setup(*gic, dev->of_node); 1416 if (ret) 1417 return ret; 1418 1419 ret = gic_init_bases(*gic, &dev->of_node->fwnode); 1420 if (ret) { 1421 gic_teardown(*gic); 1422 return ret; 1423 } 1424 1425 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); 1426 1427 return 0; 1428 } 1429 1430 static void __init gic_of_setup_kvm_info(struct device_node *node) 1431 { 1432 int ret; 1433 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1434 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1435 1436 gic_v2_kvm_info.type = GIC_V2; 1437 1438 gic_v2_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1439 if (!gic_v2_kvm_info.maint_irq) 1440 return; 1441 1442 ret = of_address_to_resource(node, 2, vctrl_res); 1443 if (ret) 1444 return; 1445 1446 ret = of_address_to_resource(node, 3, vcpu_res); 1447 if (ret) 1448 return; 1449 1450 if (static_branch_likely(&supports_deactivate_key)) 1451 gic_set_kvm_info(&gic_v2_kvm_info); 1452 } 1453 1454 int __init 1455 gic_of_init(struct device_node *node, struct device_node *parent) 1456 { 1457 struct gic_chip_data *gic; 1458 int irq, ret; 1459 1460 if (WARN_ON(!node)) 1461 return -ENODEV; 1462 1463 if (WARN_ON(gic_cnt >= CONFIG_ARM_GIC_MAX_NR)) 1464 return -EINVAL; 1465 1466 gic = &gic_data[gic_cnt]; 1467 1468 ret = gic_of_setup(gic, node); 1469 if (ret) 1470 return ret; 1471 1472 /* 1473 * Disable split EOI/Deactivate if either HYP is not available 1474 * or the CPU interface is too small. 1475 */ 1476 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) 1477 static_branch_disable(&supports_deactivate_key); 1478 1479 ret = __gic_init_bases(gic, &node->fwnode); 1480 if (ret) { 1481 gic_teardown(gic); 1482 return ret; 1483 } 1484 1485 if (!gic_cnt) { 1486 gic_init_physaddr(node); 1487 gic_of_setup_kvm_info(node); 1488 } 1489 1490 if (parent) { 1491 irq = irq_of_parse_and_map(node, 0); 1492 gic_cascade_irq(gic_cnt, irq); 1493 } 1494 1495 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1496 gicv2m_init(&node->fwnode, gic_data[gic_cnt].domain); 1497 1498 gic_cnt++; 1499 return 0; 1500 } 1501 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init); 1502 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init); 1503 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init); 1504 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init); 1505 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init); 1506 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init); 1507 IRQCHIP_DECLARE(msm_8660_qgic, "qcom,msm-8660-qgic", gic_of_init); 1508 IRQCHIP_DECLARE(msm_qgic2, "qcom,msm-qgic2", gic_of_init); 1509 IRQCHIP_DECLARE(pl390, "arm,pl390", gic_of_init); 1510 #else 1511 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) 1512 { 1513 return -ENOTSUPP; 1514 } 1515 #endif 1516 1517 #ifdef CONFIG_ACPI 1518 static struct 1519 { 1520 phys_addr_t cpu_phys_base; 1521 u32 maint_irq; 1522 int maint_irq_mode; 1523 phys_addr_t vctrl_base; 1524 phys_addr_t vcpu_base; 1525 } acpi_data __initdata; 1526 1527 static int __init 1528 gic_acpi_parse_madt_cpu(union acpi_subtable_headers *header, 1529 const unsigned long end) 1530 { 1531 struct acpi_madt_generic_interrupt *processor; 1532 phys_addr_t gic_cpu_base; 1533 static int cpu_base_assigned; 1534 1535 processor = (struct acpi_madt_generic_interrupt *)header; 1536 1537 if (BAD_MADT_GICC_ENTRY(processor, end)) 1538 return -EINVAL; 1539 1540 /* 1541 * There is no support for non-banked GICv1/2 register in ACPI spec. 1542 * All CPU interface addresses have to be the same. 1543 */ 1544 gic_cpu_base = processor->base_address; 1545 if (cpu_base_assigned && gic_cpu_base != acpi_data.cpu_phys_base) 1546 return -EINVAL; 1547 1548 acpi_data.cpu_phys_base = gic_cpu_base; 1549 acpi_data.maint_irq = processor->vgic_interrupt; 1550 acpi_data.maint_irq_mode = (processor->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1551 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1552 acpi_data.vctrl_base = processor->gich_base_address; 1553 acpi_data.vcpu_base = processor->gicv_base_address; 1554 1555 cpu_base_assigned = 1; 1556 return 0; 1557 } 1558 1559 /* The things you have to do to just *count* something... */ 1560 static int __init acpi_dummy_func(union acpi_subtable_headers *header, 1561 const unsigned long end) 1562 { 1563 return 0; 1564 } 1565 1566 static bool __init acpi_gic_redist_is_present(void) 1567 { 1568 return acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1569 acpi_dummy_func, 0) > 0; 1570 } 1571 1572 static bool __init gic_validate_dist(struct acpi_subtable_header *header, 1573 struct acpi_probe_entry *ape) 1574 { 1575 struct acpi_madt_generic_distributor *dist; 1576 dist = (struct acpi_madt_generic_distributor *)header; 1577 1578 return (dist->version == ape->driver_data && 1579 (dist->version != ACPI_MADT_GIC_VERSION_NONE || 1580 !acpi_gic_redist_is_present())); 1581 } 1582 1583 #define ACPI_GICV2_DIST_MEM_SIZE (SZ_4K) 1584 #define ACPI_GIC_CPU_IF_MEM_SIZE (SZ_8K) 1585 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1586 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1587 1588 static void __init gic_acpi_setup_kvm_info(void) 1589 { 1590 int irq; 1591 struct resource *vctrl_res = &gic_v2_kvm_info.vctrl; 1592 struct resource *vcpu_res = &gic_v2_kvm_info.vcpu; 1593 1594 gic_v2_kvm_info.type = GIC_V2; 1595 1596 if (!acpi_data.vctrl_base) 1597 return; 1598 1599 vctrl_res->flags = IORESOURCE_MEM; 1600 vctrl_res->start = acpi_data.vctrl_base; 1601 vctrl_res->end = vctrl_res->start + ACPI_GICV2_VCTRL_MEM_SIZE - 1; 1602 1603 if (!acpi_data.vcpu_base) 1604 return; 1605 1606 vcpu_res->flags = IORESOURCE_MEM; 1607 vcpu_res->start = acpi_data.vcpu_base; 1608 vcpu_res->end = vcpu_res->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1609 1610 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1611 acpi_data.maint_irq_mode, 1612 ACPI_ACTIVE_HIGH); 1613 if (irq <= 0) 1614 return; 1615 1616 gic_v2_kvm_info.maint_irq = irq; 1617 1618 gic_set_kvm_info(&gic_v2_kvm_info); 1619 } 1620 1621 static int __init gic_v2_acpi_init(union acpi_subtable_headers *header, 1622 const unsigned long end) 1623 { 1624 struct acpi_madt_generic_distributor *dist; 1625 struct fwnode_handle *domain_handle; 1626 struct gic_chip_data *gic = &gic_data[0]; 1627 int count, ret; 1628 1629 /* Collect CPU base addresses */ 1630 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1631 gic_acpi_parse_madt_cpu, 0); 1632 if (count <= 0) { 1633 pr_err("No valid GICC entries exist\n"); 1634 return -EINVAL; 1635 } 1636 1637 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); 1638 if (!gic->raw_cpu_base) { 1639 pr_err("Unable to map GICC registers\n"); 1640 return -ENOMEM; 1641 } 1642 1643 dist = (struct acpi_madt_generic_distributor *)header; 1644 gic->raw_dist_base = ioremap(dist->base_address, 1645 ACPI_GICV2_DIST_MEM_SIZE); 1646 if (!gic->raw_dist_base) { 1647 pr_err("Unable to map GICD registers\n"); 1648 gic_teardown(gic); 1649 return -ENOMEM; 1650 } 1651 1652 /* 1653 * Disable split EOI/Deactivate if HYP is not available. ACPI 1654 * guarantees that we'll always have a GICv2, so the CPU 1655 * interface will always be the right size. 1656 */ 1657 if (!is_hyp_mode_available()) 1658 static_branch_disable(&supports_deactivate_key); 1659 1660 /* 1661 * Initialize GIC instance zero (no multi-GIC support). 1662 */ 1663 domain_handle = irq_domain_alloc_fwnode(&dist->base_address); 1664 if (!domain_handle) { 1665 pr_err("Unable to allocate domain handle\n"); 1666 gic_teardown(gic); 1667 return -ENOMEM; 1668 } 1669 1670 ret = __gic_init_bases(gic, domain_handle); 1671 if (ret) { 1672 pr_err("Failed to initialise GIC\n"); 1673 irq_domain_free_fwnode(domain_handle); 1674 gic_teardown(gic); 1675 return ret; 1676 } 1677 1678 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1679 1680 if (IS_ENABLED(CONFIG_ARM_GIC_V2M)) 1681 gicv2m_init(NULL, gic_data[0].domain); 1682 1683 if (static_branch_likely(&supports_deactivate_key)) 1684 gic_acpi_setup_kvm_info(); 1685 1686 return 0; 1687 } 1688 IRQCHIP_ACPI_DECLARE(gic_v2, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1689 gic_validate_dist, ACPI_MADT_GIC_VERSION_V2, 1690 gic_v2_acpi_init); 1691 IRQCHIP_ACPI_DECLARE(gic_v2_maybe, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1692 gic_validate_dist, ACPI_MADT_GIC_VERSION_NONE, 1693 gic_v2_acpi_init); 1694 #endif 1695