1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <linux/cpu.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/percpu.h> 26 #include <linux/slab.h> 27 28 #include <linux/irqchip/arm-gic-v3.h> 29 30 #include <asm/cputype.h> 31 #include <asm/exception.h> 32 #include <asm/smp_plat.h> 33 34 #include "irq-gic-common.h" 35 #include "irqchip.h" 36 37 struct redist_region { 38 void __iomem *redist_base; 39 phys_addr_t phys_base; 40 }; 41 42 struct gic_chip_data { 43 void __iomem *dist_base; 44 struct redist_region *redist_regions; 45 struct rdists rdists; 46 struct irq_domain *domain; 47 u64 redist_stride; 48 u32 nr_redist_regions; 49 unsigned int irq_nr; 50 }; 51 52 static struct gic_chip_data gic_data __read_mostly; 53 54 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 55 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 56 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 57 58 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 59 #define DEFAULT_PMR_VALUE 0xf0 60 61 static inline unsigned int gic_irq(struct irq_data *d) 62 { 63 return d->hwirq; 64 } 65 66 static inline int gic_irq_in_rdist(struct irq_data *d) 67 { 68 return gic_irq(d) < 32; 69 } 70 71 static inline void __iomem *gic_dist_base(struct irq_data *d) 72 { 73 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 74 return gic_data_rdist_sgi_base(); 75 76 if (d->hwirq <= 1023) /* SPI -> dist_base */ 77 return gic_data.dist_base; 78 79 return NULL; 80 } 81 82 static void gic_do_wait_for_rwp(void __iomem *base) 83 { 84 u32 count = 1000000; /* 1s! */ 85 86 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 87 count--; 88 if (!count) { 89 pr_err_ratelimited("RWP timeout, gone fishing\n"); 90 return; 91 } 92 cpu_relax(); 93 udelay(1); 94 }; 95 } 96 97 /* Wait for completion of a distributor change */ 98 static void gic_dist_wait_for_rwp(void) 99 { 100 gic_do_wait_for_rwp(gic_data.dist_base); 101 } 102 103 /* Wait for completion of a redistributor change */ 104 static void gic_redist_wait_for_rwp(void) 105 { 106 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 107 } 108 109 /* Low level accessors */ 110 static u64 __maybe_unused gic_read_iar(void) 111 { 112 u64 irqstat; 113 114 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); 115 return irqstat; 116 } 117 118 static void __maybe_unused gic_write_pmr(u64 val) 119 { 120 asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); 121 } 122 123 static void __maybe_unused gic_write_ctlr(u64 val) 124 { 125 asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); 126 isb(); 127 } 128 129 static void __maybe_unused gic_write_grpen1(u64 val) 130 { 131 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); 132 isb(); 133 } 134 135 static void __maybe_unused gic_write_sgi1r(u64 val) 136 { 137 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); 138 } 139 140 static void gic_enable_sre(void) 141 { 142 u64 val; 143 144 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 145 val |= ICC_SRE_EL1_SRE; 146 asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); 147 isb(); 148 149 /* 150 * Need to check that the SRE bit has actually been set. If 151 * not, it means that SRE is disabled at EL2. We're going to 152 * die painfully, and there is nothing we can do about it. 153 * 154 * Kindly inform the luser. 155 */ 156 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 157 if (!(val & ICC_SRE_EL1_SRE)) 158 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 159 } 160 161 static void gic_enable_redist(bool enable) 162 { 163 void __iomem *rbase; 164 u32 count = 1000000; /* 1s! */ 165 u32 val; 166 167 rbase = gic_data_rdist_rd_base(); 168 169 val = readl_relaxed(rbase + GICR_WAKER); 170 if (enable) 171 /* Wake up this CPU redistributor */ 172 val &= ~GICR_WAKER_ProcessorSleep; 173 else 174 val |= GICR_WAKER_ProcessorSleep; 175 writel_relaxed(val, rbase + GICR_WAKER); 176 177 if (!enable) { /* Check that GICR_WAKER is writeable */ 178 val = readl_relaxed(rbase + GICR_WAKER); 179 if (!(val & GICR_WAKER_ProcessorSleep)) 180 return; /* No PM support in this redistributor */ 181 } 182 183 while (count--) { 184 val = readl_relaxed(rbase + GICR_WAKER); 185 if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) 186 break; 187 cpu_relax(); 188 udelay(1); 189 }; 190 if (!count) 191 pr_err_ratelimited("redistributor failed to %s...\n", 192 enable ? "wakeup" : "sleep"); 193 } 194 195 /* 196 * Routines to disable, enable, EOI and route interrupts 197 */ 198 static void gic_poke_irq(struct irq_data *d, u32 offset) 199 { 200 u32 mask = 1 << (gic_irq(d) % 32); 201 void (*rwp_wait)(void); 202 void __iomem *base; 203 204 if (gic_irq_in_rdist(d)) { 205 base = gic_data_rdist_sgi_base(); 206 rwp_wait = gic_redist_wait_for_rwp; 207 } else { 208 base = gic_data.dist_base; 209 rwp_wait = gic_dist_wait_for_rwp; 210 } 211 212 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 213 rwp_wait(); 214 } 215 216 static void gic_mask_irq(struct irq_data *d) 217 { 218 gic_poke_irq(d, GICD_ICENABLER); 219 } 220 221 static void gic_unmask_irq(struct irq_data *d) 222 { 223 gic_poke_irq(d, GICD_ISENABLER); 224 } 225 226 static void gic_eoi_irq(struct irq_data *d) 227 { 228 gic_write_eoir(gic_irq(d)); 229 } 230 231 static int gic_set_type(struct irq_data *d, unsigned int type) 232 { 233 unsigned int irq = gic_irq(d); 234 void (*rwp_wait)(void); 235 void __iomem *base; 236 237 /* Interrupt configuration for SGIs can't be changed */ 238 if (irq < 16) 239 return -EINVAL; 240 241 if (type != IRQ_TYPE_LEVEL_HIGH && type != IRQ_TYPE_EDGE_RISING) 242 return -EINVAL; 243 244 if (gic_irq_in_rdist(d)) { 245 base = gic_data_rdist_sgi_base(); 246 rwp_wait = gic_redist_wait_for_rwp; 247 } else { 248 base = gic_data.dist_base; 249 rwp_wait = gic_dist_wait_for_rwp; 250 } 251 252 gic_configure_irq(irq, type, base, rwp_wait); 253 254 return 0; 255 } 256 257 static u64 gic_mpidr_to_affinity(u64 mpidr) 258 { 259 u64 aff; 260 261 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 262 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 263 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 264 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 265 266 return aff; 267 } 268 269 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 270 { 271 u64 irqnr; 272 273 do { 274 irqnr = gic_read_iar(); 275 276 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 277 int err; 278 err = handle_domain_irq(gic_data.domain, irqnr, regs); 279 if (err) { 280 WARN_ONCE(true, "Unexpected interrupt received!\n"); 281 gic_write_eoir(irqnr); 282 } 283 continue; 284 } 285 if (irqnr < 16) { 286 gic_write_eoir(irqnr); 287 #ifdef CONFIG_SMP 288 handle_IPI(irqnr, regs); 289 #else 290 WARN_ONCE(true, "Unexpected SGI received!\n"); 291 #endif 292 continue; 293 } 294 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 295 } 296 297 static void __init gic_dist_init(void) 298 { 299 unsigned int i; 300 u64 affinity; 301 void __iomem *base = gic_data.dist_base; 302 303 /* Disable the distributor */ 304 writel_relaxed(0, base + GICD_CTLR); 305 gic_dist_wait_for_rwp(); 306 307 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 308 309 /* Enable distributor with ARE, Group1 */ 310 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 311 base + GICD_CTLR); 312 313 /* 314 * Set all global interrupts to the boot CPU only. ARE must be 315 * enabled. 316 */ 317 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 318 for (i = 32; i < gic_data.irq_nr; i++) 319 writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); 320 } 321 322 static int gic_populate_rdist(void) 323 { 324 u64 mpidr = cpu_logical_map(smp_processor_id()); 325 u64 typer; 326 u32 aff; 327 int i; 328 329 /* 330 * Convert affinity to a 32bit value that can be matched to 331 * GICR_TYPER bits [63:32]. 332 */ 333 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 334 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 335 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 336 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 337 338 for (i = 0; i < gic_data.nr_redist_regions; i++) { 339 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 340 u32 reg; 341 342 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 343 if (reg != GIC_PIDR2_ARCH_GICv3 && 344 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 345 pr_warn("No redistributor present @%p\n", ptr); 346 break; 347 } 348 349 do { 350 typer = readq_relaxed(ptr + GICR_TYPER); 351 if ((typer >> 32) == aff) { 352 u64 offset = ptr - gic_data.redist_regions[i].redist_base; 353 gic_data_rdist_rd_base() = ptr; 354 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 355 pr_info("CPU%d: found redistributor %llx region %d:%pa\n", 356 smp_processor_id(), 357 (unsigned long long)mpidr, 358 i, &gic_data_rdist()->phys_base); 359 return 0; 360 } 361 362 if (gic_data.redist_stride) { 363 ptr += gic_data.redist_stride; 364 } else { 365 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 366 if (typer & GICR_TYPER_VLPIS) 367 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 368 } 369 } while (!(typer & GICR_TYPER_LAST)); 370 } 371 372 /* We couldn't even deal with ourselves... */ 373 WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", 374 smp_processor_id(), (unsigned long long)mpidr); 375 return -ENODEV; 376 } 377 378 static void gic_cpu_sys_reg_init(void) 379 { 380 /* Enable system registers */ 381 gic_enable_sre(); 382 383 /* Set priority mask register */ 384 gic_write_pmr(DEFAULT_PMR_VALUE); 385 386 /* EOI deactivates interrupt too (mode 0) */ 387 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 388 389 /* ... and let's hit the road... */ 390 gic_write_grpen1(1); 391 } 392 393 static int gic_dist_supports_lpis(void) 394 { 395 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 396 } 397 398 static void gic_cpu_init(void) 399 { 400 void __iomem *rbase; 401 402 /* Register ourselves with the rest of the world */ 403 if (gic_populate_rdist()) 404 return; 405 406 gic_enable_redist(true); 407 408 rbase = gic_data_rdist_sgi_base(); 409 410 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 411 412 /* Give LPIs a spin */ 413 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 414 its_cpu_init(); 415 416 /* initialise system registers */ 417 gic_cpu_sys_reg_init(); 418 } 419 420 #ifdef CONFIG_SMP 421 static int gic_peek_irq(struct irq_data *d, u32 offset) 422 { 423 u32 mask = 1 << (gic_irq(d) % 32); 424 void __iomem *base; 425 426 if (gic_irq_in_rdist(d)) 427 base = gic_data_rdist_sgi_base(); 428 else 429 base = gic_data.dist_base; 430 431 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 432 } 433 434 static int gic_secondary_init(struct notifier_block *nfb, 435 unsigned long action, void *hcpu) 436 { 437 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 438 gic_cpu_init(); 439 return NOTIFY_OK; 440 } 441 442 /* 443 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 444 * priority because the GIC needs to be up before the ARM generic timers. 445 */ 446 static struct notifier_block gic_cpu_notifier = { 447 .notifier_call = gic_secondary_init, 448 .priority = 100, 449 }; 450 451 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 452 u64 cluster_id) 453 { 454 int cpu = *base_cpu; 455 u64 mpidr = cpu_logical_map(cpu); 456 u16 tlist = 0; 457 458 while (cpu < nr_cpu_ids) { 459 /* 460 * If we ever get a cluster of more than 16 CPUs, just 461 * scream and skip that CPU. 462 */ 463 if (WARN_ON((mpidr & 0xff) >= 16)) 464 goto out; 465 466 tlist |= 1 << (mpidr & 0xf); 467 468 cpu = cpumask_next(cpu, mask); 469 if (cpu == nr_cpu_ids) 470 goto out; 471 472 mpidr = cpu_logical_map(cpu); 473 474 if (cluster_id != (mpidr & ~0xffUL)) { 475 cpu--; 476 goto out; 477 } 478 } 479 out: 480 *base_cpu = cpu; 481 return tlist; 482 } 483 484 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 485 { 486 u64 val; 487 488 val = (MPIDR_AFFINITY_LEVEL(cluster_id, 3) << 48 | 489 MPIDR_AFFINITY_LEVEL(cluster_id, 2) << 32 | 490 irq << 24 | 491 MPIDR_AFFINITY_LEVEL(cluster_id, 1) << 16 | 492 tlist); 493 494 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 495 gic_write_sgi1r(val); 496 } 497 498 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 499 { 500 int cpu; 501 502 if (WARN_ON(irq >= 16)) 503 return; 504 505 /* 506 * Ensure that stores to Normal memory are visible to the 507 * other CPUs before issuing the IPI. 508 */ 509 smp_wmb(); 510 511 for_each_cpu_mask(cpu, *mask) { 512 u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; 513 u16 tlist; 514 515 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 516 gic_send_sgi(cluster_id, tlist, irq); 517 } 518 519 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 520 isb(); 521 } 522 523 static void gic_smp_init(void) 524 { 525 set_smp_cross_call(gic_raise_softirq); 526 register_cpu_notifier(&gic_cpu_notifier); 527 } 528 529 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 530 bool force) 531 { 532 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 533 void __iomem *reg; 534 int enabled; 535 u64 val; 536 537 if (gic_irq_in_rdist(d)) 538 return -EINVAL; 539 540 /* If interrupt was enabled, disable it first */ 541 enabled = gic_peek_irq(d, GICD_ISENABLER); 542 if (enabled) 543 gic_mask_irq(d); 544 545 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 546 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 547 548 writeq_relaxed(val, reg); 549 550 /* 551 * If the interrupt was enabled, enabled it again. Otherwise, 552 * just wait for the distributor to have digested our changes. 553 */ 554 if (enabled) 555 gic_unmask_irq(d); 556 else 557 gic_dist_wait_for_rwp(); 558 559 return IRQ_SET_MASK_OK; 560 } 561 #else 562 #define gic_set_affinity NULL 563 #define gic_smp_init() do { } while(0) 564 #endif 565 566 #ifdef CONFIG_CPU_PM 567 static int gic_cpu_pm_notifier(struct notifier_block *self, 568 unsigned long cmd, void *v) 569 { 570 if (cmd == CPU_PM_EXIT) { 571 gic_enable_redist(true); 572 gic_cpu_sys_reg_init(); 573 } else if (cmd == CPU_PM_ENTER) { 574 gic_write_grpen1(0); 575 gic_enable_redist(false); 576 } 577 return NOTIFY_OK; 578 } 579 580 static struct notifier_block gic_cpu_pm_notifier_block = { 581 .notifier_call = gic_cpu_pm_notifier, 582 }; 583 584 static void gic_cpu_pm_init(void) 585 { 586 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 587 } 588 589 #else 590 static inline void gic_cpu_pm_init(void) { } 591 #endif /* CONFIG_CPU_PM */ 592 593 static struct irq_chip gic_chip = { 594 .name = "GICv3", 595 .irq_mask = gic_mask_irq, 596 .irq_unmask = gic_unmask_irq, 597 .irq_eoi = gic_eoi_irq, 598 .irq_set_type = gic_set_type, 599 .irq_set_affinity = gic_set_affinity, 600 }; 601 602 #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 603 604 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 605 irq_hw_number_t hw) 606 { 607 /* SGIs are private to the core kernel */ 608 if (hw < 16) 609 return -EPERM; 610 /* Nothing here */ 611 if (hw >= gic_data.irq_nr && hw < 8192) 612 return -EPERM; 613 /* Off limits */ 614 if (hw >= GIC_ID_NR) 615 return -EPERM; 616 617 /* PPIs */ 618 if (hw < 32) { 619 irq_set_percpu_devid(irq); 620 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 621 handle_percpu_devid_irq, NULL, NULL); 622 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 623 } 624 /* SPIs */ 625 if (hw >= 32 && hw < gic_data.irq_nr) { 626 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 627 handle_fasteoi_irq, NULL, NULL); 628 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 629 } 630 /* LPIs */ 631 if (hw >= 8192 && hw < GIC_ID_NR) { 632 if (!gic_dist_supports_lpis()) 633 return -EPERM; 634 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 635 handle_fasteoi_irq, NULL, NULL); 636 set_irq_flags(irq, IRQF_VALID); 637 } 638 639 return 0; 640 } 641 642 static int gic_irq_domain_xlate(struct irq_domain *d, 643 struct device_node *controller, 644 const u32 *intspec, unsigned int intsize, 645 unsigned long *out_hwirq, unsigned int *out_type) 646 { 647 if (d->of_node != controller) 648 return -EINVAL; 649 if (intsize < 3) 650 return -EINVAL; 651 652 switch(intspec[0]) { 653 case 0: /* SPI */ 654 *out_hwirq = intspec[1] + 32; 655 break; 656 case 1: /* PPI */ 657 *out_hwirq = intspec[1] + 16; 658 break; 659 case GIC_IRQ_TYPE_LPI: /* LPI */ 660 *out_hwirq = intspec[1]; 661 break; 662 default: 663 return -EINVAL; 664 } 665 666 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 667 return 0; 668 } 669 670 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 671 unsigned int nr_irqs, void *arg) 672 { 673 int i, ret; 674 irq_hw_number_t hwirq; 675 unsigned int type = IRQ_TYPE_NONE; 676 struct of_phandle_args *irq_data = arg; 677 678 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 679 irq_data->args_count, &hwirq, &type); 680 if (ret) 681 return ret; 682 683 for (i = 0; i < nr_irqs; i++) 684 gic_irq_domain_map(domain, virq + i, hwirq + i); 685 686 return 0; 687 } 688 689 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 690 unsigned int nr_irqs) 691 { 692 int i; 693 694 for (i = 0; i < nr_irqs; i++) { 695 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 696 irq_set_handler(virq + i, NULL); 697 irq_domain_reset_irq_data(d); 698 } 699 } 700 701 static const struct irq_domain_ops gic_irq_domain_ops = { 702 .xlate = gic_irq_domain_xlate, 703 .alloc = gic_irq_domain_alloc, 704 .free = gic_irq_domain_free, 705 }; 706 707 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 708 { 709 void __iomem *dist_base; 710 struct redist_region *rdist_regs; 711 u64 redist_stride; 712 u32 nr_redist_regions; 713 u32 typer; 714 u32 reg; 715 int gic_irqs; 716 int err; 717 int i; 718 719 dist_base = of_iomap(node, 0); 720 if (!dist_base) { 721 pr_err("%s: unable to map gic dist registers\n", 722 node->full_name); 723 return -ENXIO; 724 } 725 726 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 727 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { 728 pr_err("%s: no distributor detected, giving up\n", 729 node->full_name); 730 err = -ENODEV; 731 goto out_unmap_dist; 732 } 733 734 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 735 nr_redist_regions = 1; 736 737 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 738 if (!rdist_regs) { 739 err = -ENOMEM; 740 goto out_unmap_dist; 741 } 742 743 for (i = 0; i < nr_redist_regions; i++) { 744 struct resource res; 745 int ret; 746 747 ret = of_address_to_resource(node, 1 + i, &res); 748 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 749 if (ret || !rdist_regs[i].redist_base) { 750 pr_err("%s: couldn't map region %d\n", 751 node->full_name, i); 752 err = -ENODEV; 753 goto out_unmap_rdist; 754 } 755 rdist_regs[i].phys_base = res.start; 756 } 757 758 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 759 redist_stride = 0; 760 761 gic_data.dist_base = dist_base; 762 gic_data.redist_regions = rdist_regs; 763 gic_data.nr_redist_regions = nr_redist_regions; 764 gic_data.redist_stride = redist_stride; 765 766 /* 767 * Find out how many interrupts are supported. 768 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 769 */ 770 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 771 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 772 gic_irqs = GICD_TYPER_IRQS(typer); 773 if (gic_irqs > 1020) 774 gic_irqs = 1020; 775 gic_data.irq_nr = gic_irqs; 776 777 gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, 778 &gic_data); 779 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 780 781 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 782 err = -ENOMEM; 783 goto out_free; 784 } 785 786 set_handle_irq(gic_handle_irq); 787 788 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 789 its_init(node, &gic_data.rdists, gic_data.domain); 790 791 gic_smp_init(); 792 gic_dist_init(); 793 gic_cpu_init(); 794 gic_cpu_pm_init(); 795 796 return 0; 797 798 out_free: 799 if (gic_data.domain) 800 irq_domain_remove(gic_data.domain); 801 free_percpu(gic_data.rdists.rdist); 802 out_unmap_rdist: 803 for (i = 0; i < nr_redist_regions; i++) 804 if (rdist_regs[i].redist_base) 805 iounmap(rdist_regs[i].redist_base); 806 kfree(rdist_regs); 807 out_unmap_dist: 808 iounmap(dist_base); 809 return err; 810 } 811 812 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 813