1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define pr_fmt(fmt) "GICv3: " fmt 19 20 #include <linux/acpi.h> 21 #include <linux/cpu.h> 22 #include <linux/cpu_pm.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/irqdomain.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/percpu.h> 30 #include <linux/slab.h> 31 32 #include <linux/irqchip.h> 33 #include <linux/irqchip/arm-gic-common.h> 34 #include <linux/irqchip/arm-gic-v3.h> 35 #include <linux/irqchip/irq-partition-percpu.h> 36 37 #include <asm/cputype.h> 38 #include <asm/exception.h> 39 #include <asm/smp_plat.h> 40 #include <asm/virt.h> 41 42 #include "irq-gic-common.h" 43 44 struct redist_region { 45 void __iomem *redist_base; 46 phys_addr_t phys_base; 47 bool single_redist; 48 }; 49 50 struct gic_chip_data { 51 struct fwnode_handle *fwnode; 52 void __iomem *dist_base; 53 struct redist_region *redist_regions; 54 struct rdists rdists; 55 struct irq_domain *domain; 56 u64 redist_stride; 57 u32 nr_redist_regions; 58 unsigned int irq_nr; 59 struct partition_desc *ppi_descs[16]; 60 }; 61 62 static struct gic_chip_data gic_data __read_mostly; 63 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 64 65 static struct gic_kvm_info gic_v3_kvm_info; 66 67 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 68 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 69 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 70 71 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 72 #define DEFAULT_PMR_VALUE 0xf0 73 74 static inline unsigned int gic_irq(struct irq_data *d) 75 { 76 return d->hwirq; 77 } 78 79 static inline int gic_irq_in_rdist(struct irq_data *d) 80 { 81 return gic_irq(d) < 32; 82 } 83 84 static inline void __iomem *gic_dist_base(struct irq_data *d) 85 { 86 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 87 return gic_data_rdist_sgi_base(); 88 89 if (d->hwirq <= 1023) /* SPI -> dist_base */ 90 return gic_data.dist_base; 91 92 return NULL; 93 } 94 95 static void gic_do_wait_for_rwp(void __iomem *base) 96 { 97 u32 count = 1000000; /* 1s! */ 98 99 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 100 count--; 101 if (!count) { 102 pr_err_ratelimited("RWP timeout, gone fishing\n"); 103 return; 104 } 105 cpu_relax(); 106 udelay(1); 107 }; 108 } 109 110 /* Wait for completion of a distributor change */ 111 static void gic_dist_wait_for_rwp(void) 112 { 113 gic_do_wait_for_rwp(gic_data.dist_base); 114 } 115 116 /* Wait for completion of a redistributor change */ 117 static void gic_redist_wait_for_rwp(void) 118 { 119 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 120 } 121 122 #ifdef CONFIG_ARM64 123 124 static u64 __maybe_unused gic_read_iar(void) 125 { 126 if (cpus_have_const_cap(ARM64_WORKAROUND_CAVIUM_23154)) 127 return gic_read_iar_cavium_thunderx(); 128 else 129 return gic_read_iar_common(); 130 } 131 #endif 132 133 static void gic_enable_redist(bool enable) 134 { 135 void __iomem *rbase; 136 u32 count = 1000000; /* 1s! */ 137 u32 val; 138 139 rbase = gic_data_rdist_rd_base(); 140 141 val = readl_relaxed(rbase + GICR_WAKER); 142 if (enable) 143 /* Wake up this CPU redistributor */ 144 val &= ~GICR_WAKER_ProcessorSleep; 145 else 146 val |= GICR_WAKER_ProcessorSleep; 147 writel_relaxed(val, rbase + GICR_WAKER); 148 149 if (!enable) { /* Check that GICR_WAKER is writeable */ 150 val = readl_relaxed(rbase + GICR_WAKER); 151 if (!(val & GICR_WAKER_ProcessorSleep)) 152 return; /* No PM support in this redistributor */ 153 } 154 155 while (--count) { 156 val = readl_relaxed(rbase + GICR_WAKER); 157 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 158 break; 159 cpu_relax(); 160 udelay(1); 161 }; 162 if (!count) 163 pr_err_ratelimited("redistributor failed to %s...\n", 164 enable ? "wakeup" : "sleep"); 165 } 166 167 /* 168 * Routines to disable, enable, EOI and route interrupts 169 */ 170 static int gic_peek_irq(struct irq_data *d, u32 offset) 171 { 172 u32 mask = 1 << (gic_irq(d) % 32); 173 void __iomem *base; 174 175 if (gic_irq_in_rdist(d)) 176 base = gic_data_rdist_sgi_base(); 177 else 178 base = gic_data.dist_base; 179 180 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 181 } 182 183 static void gic_poke_irq(struct irq_data *d, u32 offset) 184 { 185 u32 mask = 1 << (gic_irq(d) % 32); 186 void (*rwp_wait)(void); 187 void __iomem *base; 188 189 if (gic_irq_in_rdist(d)) { 190 base = gic_data_rdist_sgi_base(); 191 rwp_wait = gic_redist_wait_for_rwp; 192 } else { 193 base = gic_data.dist_base; 194 rwp_wait = gic_dist_wait_for_rwp; 195 } 196 197 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 198 rwp_wait(); 199 } 200 201 static void gic_mask_irq(struct irq_data *d) 202 { 203 gic_poke_irq(d, GICD_ICENABLER); 204 } 205 206 static void gic_eoimode1_mask_irq(struct irq_data *d) 207 { 208 gic_mask_irq(d); 209 /* 210 * When masking a forwarded interrupt, make sure it is 211 * deactivated as well. 212 * 213 * This ensures that an interrupt that is getting 214 * disabled/masked will not get "stuck", because there is 215 * noone to deactivate it (guest is being terminated). 216 */ 217 if (irqd_is_forwarded_to_vcpu(d)) 218 gic_poke_irq(d, GICD_ICACTIVER); 219 } 220 221 static void gic_unmask_irq(struct irq_data *d) 222 { 223 gic_poke_irq(d, GICD_ISENABLER); 224 } 225 226 static int gic_irq_set_irqchip_state(struct irq_data *d, 227 enum irqchip_irq_state which, bool val) 228 { 229 u32 reg; 230 231 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 232 return -EINVAL; 233 234 switch (which) { 235 case IRQCHIP_STATE_PENDING: 236 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 237 break; 238 239 case IRQCHIP_STATE_ACTIVE: 240 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 241 break; 242 243 case IRQCHIP_STATE_MASKED: 244 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 245 break; 246 247 default: 248 return -EINVAL; 249 } 250 251 gic_poke_irq(d, reg); 252 return 0; 253 } 254 255 static int gic_irq_get_irqchip_state(struct irq_data *d, 256 enum irqchip_irq_state which, bool *val) 257 { 258 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 259 return -EINVAL; 260 261 switch (which) { 262 case IRQCHIP_STATE_PENDING: 263 *val = gic_peek_irq(d, GICD_ISPENDR); 264 break; 265 266 case IRQCHIP_STATE_ACTIVE: 267 *val = gic_peek_irq(d, GICD_ISACTIVER); 268 break; 269 270 case IRQCHIP_STATE_MASKED: 271 *val = !gic_peek_irq(d, GICD_ISENABLER); 272 break; 273 274 default: 275 return -EINVAL; 276 } 277 278 return 0; 279 } 280 281 static void gic_eoi_irq(struct irq_data *d) 282 { 283 gic_write_eoir(gic_irq(d)); 284 } 285 286 static void gic_eoimode1_eoi_irq(struct irq_data *d) 287 { 288 /* 289 * No need to deactivate an LPI, or an interrupt that 290 * is is getting forwarded to a vcpu. 291 */ 292 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 293 return; 294 gic_write_dir(gic_irq(d)); 295 } 296 297 static int gic_set_type(struct irq_data *d, unsigned int type) 298 { 299 unsigned int irq = gic_irq(d); 300 void (*rwp_wait)(void); 301 void __iomem *base; 302 303 /* Interrupt configuration for SGIs can't be changed */ 304 if (irq < 16) 305 return -EINVAL; 306 307 /* SPIs have restrictions on the supported types */ 308 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 309 type != IRQ_TYPE_EDGE_RISING) 310 return -EINVAL; 311 312 if (gic_irq_in_rdist(d)) { 313 base = gic_data_rdist_sgi_base(); 314 rwp_wait = gic_redist_wait_for_rwp; 315 } else { 316 base = gic_data.dist_base; 317 rwp_wait = gic_dist_wait_for_rwp; 318 } 319 320 return gic_configure_irq(irq, type, base, rwp_wait); 321 } 322 323 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 324 { 325 if (vcpu) 326 irqd_set_forwarded_to_vcpu(d); 327 else 328 irqd_clr_forwarded_to_vcpu(d); 329 return 0; 330 } 331 332 static u64 gic_mpidr_to_affinity(unsigned long mpidr) 333 { 334 u64 aff; 335 336 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 337 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 338 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 339 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 340 341 return aff; 342 } 343 344 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 345 { 346 u32 irqnr; 347 348 do { 349 irqnr = gic_read_iar(); 350 351 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 352 int err; 353 354 if (static_key_true(&supports_deactivate)) 355 gic_write_eoir(irqnr); 356 else 357 isb(); 358 359 err = handle_domain_irq(gic_data.domain, irqnr, regs); 360 if (err) { 361 WARN_ONCE(true, "Unexpected interrupt received!\n"); 362 if (static_key_true(&supports_deactivate)) { 363 if (irqnr < 8192) 364 gic_write_dir(irqnr); 365 } else { 366 gic_write_eoir(irqnr); 367 } 368 } 369 continue; 370 } 371 if (irqnr < 16) { 372 gic_write_eoir(irqnr); 373 if (static_key_true(&supports_deactivate)) 374 gic_write_dir(irqnr); 375 #ifdef CONFIG_SMP 376 /* 377 * Unlike GICv2, we don't need an smp_rmb() here. 378 * The control dependency from gic_read_iar to 379 * the ISB in gic_write_eoir is enough to ensure 380 * that any shared data read by handle_IPI will 381 * be read after the ACK. 382 */ 383 handle_IPI(irqnr, regs); 384 #else 385 WARN_ONCE(true, "Unexpected SGI received!\n"); 386 #endif 387 continue; 388 } 389 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 390 } 391 392 static void __init gic_dist_init(void) 393 { 394 unsigned int i; 395 u64 affinity; 396 void __iomem *base = gic_data.dist_base; 397 398 /* Disable the distributor */ 399 writel_relaxed(0, base + GICD_CTLR); 400 gic_dist_wait_for_rwp(); 401 402 /* 403 * Configure SPIs as non-secure Group-1. This will only matter 404 * if the GIC only has a single security state. This will not 405 * do the right thing if the kernel is running in secure mode, 406 * but that's not the intended use case anyway. 407 */ 408 for (i = 32; i < gic_data.irq_nr; i += 32) 409 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 410 411 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 412 413 /* Enable distributor with ARE, Group1 */ 414 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 415 base + GICD_CTLR); 416 417 /* 418 * Set all global interrupts to the boot CPU only. ARE must be 419 * enabled. 420 */ 421 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 422 for (i = 32; i < gic_data.irq_nr; i++) 423 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 424 } 425 426 static int gic_populate_rdist(void) 427 { 428 unsigned long mpidr = cpu_logical_map(smp_processor_id()); 429 u64 typer; 430 u32 aff; 431 int i; 432 433 /* 434 * Convert affinity to a 32bit value that can be matched to 435 * GICR_TYPER bits [63:32]. 436 */ 437 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 438 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 439 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 440 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 441 442 for (i = 0; i < gic_data.nr_redist_regions; i++) { 443 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 444 u32 reg; 445 446 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 447 if (reg != GIC_PIDR2_ARCH_GICv3 && 448 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 449 pr_warn("No redistributor present @%p\n", ptr); 450 break; 451 } 452 453 do { 454 typer = gic_read_typer(ptr + GICR_TYPER); 455 if ((typer >> 32) == aff) { 456 u64 offset = ptr - gic_data.redist_regions[i].redist_base; 457 gic_data_rdist_rd_base() = ptr; 458 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 459 pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 460 smp_processor_id(), mpidr, i, 461 &gic_data_rdist()->phys_base); 462 return 0; 463 } 464 465 if (gic_data.redist_regions[i].single_redist) 466 break; 467 468 if (gic_data.redist_stride) { 469 ptr += gic_data.redist_stride; 470 } else { 471 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 472 if (typer & GICR_TYPER_VLPIS) 473 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 474 } 475 } while (!(typer & GICR_TYPER_LAST)); 476 } 477 478 /* We couldn't even deal with ourselves... */ 479 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 480 smp_processor_id(), mpidr); 481 return -ENODEV; 482 } 483 484 static void gic_cpu_sys_reg_init(void) 485 { 486 /* 487 * Need to check that the SRE bit has actually been set. If 488 * not, it means that SRE is disabled at EL2. We're going to 489 * die painfully, and there is nothing we can do about it. 490 * 491 * Kindly inform the luser. 492 */ 493 if (!gic_enable_sre()) 494 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 495 496 /* Set priority mask register */ 497 gic_write_pmr(DEFAULT_PMR_VALUE); 498 499 /* 500 * Some firmwares hand over to the kernel with the BPR changed from 501 * its reset value (and with a value large enough to prevent 502 * any pre-emptive interrupts from working at all). Writing a zero 503 * to BPR restores is reset value. 504 */ 505 gic_write_bpr1(0); 506 507 if (static_key_true(&supports_deactivate)) { 508 /* EOI drops priority only (mode 1) */ 509 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 510 } else { 511 /* EOI deactivates interrupt too (mode 0) */ 512 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 513 } 514 515 /* ... and let's hit the road... */ 516 gic_write_grpen1(1); 517 } 518 519 static int gic_dist_supports_lpis(void) 520 { 521 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 522 } 523 524 static void gic_cpu_init(void) 525 { 526 void __iomem *rbase; 527 528 /* Register ourselves with the rest of the world */ 529 if (gic_populate_rdist()) 530 return; 531 532 gic_enable_redist(true); 533 534 rbase = gic_data_rdist_sgi_base(); 535 536 /* Configure SGIs/PPIs as non-secure Group-1 */ 537 writel_relaxed(~0, rbase + GICR_IGROUPR0); 538 539 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 540 541 /* Give LPIs a spin */ 542 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 543 its_cpu_init(); 544 545 /* initialise system registers */ 546 gic_cpu_sys_reg_init(); 547 } 548 549 #ifdef CONFIG_SMP 550 551 static int gic_starting_cpu(unsigned int cpu) 552 { 553 gic_cpu_init(); 554 return 0; 555 } 556 557 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 558 unsigned long cluster_id) 559 { 560 int next_cpu, cpu = *base_cpu; 561 unsigned long mpidr = cpu_logical_map(cpu); 562 u16 tlist = 0; 563 564 while (cpu < nr_cpu_ids) { 565 /* 566 * If we ever get a cluster of more than 16 CPUs, just 567 * scream and skip that CPU. 568 */ 569 if (WARN_ON((mpidr & 0xff) >= 16)) 570 goto out; 571 572 tlist |= 1 << (mpidr & 0xf); 573 574 next_cpu = cpumask_next(cpu, mask); 575 if (next_cpu >= nr_cpu_ids) 576 goto out; 577 cpu = next_cpu; 578 579 mpidr = cpu_logical_map(cpu); 580 581 if (cluster_id != (mpidr & ~0xffUL)) { 582 cpu--; 583 goto out; 584 } 585 } 586 out: 587 *base_cpu = cpu; 588 return tlist; 589 } 590 591 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 592 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 593 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 594 595 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 596 { 597 u64 val; 598 599 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 600 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 601 irq << ICC_SGI1R_SGI_ID_SHIFT | 602 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 603 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 604 605 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 606 gic_write_sgi1r(val); 607 } 608 609 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 610 { 611 int cpu; 612 613 if (WARN_ON(irq >= 16)) 614 return; 615 616 /* 617 * Ensure that stores to Normal memory are visible to the 618 * other CPUs before issuing the IPI. 619 */ 620 smp_wmb(); 621 622 for_each_cpu(cpu, mask) { 623 unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 624 u16 tlist; 625 626 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 627 gic_send_sgi(cluster_id, tlist, irq); 628 } 629 630 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 631 isb(); 632 } 633 634 static void gic_smp_init(void) 635 { 636 set_smp_cross_call(gic_raise_softirq); 637 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GIC_STARTING, 638 "irqchip/arm/gicv3:starting", 639 gic_starting_cpu, NULL); 640 } 641 642 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 643 bool force) 644 { 645 unsigned int cpu; 646 void __iomem *reg; 647 int enabled; 648 u64 val; 649 650 if (force) 651 cpu = cpumask_first(mask_val); 652 else 653 cpu = cpumask_any_and(mask_val, cpu_online_mask); 654 655 if (cpu >= nr_cpu_ids) 656 return -EINVAL; 657 658 if (gic_irq_in_rdist(d)) 659 return -EINVAL; 660 661 /* If interrupt was enabled, disable it first */ 662 enabled = gic_peek_irq(d, GICD_ISENABLER); 663 if (enabled) 664 gic_mask_irq(d); 665 666 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 667 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 668 669 gic_write_irouter(val, reg); 670 671 /* 672 * If the interrupt was enabled, enabled it again. Otherwise, 673 * just wait for the distributor to have digested our changes. 674 */ 675 if (enabled) 676 gic_unmask_irq(d); 677 else 678 gic_dist_wait_for_rwp(); 679 680 return IRQ_SET_MASK_OK_DONE; 681 } 682 #else 683 #define gic_set_affinity NULL 684 #define gic_smp_init() do { } while(0) 685 #endif 686 687 #ifdef CONFIG_CPU_PM 688 /* Check whether it's single security state view */ 689 static bool gic_dist_security_disabled(void) 690 { 691 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 692 } 693 694 static int gic_cpu_pm_notifier(struct notifier_block *self, 695 unsigned long cmd, void *v) 696 { 697 if (cmd == CPU_PM_EXIT) { 698 if (gic_dist_security_disabled()) 699 gic_enable_redist(true); 700 gic_cpu_sys_reg_init(); 701 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 702 gic_write_grpen1(0); 703 gic_enable_redist(false); 704 } 705 return NOTIFY_OK; 706 } 707 708 static struct notifier_block gic_cpu_pm_notifier_block = { 709 .notifier_call = gic_cpu_pm_notifier, 710 }; 711 712 static void gic_cpu_pm_init(void) 713 { 714 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 715 } 716 717 #else 718 static inline void gic_cpu_pm_init(void) { } 719 #endif /* CONFIG_CPU_PM */ 720 721 static struct irq_chip gic_chip = { 722 .name = "GICv3", 723 .irq_mask = gic_mask_irq, 724 .irq_unmask = gic_unmask_irq, 725 .irq_eoi = gic_eoi_irq, 726 .irq_set_type = gic_set_type, 727 .irq_set_affinity = gic_set_affinity, 728 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 729 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 730 .flags = IRQCHIP_SET_TYPE_MASKED, 731 }; 732 733 static struct irq_chip gic_eoimode1_chip = { 734 .name = "GICv3", 735 .irq_mask = gic_eoimode1_mask_irq, 736 .irq_unmask = gic_unmask_irq, 737 .irq_eoi = gic_eoimode1_eoi_irq, 738 .irq_set_type = gic_set_type, 739 .irq_set_affinity = gic_set_affinity, 740 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 741 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 742 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 743 .flags = IRQCHIP_SET_TYPE_MASKED, 744 }; 745 746 #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 747 748 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 749 irq_hw_number_t hw) 750 { 751 struct irq_chip *chip = &gic_chip; 752 753 if (static_key_true(&supports_deactivate)) 754 chip = &gic_eoimode1_chip; 755 756 /* SGIs are private to the core kernel */ 757 if (hw < 16) 758 return -EPERM; 759 /* Nothing here */ 760 if (hw >= gic_data.irq_nr && hw < 8192) 761 return -EPERM; 762 /* Off limits */ 763 if (hw >= GIC_ID_NR) 764 return -EPERM; 765 766 /* PPIs */ 767 if (hw < 32) { 768 irq_set_percpu_devid(irq); 769 irq_domain_set_info(d, irq, hw, chip, d->host_data, 770 handle_percpu_devid_irq, NULL, NULL); 771 irq_set_status_flags(irq, IRQ_NOAUTOEN); 772 } 773 /* SPIs */ 774 if (hw >= 32 && hw < gic_data.irq_nr) { 775 irq_domain_set_info(d, irq, hw, chip, d->host_data, 776 handle_fasteoi_irq, NULL, NULL); 777 irq_set_probe(irq); 778 } 779 /* LPIs */ 780 if (hw >= 8192 && hw < GIC_ID_NR) { 781 if (!gic_dist_supports_lpis()) 782 return -EPERM; 783 irq_domain_set_info(d, irq, hw, chip, d->host_data, 784 handle_fasteoi_irq, NULL, NULL); 785 } 786 787 return 0; 788 } 789 790 static int gic_irq_domain_translate(struct irq_domain *d, 791 struct irq_fwspec *fwspec, 792 unsigned long *hwirq, 793 unsigned int *type) 794 { 795 if (is_of_node(fwspec->fwnode)) { 796 if (fwspec->param_count < 3) 797 return -EINVAL; 798 799 switch (fwspec->param[0]) { 800 case 0: /* SPI */ 801 *hwirq = fwspec->param[1] + 32; 802 break; 803 case 1: /* PPI */ 804 *hwirq = fwspec->param[1] + 16; 805 break; 806 case GIC_IRQ_TYPE_LPI: /* LPI */ 807 *hwirq = fwspec->param[1]; 808 break; 809 default: 810 return -EINVAL; 811 } 812 813 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 814 return 0; 815 } 816 817 if (is_fwnode_irqchip(fwspec->fwnode)) { 818 if(fwspec->param_count != 2) 819 return -EINVAL; 820 821 *hwirq = fwspec->param[0]; 822 *type = fwspec->param[1]; 823 return 0; 824 } 825 826 return -EINVAL; 827 } 828 829 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 830 unsigned int nr_irqs, void *arg) 831 { 832 int i, ret; 833 irq_hw_number_t hwirq; 834 unsigned int type = IRQ_TYPE_NONE; 835 struct irq_fwspec *fwspec = arg; 836 837 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 838 if (ret) 839 return ret; 840 841 for (i = 0; i < nr_irqs; i++) { 842 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); 843 if (ret) 844 return ret; 845 } 846 847 return 0; 848 } 849 850 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 851 unsigned int nr_irqs) 852 { 853 int i; 854 855 for (i = 0; i < nr_irqs; i++) { 856 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 857 irq_set_handler(virq + i, NULL); 858 irq_domain_reset_irq_data(d); 859 } 860 } 861 862 static int gic_irq_domain_select(struct irq_domain *d, 863 struct irq_fwspec *fwspec, 864 enum irq_domain_bus_token bus_token) 865 { 866 /* Not for us */ 867 if (fwspec->fwnode != d->fwnode) 868 return 0; 869 870 /* If this is not DT, then we have a single domain */ 871 if (!is_of_node(fwspec->fwnode)) 872 return 1; 873 874 /* 875 * If this is a PPI and we have a 4th (non-null) parameter, 876 * then we need to match the partition domain. 877 */ 878 if (fwspec->param_count >= 4 && 879 fwspec->param[0] == 1 && fwspec->param[3] != 0) 880 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 881 882 return d == gic_data.domain; 883 } 884 885 static const struct irq_domain_ops gic_irq_domain_ops = { 886 .translate = gic_irq_domain_translate, 887 .alloc = gic_irq_domain_alloc, 888 .free = gic_irq_domain_free, 889 .select = gic_irq_domain_select, 890 }; 891 892 static int partition_domain_translate(struct irq_domain *d, 893 struct irq_fwspec *fwspec, 894 unsigned long *hwirq, 895 unsigned int *type) 896 { 897 struct device_node *np; 898 int ret; 899 900 np = of_find_node_by_phandle(fwspec->param[3]); 901 if (WARN_ON(!np)) 902 return -EINVAL; 903 904 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 905 of_node_to_fwnode(np)); 906 if (ret < 0) 907 return ret; 908 909 *hwirq = ret; 910 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 911 912 return 0; 913 } 914 915 static const struct irq_domain_ops partition_domain_ops = { 916 .translate = partition_domain_translate, 917 .select = gic_irq_domain_select, 918 }; 919 920 static int __init gic_init_bases(void __iomem *dist_base, 921 struct redist_region *rdist_regs, 922 u32 nr_redist_regions, 923 u64 redist_stride, 924 struct fwnode_handle *handle) 925 { 926 u32 typer; 927 int gic_irqs; 928 int err; 929 930 if (!is_hyp_mode_available()) 931 static_key_slow_dec(&supports_deactivate); 932 933 if (static_key_true(&supports_deactivate)) 934 pr_info("GIC: Using split EOI/Deactivate mode\n"); 935 936 gic_data.fwnode = handle; 937 gic_data.dist_base = dist_base; 938 gic_data.redist_regions = rdist_regs; 939 gic_data.nr_redist_regions = nr_redist_regions; 940 gic_data.redist_stride = redist_stride; 941 942 /* 943 * Find out how many interrupts are supported. 944 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 945 */ 946 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 947 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 948 gic_irqs = GICD_TYPER_IRQS(typer); 949 if (gic_irqs > 1020) 950 gic_irqs = 1020; 951 gic_data.irq_nr = gic_irqs; 952 953 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 954 &gic_data); 955 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 956 957 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 958 err = -ENOMEM; 959 goto out_free; 960 } 961 962 set_handle_irq(gic_handle_irq); 963 964 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 965 its_init(handle, &gic_data.rdists, gic_data.domain); 966 967 gic_smp_init(); 968 gic_dist_init(); 969 gic_cpu_init(); 970 gic_cpu_pm_init(); 971 972 return 0; 973 974 out_free: 975 if (gic_data.domain) 976 irq_domain_remove(gic_data.domain); 977 free_percpu(gic_data.rdists.rdist); 978 return err; 979 } 980 981 static int __init gic_validate_dist_version(void __iomem *dist_base) 982 { 983 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 984 985 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 986 return -ENODEV; 987 988 return 0; 989 } 990 991 static int get_cpu_number(struct device_node *dn) 992 { 993 const __be32 *cell; 994 u64 hwid; 995 int i; 996 997 cell = of_get_property(dn, "reg", NULL); 998 if (!cell) 999 return -1; 1000 1001 hwid = of_read_number(cell, of_n_addr_cells(dn)); 1002 1003 /* 1004 * Non affinity bits must be set to 0 in the DT 1005 */ 1006 if (hwid & ~MPIDR_HWID_BITMASK) 1007 return -1; 1008 1009 for (i = 0; i < num_possible_cpus(); i++) 1010 if (cpu_logical_map(i) == hwid) 1011 return i; 1012 1013 return -1; 1014 } 1015 1016 /* Create all possible partitions at boot time */ 1017 static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1018 { 1019 struct device_node *parts_node, *child_part; 1020 int part_idx = 0, i; 1021 int nr_parts; 1022 struct partition_affinity *parts; 1023 1024 parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); 1025 if (!parts_node) 1026 return; 1027 1028 nr_parts = of_get_child_count(parts_node); 1029 1030 if (!nr_parts) 1031 return; 1032 1033 parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1034 if (WARN_ON(!parts)) 1035 return; 1036 1037 for_each_child_of_node(parts_node, child_part) { 1038 struct partition_affinity *part; 1039 int n; 1040 1041 part = &parts[part_idx]; 1042 1043 part->partition_id = of_node_to_fwnode(child_part); 1044 1045 pr_info("GIC: PPI partition %s[%d] { ", 1046 child_part->name, part_idx); 1047 1048 n = of_property_count_elems_of_size(child_part, "affinity", 1049 sizeof(u32)); 1050 WARN_ON(n <= 0); 1051 1052 for (i = 0; i < n; i++) { 1053 int err, cpu; 1054 u32 cpu_phandle; 1055 struct device_node *cpu_node; 1056 1057 err = of_property_read_u32_index(child_part, "affinity", 1058 i, &cpu_phandle); 1059 if (WARN_ON(err)) 1060 continue; 1061 1062 cpu_node = of_find_node_by_phandle(cpu_phandle); 1063 if (WARN_ON(!cpu_node)) 1064 continue; 1065 1066 cpu = get_cpu_number(cpu_node); 1067 if (WARN_ON(cpu == -1)) 1068 continue; 1069 1070 pr_cont("%s[%d] ", cpu_node->full_name, cpu); 1071 1072 cpumask_set_cpu(cpu, &part->mask); 1073 } 1074 1075 pr_cont("}\n"); 1076 part_idx++; 1077 } 1078 1079 for (i = 0; i < 16; i++) { 1080 unsigned int irq; 1081 struct partition_desc *desc; 1082 struct irq_fwspec ppi_fwspec = { 1083 .fwnode = gic_data.fwnode, 1084 .param_count = 3, 1085 .param = { 1086 [0] = 1, 1087 [1] = i, 1088 [2] = IRQ_TYPE_NONE, 1089 }, 1090 }; 1091 1092 irq = irq_create_fwspec_mapping(&ppi_fwspec); 1093 if (WARN_ON(!irq)) 1094 continue; 1095 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1096 irq, &partition_domain_ops); 1097 if (WARN_ON(!desc)) 1098 continue; 1099 1100 gic_data.ppi_descs[i] = desc; 1101 } 1102 } 1103 1104 static void __init gic_of_setup_kvm_info(struct device_node *node) 1105 { 1106 int ret; 1107 struct resource r; 1108 u32 gicv_idx; 1109 1110 gic_v3_kvm_info.type = GIC_V3; 1111 1112 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1113 if (!gic_v3_kvm_info.maint_irq) 1114 return; 1115 1116 if (of_property_read_u32(node, "#redistributor-regions", 1117 &gicv_idx)) 1118 gicv_idx = 1; 1119 1120 gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 1121 ret = of_address_to_resource(node, gicv_idx, &r); 1122 if (!ret) 1123 gic_v3_kvm_info.vcpu = r; 1124 1125 gic_set_kvm_info(&gic_v3_kvm_info); 1126 } 1127 1128 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1129 { 1130 void __iomem *dist_base; 1131 struct redist_region *rdist_regs; 1132 u64 redist_stride; 1133 u32 nr_redist_regions; 1134 int err, i; 1135 1136 dist_base = of_iomap(node, 0); 1137 if (!dist_base) { 1138 pr_err("%s: unable to map gic dist registers\n", 1139 node->full_name); 1140 return -ENXIO; 1141 } 1142 1143 err = gic_validate_dist_version(dist_base); 1144 if (err) { 1145 pr_err("%s: no distributor detected, giving up\n", 1146 node->full_name); 1147 goto out_unmap_dist; 1148 } 1149 1150 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1151 nr_redist_regions = 1; 1152 1153 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1154 if (!rdist_regs) { 1155 err = -ENOMEM; 1156 goto out_unmap_dist; 1157 } 1158 1159 for (i = 0; i < nr_redist_regions; i++) { 1160 struct resource res; 1161 int ret; 1162 1163 ret = of_address_to_resource(node, 1 + i, &res); 1164 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1165 if (ret || !rdist_regs[i].redist_base) { 1166 pr_err("%s: couldn't map region %d\n", 1167 node->full_name, i); 1168 err = -ENODEV; 1169 goto out_unmap_rdist; 1170 } 1171 rdist_regs[i].phys_base = res.start; 1172 } 1173 1174 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1175 redist_stride = 0; 1176 1177 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1178 redist_stride, &node->fwnode); 1179 if (err) 1180 goto out_unmap_rdist; 1181 1182 gic_populate_ppi_partitions(node); 1183 gic_of_setup_kvm_info(node); 1184 return 0; 1185 1186 out_unmap_rdist: 1187 for (i = 0; i < nr_redist_regions; i++) 1188 if (rdist_regs[i].redist_base) 1189 iounmap(rdist_regs[i].redist_base); 1190 kfree(rdist_regs); 1191 out_unmap_dist: 1192 iounmap(dist_base); 1193 return err; 1194 } 1195 1196 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1197 1198 #ifdef CONFIG_ACPI 1199 static struct 1200 { 1201 void __iomem *dist_base; 1202 struct redist_region *redist_regs; 1203 u32 nr_redist_regions; 1204 bool single_redist; 1205 u32 maint_irq; 1206 int maint_irq_mode; 1207 phys_addr_t vcpu_base; 1208 } acpi_data __initdata; 1209 1210 static void __init 1211 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1212 { 1213 static int count = 0; 1214 1215 acpi_data.redist_regs[count].phys_base = phys_base; 1216 acpi_data.redist_regs[count].redist_base = redist_base; 1217 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1218 count++; 1219 } 1220 1221 static int __init 1222 gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1223 const unsigned long end) 1224 { 1225 struct acpi_madt_generic_redistributor *redist = 1226 (struct acpi_madt_generic_redistributor *)header; 1227 void __iomem *redist_base; 1228 1229 redist_base = ioremap(redist->base_address, redist->length); 1230 if (!redist_base) { 1231 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1232 return -ENOMEM; 1233 } 1234 1235 gic_acpi_register_redist(redist->base_address, redist_base); 1236 return 0; 1237 } 1238 1239 static int __init 1240 gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1241 const unsigned long end) 1242 { 1243 struct acpi_madt_generic_interrupt *gicc = 1244 (struct acpi_madt_generic_interrupt *)header; 1245 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1246 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1247 void __iomem *redist_base; 1248 1249 redist_base = ioremap(gicc->gicr_base_address, size); 1250 if (!redist_base) 1251 return -ENOMEM; 1252 1253 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1254 return 0; 1255 } 1256 1257 static int __init gic_acpi_collect_gicr_base(void) 1258 { 1259 acpi_tbl_entry_handler redist_parser; 1260 enum acpi_madt_type type; 1261 1262 if (acpi_data.single_redist) { 1263 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1264 redist_parser = gic_acpi_parse_madt_gicc; 1265 } else { 1266 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1267 redist_parser = gic_acpi_parse_madt_redist; 1268 } 1269 1270 /* Collect redistributor base addresses in GICR entries */ 1271 if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1272 return 0; 1273 1274 pr_info("No valid GICR entries exist\n"); 1275 return -ENODEV; 1276 } 1277 1278 static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1279 const unsigned long end) 1280 { 1281 /* Subtable presence means that redist exists, that's it */ 1282 return 0; 1283 } 1284 1285 static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1286 const unsigned long end) 1287 { 1288 struct acpi_madt_generic_interrupt *gicc = 1289 (struct acpi_madt_generic_interrupt *)header; 1290 1291 /* 1292 * If GICC is enabled and has valid gicr base address, then it means 1293 * GICR base is presented via GICC 1294 */ 1295 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1296 return 0; 1297 1298 return -ENODEV; 1299 } 1300 1301 static int __init gic_acpi_count_gicr_regions(void) 1302 { 1303 int count; 1304 1305 /* 1306 * Count how many redistributor regions we have. It is not allowed 1307 * to mix redistributor description, GICR and GICC subtables have to be 1308 * mutually exclusive. 1309 */ 1310 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1311 gic_acpi_match_gicr, 0); 1312 if (count > 0) { 1313 acpi_data.single_redist = false; 1314 return count; 1315 } 1316 1317 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1318 gic_acpi_match_gicc, 0); 1319 if (count > 0) 1320 acpi_data.single_redist = true; 1321 1322 return count; 1323 } 1324 1325 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1326 struct acpi_probe_entry *ape) 1327 { 1328 struct acpi_madt_generic_distributor *dist; 1329 int count; 1330 1331 dist = (struct acpi_madt_generic_distributor *)header; 1332 if (dist->version != ape->driver_data) 1333 return false; 1334 1335 /* We need to do that exercise anyway, the sooner the better */ 1336 count = gic_acpi_count_gicr_regions(); 1337 if (count <= 0) 1338 return false; 1339 1340 acpi_data.nr_redist_regions = count; 1341 return true; 1342 } 1343 1344 static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 1345 const unsigned long end) 1346 { 1347 struct acpi_madt_generic_interrupt *gicc = 1348 (struct acpi_madt_generic_interrupt *)header; 1349 int maint_irq_mode; 1350 static int first_madt = true; 1351 1352 /* Skip unusable CPUs */ 1353 if (!(gicc->flags & ACPI_MADT_ENABLED)) 1354 return 0; 1355 1356 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1357 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1358 1359 if (first_madt) { 1360 first_madt = false; 1361 1362 acpi_data.maint_irq = gicc->vgic_interrupt; 1363 acpi_data.maint_irq_mode = maint_irq_mode; 1364 acpi_data.vcpu_base = gicc->gicv_base_address; 1365 1366 return 0; 1367 } 1368 1369 /* 1370 * The maintenance interrupt and GICV should be the same for every CPU 1371 */ 1372 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 1373 (acpi_data.maint_irq_mode != maint_irq_mode) || 1374 (acpi_data.vcpu_base != gicc->gicv_base_address)) 1375 return -EINVAL; 1376 1377 return 0; 1378 } 1379 1380 static bool __init gic_acpi_collect_virt_info(void) 1381 { 1382 int count; 1383 1384 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1385 gic_acpi_parse_virt_madt_gicc, 0); 1386 1387 return (count > 0); 1388 } 1389 1390 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 1391 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1392 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1393 1394 static void __init gic_acpi_setup_kvm_info(void) 1395 { 1396 int irq; 1397 1398 if (!gic_acpi_collect_virt_info()) { 1399 pr_warn("Unable to get hardware information used for virtualization\n"); 1400 return; 1401 } 1402 1403 gic_v3_kvm_info.type = GIC_V3; 1404 1405 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1406 acpi_data.maint_irq_mode, 1407 ACPI_ACTIVE_HIGH); 1408 if (irq <= 0) 1409 return; 1410 1411 gic_v3_kvm_info.maint_irq = irq; 1412 1413 if (acpi_data.vcpu_base) { 1414 struct resource *vcpu = &gic_v3_kvm_info.vcpu; 1415 1416 vcpu->flags = IORESOURCE_MEM; 1417 vcpu->start = acpi_data.vcpu_base; 1418 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1419 } 1420 1421 gic_set_kvm_info(&gic_v3_kvm_info); 1422 } 1423 1424 static int __init 1425 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1426 { 1427 struct acpi_madt_generic_distributor *dist; 1428 struct fwnode_handle *domain_handle; 1429 size_t size; 1430 int i, err; 1431 1432 /* Get distributor base address */ 1433 dist = (struct acpi_madt_generic_distributor *)header; 1434 acpi_data.dist_base = ioremap(dist->base_address, 1435 ACPI_GICV3_DIST_MEM_SIZE); 1436 if (!acpi_data.dist_base) { 1437 pr_err("Unable to map GICD registers\n"); 1438 return -ENOMEM; 1439 } 1440 1441 err = gic_validate_dist_version(acpi_data.dist_base); 1442 if (err) { 1443 pr_err("No distributor detected at @%p, giving up", 1444 acpi_data.dist_base); 1445 goto out_dist_unmap; 1446 } 1447 1448 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1449 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1450 if (!acpi_data.redist_regs) { 1451 err = -ENOMEM; 1452 goto out_dist_unmap; 1453 } 1454 1455 err = gic_acpi_collect_gicr_base(); 1456 if (err) 1457 goto out_redist_unmap; 1458 1459 domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1460 if (!domain_handle) { 1461 err = -ENOMEM; 1462 goto out_redist_unmap; 1463 } 1464 1465 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1466 acpi_data.nr_redist_regions, 0, domain_handle); 1467 if (err) 1468 goto out_fwhandle_free; 1469 1470 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1471 gic_acpi_setup_kvm_info(); 1472 1473 return 0; 1474 1475 out_fwhandle_free: 1476 irq_domain_free_fwnode(domain_handle); 1477 out_redist_unmap: 1478 for (i = 0; i < acpi_data.nr_redist_regions; i++) 1479 if (acpi_data.redist_regs[i].redist_base) 1480 iounmap(acpi_data.redist_regs[i].redist_base); 1481 kfree(acpi_data.redist_regs); 1482 out_dist_unmap: 1483 iounmap(acpi_data.dist_base); 1484 return err; 1485 } 1486 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1487 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1488 gic_acpi_init); 1489 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1490 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1491 gic_acpi_init); 1492 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1493 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1494 gic_acpi_init); 1495 #endif 1496