1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <linux/cpu.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/percpu.h> 26 #include <linux/slab.h> 27 28 #include <linux/irqchip/arm-gic-v3.h> 29 30 #include <asm/cputype.h> 31 #include <asm/exception.h> 32 #include <asm/smp_plat.h> 33 34 #include "irq-gic-common.h" 35 #include "irqchip.h" 36 37 struct redist_region { 38 void __iomem *redist_base; 39 phys_addr_t phys_base; 40 }; 41 42 struct gic_chip_data { 43 void __iomem *dist_base; 44 struct redist_region *redist_regions; 45 struct rdists rdists; 46 struct irq_domain *domain; 47 u64 redist_stride; 48 u32 nr_redist_regions; 49 unsigned int irq_nr; 50 }; 51 52 static struct gic_chip_data gic_data __read_mostly; 53 54 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 55 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 56 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 57 58 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 59 #define DEFAULT_PMR_VALUE 0xf0 60 61 static inline unsigned int gic_irq(struct irq_data *d) 62 { 63 return d->hwirq; 64 } 65 66 static inline int gic_irq_in_rdist(struct irq_data *d) 67 { 68 return gic_irq(d) < 32; 69 } 70 71 static inline void __iomem *gic_dist_base(struct irq_data *d) 72 { 73 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 74 return gic_data_rdist_sgi_base(); 75 76 if (d->hwirq <= 1023) /* SPI -> dist_base */ 77 return gic_data.dist_base; 78 79 return NULL; 80 } 81 82 static void gic_do_wait_for_rwp(void __iomem *base) 83 { 84 u32 count = 1000000; /* 1s! */ 85 86 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 87 count--; 88 if (!count) { 89 pr_err_ratelimited("RWP timeout, gone fishing\n"); 90 return; 91 } 92 cpu_relax(); 93 udelay(1); 94 }; 95 } 96 97 /* Wait for completion of a distributor change */ 98 static void gic_dist_wait_for_rwp(void) 99 { 100 gic_do_wait_for_rwp(gic_data.dist_base); 101 } 102 103 /* Wait for completion of a redistributor change */ 104 static void gic_redist_wait_for_rwp(void) 105 { 106 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 107 } 108 109 /* Low level accessors */ 110 static u64 __maybe_unused gic_read_iar(void) 111 { 112 u64 irqstat; 113 114 asm volatile("mrs_s %0, " __stringify(ICC_IAR1_EL1) : "=r" (irqstat)); 115 return irqstat; 116 } 117 118 static void __maybe_unused gic_write_pmr(u64 val) 119 { 120 asm volatile("msr_s " __stringify(ICC_PMR_EL1) ", %0" : : "r" (val)); 121 } 122 123 static void __maybe_unused gic_write_ctlr(u64 val) 124 { 125 asm volatile("msr_s " __stringify(ICC_CTLR_EL1) ", %0" : : "r" (val)); 126 isb(); 127 } 128 129 static void __maybe_unused gic_write_grpen1(u64 val) 130 { 131 asm volatile("msr_s " __stringify(ICC_GRPEN1_EL1) ", %0" : : "r" (val)); 132 isb(); 133 } 134 135 static void __maybe_unused gic_write_sgi1r(u64 val) 136 { 137 asm volatile("msr_s " __stringify(ICC_SGI1R_EL1) ", %0" : : "r" (val)); 138 } 139 140 static void gic_enable_sre(void) 141 { 142 u64 val; 143 144 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 145 val |= ICC_SRE_EL1_SRE; 146 asm volatile("msr_s " __stringify(ICC_SRE_EL1) ", %0" : : "r" (val)); 147 isb(); 148 149 /* 150 * Need to check that the SRE bit has actually been set. If 151 * not, it means that SRE is disabled at EL2. We're going to 152 * die painfully, and there is nothing we can do about it. 153 * 154 * Kindly inform the luser. 155 */ 156 asm volatile("mrs_s %0, " __stringify(ICC_SRE_EL1) : "=r" (val)); 157 if (!(val & ICC_SRE_EL1_SRE)) 158 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 159 } 160 161 static void gic_enable_redist(bool enable) 162 { 163 void __iomem *rbase; 164 u32 count = 1000000; /* 1s! */ 165 u32 val; 166 167 rbase = gic_data_rdist_rd_base(); 168 169 val = readl_relaxed(rbase + GICR_WAKER); 170 if (enable) 171 /* Wake up this CPU redistributor */ 172 val &= ~GICR_WAKER_ProcessorSleep; 173 else 174 val |= GICR_WAKER_ProcessorSleep; 175 writel_relaxed(val, rbase + GICR_WAKER); 176 177 if (!enable) { /* Check that GICR_WAKER is writeable */ 178 val = readl_relaxed(rbase + GICR_WAKER); 179 if (!(val & GICR_WAKER_ProcessorSleep)) 180 return; /* No PM support in this redistributor */ 181 } 182 183 while (count--) { 184 val = readl_relaxed(rbase + GICR_WAKER); 185 if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) 186 break; 187 cpu_relax(); 188 udelay(1); 189 }; 190 if (!count) 191 pr_err_ratelimited("redistributor failed to %s...\n", 192 enable ? "wakeup" : "sleep"); 193 } 194 195 /* 196 * Routines to disable, enable, EOI and route interrupts 197 */ 198 static int gic_peek_irq(struct irq_data *d, u32 offset) 199 { 200 u32 mask = 1 << (gic_irq(d) % 32); 201 void __iomem *base; 202 203 if (gic_irq_in_rdist(d)) 204 base = gic_data_rdist_sgi_base(); 205 else 206 base = gic_data.dist_base; 207 208 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 209 } 210 211 static void gic_poke_irq(struct irq_data *d, u32 offset) 212 { 213 u32 mask = 1 << (gic_irq(d) % 32); 214 void (*rwp_wait)(void); 215 void __iomem *base; 216 217 if (gic_irq_in_rdist(d)) { 218 base = gic_data_rdist_sgi_base(); 219 rwp_wait = gic_redist_wait_for_rwp; 220 } else { 221 base = gic_data.dist_base; 222 rwp_wait = gic_dist_wait_for_rwp; 223 } 224 225 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 226 rwp_wait(); 227 } 228 229 static void gic_mask_irq(struct irq_data *d) 230 { 231 gic_poke_irq(d, GICD_ICENABLER); 232 } 233 234 static void gic_unmask_irq(struct irq_data *d) 235 { 236 gic_poke_irq(d, GICD_ISENABLER); 237 } 238 239 static int gic_irq_set_irqchip_state(struct irq_data *d, 240 enum irqchip_irq_state which, bool val) 241 { 242 u32 reg; 243 244 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 245 return -EINVAL; 246 247 switch (which) { 248 case IRQCHIP_STATE_PENDING: 249 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 250 break; 251 252 case IRQCHIP_STATE_ACTIVE: 253 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 254 break; 255 256 case IRQCHIP_STATE_MASKED: 257 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 258 break; 259 260 default: 261 return -EINVAL; 262 } 263 264 gic_poke_irq(d, reg); 265 return 0; 266 } 267 268 static int gic_irq_get_irqchip_state(struct irq_data *d, 269 enum irqchip_irq_state which, bool *val) 270 { 271 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 272 return -EINVAL; 273 274 switch (which) { 275 case IRQCHIP_STATE_PENDING: 276 *val = gic_peek_irq(d, GICD_ISPENDR); 277 break; 278 279 case IRQCHIP_STATE_ACTIVE: 280 *val = gic_peek_irq(d, GICD_ISACTIVER); 281 break; 282 283 case IRQCHIP_STATE_MASKED: 284 *val = !gic_peek_irq(d, GICD_ISENABLER); 285 break; 286 287 default: 288 return -EINVAL; 289 } 290 291 return 0; 292 } 293 294 static void gic_eoi_irq(struct irq_data *d) 295 { 296 gic_write_eoir(gic_irq(d)); 297 } 298 299 static int gic_set_type(struct irq_data *d, unsigned int type) 300 { 301 unsigned int irq = gic_irq(d); 302 void (*rwp_wait)(void); 303 void __iomem *base; 304 305 /* Interrupt configuration for SGIs can't be changed */ 306 if (irq < 16) 307 return -EINVAL; 308 309 /* SPIs have restrictions on the supported types */ 310 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 311 type != IRQ_TYPE_EDGE_RISING) 312 return -EINVAL; 313 314 if (gic_irq_in_rdist(d)) { 315 base = gic_data_rdist_sgi_base(); 316 rwp_wait = gic_redist_wait_for_rwp; 317 } else { 318 base = gic_data.dist_base; 319 rwp_wait = gic_dist_wait_for_rwp; 320 } 321 322 return gic_configure_irq(irq, type, base, rwp_wait); 323 } 324 325 static u64 gic_mpidr_to_affinity(u64 mpidr) 326 { 327 u64 aff; 328 329 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 330 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 331 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 332 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 333 334 return aff; 335 } 336 337 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 338 { 339 u64 irqnr; 340 341 do { 342 irqnr = gic_read_iar(); 343 344 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 345 int err; 346 err = handle_domain_irq(gic_data.domain, irqnr, regs); 347 if (err) { 348 WARN_ONCE(true, "Unexpected interrupt received!\n"); 349 gic_write_eoir(irqnr); 350 } 351 continue; 352 } 353 if (irqnr < 16) { 354 gic_write_eoir(irqnr); 355 #ifdef CONFIG_SMP 356 handle_IPI(irqnr, regs); 357 #else 358 WARN_ONCE(true, "Unexpected SGI received!\n"); 359 #endif 360 continue; 361 } 362 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 363 } 364 365 static void __init gic_dist_init(void) 366 { 367 unsigned int i; 368 u64 affinity; 369 void __iomem *base = gic_data.dist_base; 370 371 /* Disable the distributor */ 372 writel_relaxed(0, base + GICD_CTLR); 373 gic_dist_wait_for_rwp(); 374 375 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 376 377 /* Enable distributor with ARE, Group1 */ 378 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 379 base + GICD_CTLR); 380 381 /* 382 * Set all global interrupts to the boot CPU only. ARE must be 383 * enabled. 384 */ 385 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 386 for (i = 32; i < gic_data.irq_nr; i++) 387 writeq_relaxed(affinity, base + GICD_IROUTER + i * 8); 388 } 389 390 static int gic_populate_rdist(void) 391 { 392 u64 mpidr = cpu_logical_map(smp_processor_id()); 393 u64 typer; 394 u32 aff; 395 int i; 396 397 /* 398 * Convert affinity to a 32bit value that can be matched to 399 * GICR_TYPER bits [63:32]. 400 */ 401 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 402 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 403 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 404 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 405 406 for (i = 0; i < gic_data.nr_redist_regions; i++) { 407 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 408 u32 reg; 409 410 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 411 if (reg != GIC_PIDR2_ARCH_GICv3 && 412 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 413 pr_warn("No redistributor present @%p\n", ptr); 414 break; 415 } 416 417 do { 418 typer = readq_relaxed(ptr + GICR_TYPER); 419 if ((typer >> 32) == aff) { 420 u64 offset = ptr - gic_data.redist_regions[i].redist_base; 421 gic_data_rdist_rd_base() = ptr; 422 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 423 pr_info("CPU%d: found redistributor %llx region %d:%pa\n", 424 smp_processor_id(), 425 (unsigned long long)mpidr, 426 i, &gic_data_rdist()->phys_base); 427 return 0; 428 } 429 430 if (gic_data.redist_stride) { 431 ptr += gic_data.redist_stride; 432 } else { 433 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 434 if (typer & GICR_TYPER_VLPIS) 435 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 436 } 437 } while (!(typer & GICR_TYPER_LAST)); 438 } 439 440 /* We couldn't even deal with ourselves... */ 441 WARN(true, "CPU%d: mpidr %llx has no re-distributor!\n", 442 smp_processor_id(), (unsigned long long)mpidr); 443 return -ENODEV; 444 } 445 446 static void gic_cpu_sys_reg_init(void) 447 { 448 /* Enable system registers */ 449 gic_enable_sre(); 450 451 /* Set priority mask register */ 452 gic_write_pmr(DEFAULT_PMR_VALUE); 453 454 /* EOI deactivates interrupt too (mode 0) */ 455 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 456 457 /* ... and let's hit the road... */ 458 gic_write_grpen1(1); 459 } 460 461 static int gic_dist_supports_lpis(void) 462 { 463 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 464 } 465 466 static void gic_cpu_init(void) 467 { 468 void __iomem *rbase; 469 470 /* Register ourselves with the rest of the world */ 471 if (gic_populate_rdist()) 472 return; 473 474 gic_enable_redist(true); 475 476 rbase = gic_data_rdist_sgi_base(); 477 478 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 479 480 /* Give LPIs a spin */ 481 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 482 its_cpu_init(); 483 484 /* initialise system registers */ 485 gic_cpu_sys_reg_init(); 486 } 487 488 #ifdef CONFIG_SMP 489 static int gic_secondary_init(struct notifier_block *nfb, 490 unsigned long action, void *hcpu) 491 { 492 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 493 gic_cpu_init(); 494 return NOTIFY_OK; 495 } 496 497 /* 498 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 499 * priority because the GIC needs to be up before the ARM generic timers. 500 */ 501 static struct notifier_block gic_cpu_notifier = { 502 .notifier_call = gic_secondary_init, 503 .priority = 100, 504 }; 505 506 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 507 u64 cluster_id) 508 { 509 int cpu = *base_cpu; 510 u64 mpidr = cpu_logical_map(cpu); 511 u16 tlist = 0; 512 513 while (cpu < nr_cpu_ids) { 514 /* 515 * If we ever get a cluster of more than 16 CPUs, just 516 * scream and skip that CPU. 517 */ 518 if (WARN_ON((mpidr & 0xff) >= 16)) 519 goto out; 520 521 tlist |= 1 << (mpidr & 0xf); 522 523 cpu = cpumask_next(cpu, mask); 524 if (cpu >= nr_cpu_ids) 525 goto out; 526 527 mpidr = cpu_logical_map(cpu); 528 529 if (cluster_id != (mpidr & ~0xffUL)) { 530 cpu--; 531 goto out; 532 } 533 } 534 out: 535 *base_cpu = cpu; 536 return tlist; 537 } 538 539 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 540 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 541 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 542 543 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 544 { 545 u64 val; 546 547 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 548 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 549 irq << ICC_SGI1R_SGI_ID_SHIFT | 550 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 551 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 552 553 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 554 gic_write_sgi1r(val); 555 } 556 557 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 558 { 559 int cpu; 560 561 if (WARN_ON(irq >= 16)) 562 return; 563 564 /* 565 * Ensure that stores to Normal memory are visible to the 566 * other CPUs before issuing the IPI. 567 */ 568 smp_wmb(); 569 570 for_each_cpu(cpu, mask) { 571 u64 cluster_id = cpu_logical_map(cpu) & ~0xffUL; 572 u16 tlist; 573 574 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 575 gic_send_sgi(cluster_id, tlist, irq); 576 } 577 578 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 579 isb(); 580 } 581 582 static void gic_smp_init(void) 583 { 584 set_smp_cross_call(gic_raise_softirq); 585 register_cpu_notifier(&gic_cpu_notifier); 586 } 587 588 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 589 bool force) 590 { 591 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 592 void __iomem *reg; 593 int enabled; 594 u64 val; 595 596 if (gic_irq_in_rdist(d)) 597 return -EINVAL; 598 599 /* If interrupt was enabled, disable it first */ 600 enabled = gic_peek_irq(d, GICD_ISENABLER); 601 if (enabled) 602 gic_mask_irq(d); 603 604 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 605 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 606 607 writeq_relaxed(val, reg); 608 609 /* 610 * If the interrupt was enabled, enabled it again. Otherwise, 611 * just wait for the distributor to have digested our changes. 612 */ 613 if (enabled) 614 gic_unmask_irq(d); 615 else 616 gic_dist_wait_for_rwp(); 617 618 return IRQ_SET_MASK_OK; 619 } 620 #else 621 #define gic_set_affinity NULL 622 #define gic_smp_init() do { } while(0) 623 #endif 624 625 #ifdef CONFIG_CPU_PM 626 static int gic_cpu_pm_notifier(struct notifier_block *self, 627 unsigned long cmd, void *v) 628 { 629 if (cmd == CPU_PM_EXIT) { 630 gic_enable_redist(true); 631 gic_cpu_sys_reg_init(); 632 } else if (cmd == CPU_PM_ENTER) { 633 gic_write_grpen1(0); 634 gic_enable_redist(false); 635 } 636 return NOTIFY_OK; 637 } 638 639 static struct notifier_block gic_cpu_pm_notifier_block = { 640 .notifier_call = gic_cpu_pm_notifier, 641 }; 642 643 static void gic_cpu_pm_init(void) 644 { 645 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 646 } 647 648 #else 649 static inline void gic_cpu_pm_init(void) { } 650 #endif /* CONFIG_CPU_PM */ 651 652 static struct irq_chip gic_chip = { 653 .name = "GICv3", 654 .irq_mask = gic_mask_irq, 655 .irq_unmask = gic_unmask_irq, 656 .irq_eoi = gic_eoi_irq, 657 .irq_set_type = gic_set_type, 658 .irq_set_affinity = gic_set_affinity, 659 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 660 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 661 }; 662 663 #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 664 665 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 666 irq_hw_number_t hw) 667 { 668 /* SGIs are private to the core kernel */ 669 if (hw < 16) 670 return -EPERM; 671 /* Nothing here */ 672 if (hw >= gic_data.irq_nr && hw < 8192) 673 return -EPERM; 674 /* Off limits */ 675 if (hw >= GIC_ID_NR) 676 return -EPERM; 677 678 /* PPIs */ 679 if (hw < 32) { 680 irq_set_percpu_devid(irq); 681 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 682 handle_percpu_devid_irq, NULL, NULL); 683 set_irq_flags(irq, IRQF_VALID | IRQF_NOAUTOEN); 684 } 685 /* SPIs */ 686 if (hw >= 32 && hw < gic_data.irq_nr) { 687 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 688 handle_fasteoi_irq, NULL, NULL); 689 set_irq_flags(irq, IRQF_VALID | IRQF_PROBE); 690 } 691 /* LPIs */ 692 if (hw >= 8192 && hw < GIC_ID_NR) { 693 if (!gic_dist_supports_lpis()) 694 return -EPERM; 695 irq_domain_set_info(d, irq, hw, &gic_chip, d->host_data, 696 handle_fasteoi_irq, NULL, NULL); 697 set_irq_flags(irq, IRQF_VALID); 698 } 699 700 return 0; 701 } 702 703 static int gic_irq_domain_xlate(struct irq_domain *d, 704 struct device_node *controller, 705 const u32 *intspec, unsigned int intsize, 706 unsigned long *out_hwirq, unsigned int *out_type) 707 { 708 if (d->of_node != controller) 709 return -EINVAL; 710 if (intsize < 3) 711 return -EINVAL; 712 713 switch(intspec[0]) { 714 case 0: /* SPI */ 715 *out_hwirq = intspec[1] + 32; 716 break; 717 case 1: /* PPI */ 718 *out_hwirq = intspec[1] + 16; 719 break; 720 case GIC_IRQ_TYPE_LPI: /* LPI */ 721 *out_hwirq = intspec[1]; 722 break; 723 default: 724 return -EINVAL; 725 } 726 727 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 728 return 0; 729 } 730 731 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 732 unsigned int nr_irqs, void *arg) 733 { 734 int i, ret; 735 irq_hw_number_t hwirq; 736 unsigned int type = IRQ_TYPE_NONE; 737 struct of_phandle_args *irq_data = arg; 738 739 ret = gic_irq_domain_xlate(domain, irq_data->np, irq_data->args, 740 irq_data->args_count, &hwirq, &type); 741 if (ret) 742 return ret; 743 744 for (i = 0; i < nr_irqs; i++) 745 gic_irq_domain_map(domain, virq + i, hwirq + i); 746 747 return 0; 748 } 749 750 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 751 unsigned int nr_irqs) 752 { 753 int i; 754 755 for (i = 0; i < nr_irqs; i++) { 756 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 757 irq_set_handler(virq + i, NULL); 758 irq_domain_reset_irq_data(d); 759 } 760 } 761 762 static const struct irq_domain_ops gic_irq_domain_ops = { 763 .xlate = gic_irq_domain_xlate, 764 .alloc = gic_irq_domain_alloc, 765 .free = gic_irq_domain_free, 766 }; 767 768 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 769 { 770 void __iomem *dist_base; 771 struct redist_region *rdist_regs; 772 u64 redist_stride; 773 u32 nr_redist_regions; 774 u32 typer; 775 u32 reg; 776 int gic_irqs; 777 int err; 778 int i; 779 780 dist_base = of_iomap(node, 0); 781 if (!dist_base) { 782 pr_err("%s: unable to map gic dist registers\n", 783 node->full_name); 784 return -ENXIO; 785 } 786 787 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 788 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { 789 pr_err("%s: no distributor detected, giving up\n", 790 node->full_name); 791 err = -ENODEV; 792 goto out_unmap_dist; 793 } 794 795 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 796 nr_redist_regions = 1; 797 798 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 799 if (!rdist_regs) { 800 err = -ENOMEM; 801 goto out_unmap_dist; 802 } 803 804 for (i = 0; i < nr_redist_regions; i++) { 805 struct resource res; 806 int ret; 807 808 ret = of_address_to_resource(node, 1 + i, &res); 809 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 810 if (ret || !rdist_regs[i].redist_base) { 811 pr_err("%s: couldn't map region %d\n", 812 node->full_name, i); 813 err = -ENODEV; 814 goto out_unmap_rdist; 815 } 816 rdist_regs[i].phys_base = res.start; 817 } 818 819 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 820 redist_stride = 0; 821 822 gic_data.dist_base = dist_base; 823 gic_data.redist_regions = rdist_regs; 824 gic_data.nr_redist_regions = nr_redist_regions; 825 gic_data.redist_stride = redist_stride; 826 827 /* 828 * Find out how many interrupts are supported. 829 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 830 */ 831 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 832 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 833 gic_irqs = GICD_TYPER_IRQS(typer); 834 if (gic_irqs > 1020) 835 gic_irqs = 1020; 836 gic_data.irq_nr = gic_irqs; 837 838 gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, 839 &gic_data); 840 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 841 842 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 843 err = -ENOMEM; 844 goto out_free; 845 } 846 847 set_handle_irq(gic_handle_irq); 848 849 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 850 its_init(node, &gic_data.rdists, gic_data.domain); 851 852 gic_smp_init(); 853 gic_dist_init(); 854 gic_cpu_init(); 855 gic_cpu_pm_init(); 856 857 return 0; 858 859 out_free: 860 if (gic_data.domain) 861 irq_domain_remove(gic_data.domain); 862 free_percpu(gic_data.rdists.rdist); 863 out_unmap_rdist: 864 for (i = 0; i < nr_redist_regions; i++) 865 if (rdist_regs[i].redist_base) 866 iounmap(rdist_regs[i].redist_base); 867 kfree(rdist_regs); 868 out_unmap_dist: 869 iounmap(dist_base); 870 return err; 871 } 872 873 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 874