1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #define pr_fmt(fmt) "GICv3: " fmt 19 20 #include <linux/acpi.h> 21 #include <linux/cpu.h> 22 #include <linux/cpu_pm.h> 23 #include <linux/delay.h> 24 #include <linux/interrupt.h> 25 #include <linux/irqdomain.h> 26 #include <linux/of.h> 27 #include <linux/of_address.h> 28 #include <linux/of_irq.h> 29 #include <linux/percpu.h> 30 #include <linux/slab.h> 31 32 #include <linux/irqchip.h> 33 #include <linux/irqchip/arm-gic-common.h> 34 #include <linux/irqchip/arm-gic-v3.h> 35 #include <linux/irqchip/irq-partition-percpu.h> 36 37 #include <asm/cputype.h> 38 #include <asm/exception.h> 39 #include <asm/smp_plat.h> 40 #include <asm/virt.h> 41 42 #include "irq-gic-common.h" 43 44 struct redist_region { 45 void __iomem *redist_base; 46 phys_addr_t phys_base; 47 bool single_redist; 48 }; 49 50 struct gic_chip_data { 51 struct fwnode_handle *fwnode; 52 void __iomem *dist_base; 53 struct redist_region *redist_regions; 54 struct rdists rdists; 55 struct irq_domain *domain; 56 u64 redist_stride; 57 u32 nr_redist_regions; 58 unsigned int irq_nr; 59 struct partition_desc *ppi_descs[16]; 60 }; 61 62 static struct gic_chip_data gic_data __read_mostly; 63 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 64 65 static struct gic_kvm_info gic_v3_kvm_info; 66 67 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 68 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 69 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 70 71 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 72 #define DEFAULT_PMR_VALUE 0xf0 73 74 static inline unsigned int gic_irq(struct irq_data *d) 75 { 76 return d->hwirq; 77 } 78 79 static inline int gic_irq_in_rdist(struct irq_data *d) 80 { 81 return gic_irq(d) < 32; 82 } 83 84 static inline void __iomem *gic_dist_base(struct irq_data *d) 85 { 86 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 87 return gic_data_rdist_sgi_base(); 88 89 if (d->hwirq <= 1023) /* SPI -> dist_base */ 90 return gic_data.dist_base; 91 92 return NULL; 93 } 94 95 static void gic_do_wait_for_rwp(void __iomem *base) 96 { 97 u32 count = 1000000; /* 1s! */ 98 99 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 100 count--; 101 if (!count) { 102 pr_err_ratelimited("RWP timeout, gone fishing\n"); 103 return; 104 } 105 cpu_relax(); 106 udelay(1); 107 }; 108 } 109 110 /* Wait for completion of a distributor change */ 111 static void gic_dist_wait_for_rwp(void) 112 { 113 gic_do_wait_for_rwp(gic_data.dist_base); 114 } 115 116 /* Wait for completion of a redistributor change */ 117 static void gic_redist_wait_for_rwp(void) 118 { 119 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 120 } 121 122 #ifdef CONFIG_ARM64 123 static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); 124 125 static u64 __maybe_unused gic_read_iar(void) 126 { 127 if (static_branch_unlikely(&is_cavium_thunderx)) 128 return gic_read_iar_cavium_thunderx(); 129 else 130 return gic_read_iar_common(); 131 } 132 #endif 133 134 static void gic_enable_redist(bool enable) 135 { 136 void __iomem *rbase; 137 u32 count = 1000000; /* 1s! */ 138 u32 val; 139 140 rbase = gic_data_rdist_rd_base(); 141 142 val = readl_relaxed(rbase + GICR_WAKER); 143 if (enable) 144 /* Wake up this CPU redistributor */ 145 val &= ~GICR_WAKER_ProcessorSleep; 146 else 147 val |= GICR_WAKER_ProcessorSleep; 148 writel_relaxed(val, rbase + GICR_WAKER); 149 150 if (!enable) { /* Check that GICR_WAKER is writeable */ 151 val = readl_relaxed(rbase + GICR_WAKER); 152 if (!(val & GICR_WAKER_ProcessorSleep)) 153 return; /* No PM support in this redistributor */ 154 } 155 156 while (count--) { 157 val = readl_relaxed(rbase + GICR_WAKER); 158 if (enable ^ (bool)(val & GICR_WAKER_ChildrenAsleep)) 159 break; 160 cpu_relax(); 161 udelay(1); 162 }; 163 if (!count) 164 pr_err_ratelimited("redistributor failed to %s...\n", 165 enable ? "wakeup" : "sleep"); 166 } 167 168 /* 169 * Routines to disable, enable, EOI and route interrupts 170 */ 171 static int gic_peek_irq(struct irq_data *d, u32 offset) 172 { 173 u32 mask = 1 << (gic_irq(d) % 32); 174 void __iomem *base; 175 176 if (gic_irq_in_rdist(d)) 177 base = gic_data_rdist_sgi_base(); 178 else 179 base = gic_data.dist_base; 180 181 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 182 } 183 184 static void gic_poke_irq(struct irq_data *d, u32 offset) 185 { 186 u32 mask = 1 << (gic_irq(d) % 32); 187 void (*rwp_wait)(void); 188 void __iomem *base; 189 190 if (gic_irq_in_rdist(d)) { 191 base = gic_data_rdist_sgi_base(); 192 rwp_wait = gic_redist_wait_for_rwp; 193 } else { 194 base = gic_data.dist_base; 195 rwp_wait = gic_dist_wait_for_rwp; 196 } 197 198 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 199 rwp_wait(); 200 } 201 202 static void gic_mask_irq(struct irq_data *d) 203 { 204 gic_poke_irq(d, GICD_ICENABLER); 205 } 206 207 static void gic_eoimode1_mask_irq(struct irq_data *d) 208 { 209 gic_mask_irq(d); 210 /* 211 * When masking a forwarded interrupt, make sure it is 212 * deactivated as well. 213 * 214 * This ensures that an interrupt that is getting 215 * disabled/masked will not get "stuck", because there is 216 * noone to deactivate it (guest is being terminated). 217 */ 218 if (irqd_is_forwarded_to_vcpu(d)) 219 gic_poke_irq(d, GICD_ICACTIVER); 220 } 221 222 static void gic_unmask_irq(struct irq_data *d) 223 { 224 gic_poke_irq(d, GICD_ISENABLER); 225 } 226 227 static int gic_irq_set_irqchip_state(struct irq_data *d, 228 enum irqchip_irq_state which, bool val) 229 { 230 u32 reg; 231 232 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 233 return -EINVAL; 234 235 switch (which) { 236 case IRQCHIP_STATE_PENDING: 237 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 238 break; 239 240 case IRQCHIP_STATE_ACTIVE: 241 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 242 break; 243 244 case IRQCHIP_STATE_MASKED: 245 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 246 break; 247 248 default: 249 return -EINVAL; 250 } 251 252 gic_poke_irq(d, reg); 253 return 0; 254 } 255 256 static int gic_irq_get_irqchip_state(struct irq_data *d, 257 enum irqchip_irq_state which, bool *val) 258 { 259 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 260 return -EINVAL; 261 262 switch (which) { 263 case IRQCHIP_STATE_PENDING: 264 *val = gic_peek_irq(d, GICD_ISPENDR); 265 break; 266 267 case IRQCHIP_STATE_ACTIVE: 268 *val = gic_peek_irq(d, GICD_ISACTIVER); 269 break; 270 271 case IRQCHIP_STATE_MASKED: 272 *val = !gic_peek_irq(d, GICD_ISENABLER); 273 break; 274 275 default: 276 return -EINVAL; 277 } 278 279 return 0; 280 } 281 282 static void gic_eoi_irq(struct irq_data *d) 283 { 284 gic_write_eoir(gic_irq(d)); 285 } 286 287 static void gic_eoimode1_eoi_irq(struct irq_data *d) 288 { 289 /* 290 * No need to deactivate an LPI, or an interrupt that 291 * is is getting forwarded to a vcpu. 292 */ 293 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 294 return; 295 gic_write_dir(gic_irq(d)); 296 } 297 298 static int gic_set_type(struct irq_data *d, unsigned int type) 299 { 300 unsigned int irq = gic_irq(d); 301 void (*rwp_wait)(void); 302 void __iomem *base; 303 304 /* Interrupt configuration for SGIs can't be changed */ 305 if (irq < 16) 306 return -EINVAL; 307 308 /* SPIs have restrictions on the supported types */ 309 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 310 type != IRQ_TYPE_EDGE_RISING) 311 return -EINVAL; 312 313 if (gic_irq_in_rdist(d)) { 314 base = gic_data_rdist_sgi_base(); 315 rwp_wait = gic_redist_wait_for_rwp; 316 } else { 317 base = gic_data.dist_base; 318 rwp_wait = gic_dist_wait_for_rwp; 319 } 320 321 return gic_configure_irq(irq, type, base, rwp_wait); 322 } 323 324 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 325 { 326 if (vcpu) 327 irqd_set_forwarded_to_vcpu(d); 328 else 329 irqd_clr_forwarded_to_vcpu(d); 330 return 0; 331 } 332 333 static u64 gic_mpidr_to_affinity(unsigned long mpidr) 334 { 335 u64 aff; 336 337 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 338 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 339 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 340 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 341 342 return aff; 343 } 344 345 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 346 { 347 u32 irqnr; 348 349 do { 350 irqnr = gic_read_iar(); 351 352 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 353 int err; 354 355 if (static_key_true(&supports_deactivate)) 356 gic_write_eoir(irqnr); 357 358 err = handle_domain_irq(gic_data.domain, irqnr, regs); 359 if (err) { 360 WARN_ONCE(true, "Unexpected interrupt received!\n"); 361 if (static_key_true(&supports_deactivate)) { 362 if (irqnr < 8192) 363 gic_write_dir(irqnr); 364 } else { 365 gic_write_eoir(irqnr); 366 } 367 } 368 continue; 369 } 370 if (irqnr < 16) { 371 gic_write_eoir(irqnr); 372 if (static_key_true(&supports_deactivate)) 373 gic_write_dir(irqnr); 374 #ifdef CONFIG_SMP 375 /* 376 * Unlike GICv2, we don't need an smp_rmb() here. 377 * The control dependency from gic_read_iar to 378 * the ISB in gic_write_eoir is enough to ensure 379 * that any shared data read by handle_IPI will 380 * be read after the ACK. 381 */ 382 handle_IPI(irqnr, regs); 383 #else 384 WARN_ONCE(true, "Unexpected SGI received!\n"); 385 #endif 386 continue; 387 } 388 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 389 } 390 391 static void __init gic_dist_init(void) 392 { 393 unsigned int i; 394 u64 affinity; 395 void __iomem *base = gic_data.dist_base; 396 397 /* Disable the distributor */ 398 writel_relaxed(0, base + GICD_CTLR); 399 gic_dist_wait_for_rwp(); 400 401 /* 402 * Configure SPIs as non-secure Group-1. This will only matter 403 * if the GIC only has a single security state. This will not 404 * do the right thing if the kernel is running in secure mode, 405 * but that's not the intended use case anyway. 406 */ 407 for (i = 32; i < gic_data.irq_nr; i += 32) 408 writel_relaxed(~0, base + GICD_IGROUPR + i / 8); 409 410 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 411 412 /* Enable distributor with ARE, Group1 */ 413 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 414 base + GICD_CTLR); 415 416 /* 417 * Set all global interrupts to the boot CPU only. ARE must be 418 * enabled. 419 */ 420 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 421 for (i = 32; i < gic_data.irq_nr; i++) 422 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 423 } 424 425 static int gic_populate_rdist(void) 426 { 427 unsigned long mpidr = cpu_logical_map(smp_processor_id()); 428 u64 typer; 429 u32 aff; 430 int i; 431 432 /* 433 * Convert affinity to a 32bit value that can be matched to 434 * GICR_TYPER bits [63:32]. 435 */ 436 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 437 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 438 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 439 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 440 441 for (i = 0; i < gic_data.nr_redist_regions; i++) { 442 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 443 u32 reg; 444 445 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 446 if (reg != GIC_PIDR2_ARCH_GICv3 && 447 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 448 pr_warn("No redistributor present @%p\n", ptr); 449 break; 450 } 451 452 do { 453 typer = gic_read_typer(ptr + GICR_TYPER); 454 if ((typer >> 32) == aff) { 455 u64 offset = ptr - gic_data.redist_regions[i].redist_base; 456 gic_data_rdist_rd_base() = ptr; 457 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 458 pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 459 smp_processor_id(), mpidr, i, 460 &gic_data_rdist()->phys_base); 461 return 0; 462 } 463 464 if (gic_data.redist_regions[i].single_redist) 465 break; 466 467 if (gic_data.redist_stride) { 468 ptr += gic_data.redist_stride; 469 } else { 470 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 471 if (typer & GICR_TYPER_VLPIS) 472 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 473 } 474 } while (!(typer & GICR_TYPER_LAST)); 475 } 476 477 /* We couldn't even deal with ourselves... */ 478 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 479 smp_processor_id(), mpidr); 480 return -ENODEV; 481 } 482 483 static void gic_cpu_sys_reg_init(void) 484 { 485 /* 486 * Need to check that the SRE bit has actually been set. If 487 * not, it means that SRE is disabled at EL2. We're going to 488 * die painfully, and there is nothing we can do about it. 489 * 490 * Kindly inform the luser. 491 */ 492 if (!gic_enable_sre()) 493 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 494 495 /* Set priority mask register */ 496 gic_write_pmr(DEFAULT_PMR_VALUE); 497 498 if (static_key_true(&supports_deactivate)) { 499 /* EOI drops priority only (mode 1) */ 500 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 501 } else { 502 /* EOI deactivates interrupt too (mode 0) */ 503 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 504 } 505 506 /* ... and let's hit the road... */ 507 gic_write_grpen1(1); 508 } 509 510 static int gic_dist_supports_lpis(void) 511 { 512 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 513 } 514 515 static void gic_cpu_init(void) 516 { 517 void __iomem *rbase; 518 519 /* Register ourselves with the rest of the world */ 520 if (gic_populate_rdist()) 521 return; 522 523 gic_enable_redist(true); 524 525 rbase = gic_data_rdist_sgi_base(); 526 527 /* Configure SGIs/PPIs as non-secure Group-1 */ 528 writel_relaxed(~0, rbase + GICR_IGROUPR0); 529 530 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 531 532 /* Give LPIs a spin */ 533 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 534 its_cpu_init(); 535 536 /* initialise system registers */ 537 gic_cpu_sys_reg_init(); 538 } 539 540 #ifdef CONFIG_SMP 541 542 static int gic_starting_cpu(unsigned int cpu) 543 { 544 gic_cpu_init(); 545 return 0; 546 } 547 548 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 549 unsigned long cluster_id) 550 { 551 int cpu = *base_cpu; 552 unsigned long mpidr = cpu_logical_map(cpu); 553 u16 tlist = 0; 554 555 while (cpu < nr_cpu_ids) { 556 /* 557 * If we ever get a cluster of more than 16 CPUs, just 558 * scream and skip that CPU. 559 */ 560 if (WARN_ON((mpidr & 0xff) >= 16)) 561 goto out; 562 563 tlist |= 1 << (mpidr & 0xf); 564 565 cpu = cpumask_next(cpu, mask); 566 if (cpu >= nr_cpu_ids) 567 goto out; 568 569 mpidr = cpu_logical_map(cpu); 570 571 if (cluster_id != (mpidr & ~0xffUL)) { 572 cpu--; 573 goto out; 574 } 575 } 576 out: 577 *base_cpu = cpu; 578 return tlist; 579 } 580 581 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 582 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 583 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 584 585 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 586 { 587 u64 val; 588 589 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 590 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 591 irq << ICC_SGI1R_SGI_ID_SHIFT | 592 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 593 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 594 595 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 596 gic_write_sgi1r(val); 597 } 598 599 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 600 { 601 int cpu; 602 603 if (WARN_ON(irq >= 16)) 604 return; 605 606 /* 607 * Ensure that stores to Normal memory are visible to the 608 * other CPUs before issuing the IPI. 609 */ 610 smp_wmb(); 611 612 for_each_cpu(cpu, mask) { 613 unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 614 u16 tlist; 615 616 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 617 gic_send_sgi(cluster_id, tlist, irq); 618 } 619 620 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 621 isb(); 622 } 623 624 static void gic_smp_init(void) 625 { 626 set_smp_cross_call(gic_raise_softirq); 627 cpuhp_setup_state_nocalls(CPUHP_AP_IRQ_GICV3_STARTING, 628 "AP_IRQ_GICV3_STARTING", gic_starting_cpu, 629 NULL); 630 } 631 632 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 633 bool force) 634 { 635 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 636 void __iomem *reg; 637 int enabled; 638 u64 val; 639 640 if (gic_irq_in_rdist(d)) 641 return -EINVAL; 642 643 /* If interrupt was enabled, disable it first */ 644 enabled = gic_peek_irq(d, GICD_ISENABLER); 645 if (enabled) 646 gic_mask_irq(d); 647 648 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 649 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 650 651 gic_write_irouter(val, reg); 652 653 /* 654 * If the interrupt was enabled, enabled it again. Otherwise, 655 * just wait for the distributor to have digested our changes. 656 */ 657 if (enabled) 658 gic_unmask_irq(d); 659 else 660 gic_dist_wait_for_rwp(); 661 662 return IRQ_SET_MASK_OK_DONE; 663 } 664 #else 665 #define gic_set_affinity NULL 666 #define gic_smp_init() do { } while(0) 667 #endif 668 669 #ifdef CONFIG_CPU_PM 670 /* Check whether it's single security state view */ 671 static bool gic_dist_security_disabled(void) 672 { 673 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; 674 } 675 676 static int gic_cpu_pm_notifier(struct notifier_block *self, 677 unsigned long cmd, void *v) 678 { 679 if (cmd == CPU_PM_EXIT) { 680 if (gic_dist_security_disabled()) 681 gic_enable_redist(true); 682 gic_cpu_sys_reg_init(); 683 } else if (cmd == CPU_PM_ENTER && gic_dist_security_disabled()) { 684 gic_write_grpen1(0); 685 gic_enable_redist(false); 686 } 687 return NOTIFY_OK; 688 } 689 690 static struct notifier_block gic_cpu_pm_notifier_block = { 691 .notifier_call = gic_cpu_pm_notifier, 692 }; 693 694 static void gic_cpu_pm_init(void) 695 { 696 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 697 } 698 699 #else 700 static inline void gic_cpu_pm_init(void) { } 701 #endif /* CONFIG_CPU_PM */ 702 703 static struct irq_chip gic_chip = { 704 .name = "GICv3", 705 .irq_mask = gic_mask_irq, 706 .irq_unmask = gic_unmask_irq, 707 .irq_eoi = gic_eoi_irq, 708 .irq_set_type = gic_set_type, 709 .irq_set_affinity = gic_set_affinity, 710 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 711 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 712 .flags = IRQCHIP_SET_TYPE_MASKED, 713 }; 714 715 static struct irq_chip gic_eoimode1_chip = { 716 .name = "GICv3", 717 .irq_mask = gic_eoimode1_mask_irq, 718 .irq_unmask = gic_unmask_irq, 719 .irq_eoi = gic_eoimode1_eoi_irq, 720 .irq_set_type = gic_set_type, 721 .irq_set_affinity = gic_set_affinity, 722 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 723 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 724 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 725 .flags = IRQCHIP_SET_TYPE_MASKED, 726 }; 727 728 #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 729 730 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 731 irq_hw_number_t hw) 732 { 733 struct irq_chip *chip = &gic_chip; 734 735 if (static_key_true(&supports_deactivate)) 736 chip = &gic_eoimode1_chip; 737 738 /* SGIs are private to the core kernel */ 739 if (hw < 16) 740 return -EPERM; 741 /* Nothing here */ 742 if (hw >= gic_data.irq_nr && hw < 8192) 743 return -EPERM; 744 /* Off limits */ 745 if (hw >= GIC_ID_NR) 746 return -EPERM; 747 748 /* PPIs */ 749 if (hw < 32) { 750 irq_set_percpu_devid(irq); 751 irq_domain_set_info(d, irq, hw, chip, d->host_data, 752 handle_percpu_devid_irq, NULL, NULL); 753 irq_set_status_flags(irq, IRQ_NOAUTOEN); 754 } 755 /* SPIs */ 756 if (hw >= 32 && hw < gic_data.irq_nr) { 757 irq_domain_set_info(d, irq, hw, chip, d->host_data, 758 handle_fasteoi_irq, NULL, NULL); 759 irq_set_probe(irq); 760 } 761 /* LPIs */ 762 if (hw >= 8192 && hw < GIC_ID_NR) { 763 if (!gic_dist_supports_lpis()) 764 return -EPERM; 765 irq_domain_set_info(d, irq, hw, chip, d->host_data, 766 handle_fasteoi_irq, NULL, NULL); 767 } 768 769 return 0; 770 } 771 772 static int gic_irq_domain_translate(struct irq_domain *d, 773 struct irq_fwspec *fwspec, 774 unsigned long *hwirq, 775 unsigned int *type) 776 { 777 if (is_of_node(fwspec->fwnode)) { 778 if (fwspec->param_count < 3) 779 return -EINVAL; 780 781 switch (fwspec->param[0]) { 782 case 0: /* SPI */ 783 *hwirq = fwspec->param[1] + 32; 784 break; 785 case 1: /* PPI */ 786 *hwirq = fwspec->param[1] + 16; 787 break; 788 case GIC_IRQ_TYPE_LPI: /* LPI */ 789 *hwirq = fwspec->param[1]; 790 break; 791 default: 792 return -EINVAL; 793 } 794 795 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 796 return 0; 797 } 798 799 if (is_fwnode_irqchip(fwspec->fwnode)) { 800 if(fwspec->param_count != 2) 801 return -EINVAL; 802 803 *hwirq = fwspec->param[0]; 804 *type = fwspec->param[1]; 805 return 0; 806 } 807 808 return -EINVAL; 809 } 810 811 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 812 unsigned int nr_irqs, void *arg) 813 { 814 int i, ret; 815 irq_hw_number_t hwirq; 816 unsigned int type = IRQ_TYPE_NONE; 817 struct irq_fwspec *fwspec = arg; 818 819 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 820 if (ret) 821 return ret; 822 823 for (i = 0; i < nr_irqs; i++) 824 gic_irq_domain_map(domain, virq + i, hwirq + i); 825 826 return 0; 827 } 828 829 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 830 unsigned int nr_irqs) 831 { 832 int i; 833 834 for (i = 0; i < nr_irqs; i++) { 835 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 836 irq_set_handler(virq + i, NULL); 837 irq_domain_reset_irq_data(d); 838 } 839 } 840 841 static int gic_irq_domain_select(struct irq_domain *d, 842 struct irq_fwspec *fwspec, 843 enum irq_domain_bus_token bus_token) 844 { 845 /* Not for us */ 846 if (fwspec->fwnode != d->fwnode) 847 return 0; 848 849 /* If this is not DT, then we have a single domain */ 850 if (!is_of_node(fwspec->fwnode)) 851 return 1; 852 853 /* 854 * If this is a PPI and we have a 4th (non-null) parameter, 855 * then we need to match the partition domain. 856 */ 857 if (fwspec->param_count >= 4 && 858 fwspec->param[0] == 1 && fwspec->param[3] != 0) 859 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); 860 861 return d == gic_data.domain; 862 } 863 864 static const struct irq_domain_ops gic_irq_domain_ops = { 865 .translate = gic_irq_domain_translate, 866 .alloc = gic_irq_domain_alloc, 867 .free = gic_irq_domain_free, 868 .select = gic_irq_domain_select, 869 }; 870 871 static int partition_domain_translate(struct irq_domain *d, 872 struct irq_fwspec *fwspec, 873 unsigned long *hwirq, 874 unsigned int *type) 875 { 876 struct device_node *np; 877 int ret; 878 879 np = of_find_node_by_phandle(fwspec->param[3]); 880 if (WARN_ON(!np)) 881 return -EINVAL; 882 883 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], 884 of_node_to_fwnode(np)); 885 if (ret < 0) 886 return ret; 887 888 *hwirq = ret; 889 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 890 891 return 0; 892 } 893 894 static const struct irq_domain_ops partition_domain_ops = { 895 .translate = partition_domain_translate, 896 .select = gic_irq_domain_select, 897 }; 898 899 static void gicv3_enable_quirks(void) 900 { 901 #ifdef CONFIG_ARM64 902 if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) 903 static_branch_enable(&is_cavium_thunderx); 904 #endif 905 } 906 907 static int __init gic_init_bases(void __iomem *dist_base, 908 struct redist_region *rdist_regs, 909 u32 nr_redist_regions, 910 u64 redist_stride, 911 struct fwnode_handle *handle) 912 { 913 struct device_node *node; 914 u32 typer; 915 int gic_irqs; 916 int err; 917 918 if (!is_hyp_mode_available()) 919 static_key_slow_dec(&supports_deactivate); 920 921 if (static_key_true(&supports_deactivate)) 922 pr_info("GIC: Using split EOI/Deactivate mode\n"); 923 924 gic_data.fwnode = handle; 925 gic_data.dist_base = dist_base; 926 gic_data.redist_regions = rdist_regs; 927 gic_data.nr_redist_regions = nr_redist_regions; 928 gic_data.redist_stride = redist_stride; 929 930 gicv3_enable_quirks(); 931 932 /* 933 * Find out how many interrupts are supported. 934 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 935 */ 936 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 937 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 938 gic_irqs = GICD_TYPER_IRQS(typer); 939 if (gic_irqs > 1020) 940 gic_irqs = 1020; 941 gic_data.irq_nr = gic_irqs; 942 943 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, 944 &gic_data); 945 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 946 947 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 948 err = -ENOMEM; 949 goto out_free; 950 } 951 952 set_handle_irq(gic_handle_irq); 953 954 node = to_of_node(handle); 955 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis() && 956 node) /* Temp hack to prevent ITS init for ACPI */ 957 its_init(node, &gic_data.rdists, gic_data.domain); 958 959 gic_smp_init(); 960 gic_dist_init(); 961 gic_cpu_init(); 962 gic_cpu_pm_init(); 963 964 return 0; 965 966 out_free: 967 if (gic_data.domain) 968 irq_domain_remove(gic_data.domain); 969 free_percpu(gic_data.rdists.rdist); 970 return err; 971 } 972 973 static int __init gic_validate_dist_version(void __iomem *dist_base) 974 { 975 u32 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 976 977 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) 978 return -ENODEV; 979 980 return 0; 981 } 982 983 static int get_cpu_number(struct device_node *dn) 984 { 985 const __be32 *cell; 986 u64 hwid; 987 int i; 988 989 cell = of_get_property(dn, "reg", NULL); 990 if (!cell) 991 return -1; 992 993 hwid = of_read_number(cell, of_n_addr_cells(dn)); 994 995 /* 996 * Non affinity bits must be set to 0 in the DT 997 */ 998 if (hwid & ~MPIDR_HWID_BITMASK) 999 return -1; 1000 1001 for (i = 0; i < num_possible_cpus(); i++) 1002 if (cpu_logical_map(i) == hwid) 1003 return i; 1004 1005 return -1; 1006 } 1007 1008 /* Create all possible partitions at boot time */ 1009 static void __init gic_populate_ppi_partitions(struct device_node *gic_node) 1010 { 1011 struct device_node *parts_node, *child_part; 1012 int part_idx = 0, i; 1013 int nr_parts; 1014 struct partition_affinity *parts; 1015 1016 parts_node = of_find_node_by_name(gic_node, "ppi-partitions"); 1017 if (!parts_node) 1018 return; 1019 1020 nr_parts = of_get_child_count(parts_node); 1021 1022 if (!nr_parts) 1023 return; 1024 1025 parts = kzalloc(sizeof(*parts) * nr_parts, GFP_KERNEL); 1026 if (WARN_ON(!parts)) 1027 return; 1028 1029 for_each_child_of_node(parts_node, child_part) { 1030 struct partition_affinity *part; 1031 int n; 1032 1033 part = &parts[part_idx]; 1034 1035 part->partition_id = of_node_to_fwnode(child_part); 1036 1037 pr_info("GIC: PPI partition %s[%d] { ", 1038 child_part->name, part_idx); 1039 1040 n = of_property_count_elems_of_size(child_part, "affinity", 1041 sizeof(u32)); 1042 WARN_ON(n <= 0); 1043 1044 for (i = 0; i < n; i++) { 1045 int err, cpu; 1046 u32 cpu_phandle; 1047 struct device_node *cpu_node; 1048 1049 err = of_property_read_u32_index(child_part, "affinity", 1050 i, &cpu_phandle); 1051 if (WARN_ON(err)) 1052 continue; 1053 1054 cpu_node = of_find_node_by_phandle(cpu_phandle); 1055 if (WARN_ON(!cpu_node)) 1056 continue; 1057 1058 cpu = get_cpu_number(cpu_node); 1059 if (WARN_ON(cpu == -1)) 1060 continue; 1061 1062 pr_cont("%s[%d] ", cpu_node->full_name, cpu); 1063 1064 cpumask_set_cpu(cpu, &part->mask); 1065 } 1066 1067 pr_cont("}\n"); 1068 part_idx++; 1069 } 1070 1071 for (i = 0; i < 16; i++) { 1072 unsigned int irq; 1073 struct partition_desc *desc; 1074 struct irq_fwspec ppi_fwspec = { 1075 .fwnode = gic_data.fwnode, 1076 .param_count = 3, 1077 .param = { 1078 [0] = 1, 1079 [1] = i, 1080 [2] = IRQ_TYPE_NONE, 1081 }, 1082 }; 1083 1084 irq = irq_create_fwspec_mapping(&ppi_fwspec); 1085 if (WARN_ON(!irq)) 1086 continue; 1087 desc = partition_create_desc(gic_data.fwnode, parts, nr_parts, 1088 irq, &partition_domain_ops); 1089 if (WARN_ON(!desc)) 1090 continue; 1091 1092 gic_data.ppi_descs[i] = desc; 1093 } 1094 } 1095 1096 static void __init gic_of_setup_kvm_info(struct device_node *node) 1097 { 1098 int ret; 1099 struct resource r; 1100 u32 gicv_idx; 1101 1102 gic_v3_kvm_info.type = GIC_V3; 1103 1104 gic_v3_kvm_info.maint_irq = irq_of_parse_and_map(node, 0); 1105 if (!gic_v3_kvm_info.maint_irq) 1106 return; 1107 1108 if (of_property_read_u32(node, "#redistributor-regions", 1109 &gicv_idx)) 1110 gicv_idx = 1; 1111 1112 gicv_idx += 3; /* Also skip GICD, GICC, GICH */ 1113 ret = of_address_to_resource(node, gicv_idx, &r); 1114 if (!ret) 1115 gic_v3_kvm_info.vcpu = r; 1116 1117 gic_set_kvm_info(&gic_v3_kvm_info); 1118 } 1119 1120 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 1121 { 1122 void __iomem *dist_base; 1123 struct redist_region *rdist_regs; 1124 u64 redist_stride; 1125 u32 nr_redist_regions; 1126 int err, i; 1127 1128 dist_base = of_iomap(node, 0); 1129 if (!dist_base) { 1130 pr_err("%s: unable to map gic dist registers\n", 1131 node->full_name); 1132 return -ENXIO; 1133 } 1134 1135 err = gic_validate_dist_version(dist_base); 1136 if (err) { 1137 pr_err("%s: no distributor detected, giving up\n", 1138 node->full_name); 1139 goto out_unmap_dist; 1140 } 1141 1142 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 1143 nr_redist_regions = 1; 1144 1145 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 1146 if (!rdist_regs) { 1147 err = -ENOMEM; 1148 goto out_unmap_dist; 1149 } 1150 1151 for (i = 0; i < nr_redist_regions; i++) { 1152 struct resource res; 1153 int ret; 1154 1155 ret = of_address_to_resource(node, 1 + i, &res); 1156 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 1157 if (ret || !rdist_regs[i].redist_base) { 1158 pr_err("%s: couldn't map region %d\n", 1159 node->full_name, i); 1160 err = -ENODEV; 1161 goto out_unmap_rdist; 1162 } 1163 rdist_regs[i].phys_base = res.start; 1164 } 1165 1166 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 1167 redist_stride = 0; 1168 1169 err = gic_init_bases(dist_base, rdist_regs, nr_redist_regions, 1170 redist_stride, &node->fwnode); 1171 if (err) 1172 goto out_unmap_rdist; 1173 1174 gic_populate_ppi_partitions(node); 1175 gic_of_setup_kvm_info(node); 1176 return 0; 1177 1178 out_unmap_rdist: 1179 for (i = 0; i < nr_redist_regions; i++) 1180 if (rdist_regs[i].redist_base) 1181 iounmap(rdist_regs[i].redist_base); 1182 kfree(rdist_regs); 1183 out_unmap_dist: 1184 iounmap(dist_base); 1185 return err; 1186 } 1187 1188 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 1189 1190 #ifdef CONFIG_ACPI 1191 static struct 1192 { 1193 void __iomem *dist_base; 1194 struct redist_region *redist_regs; 1195 u32 nr_redist_regions; 1196 bool single_redist; 1197 u32 maint_irq; 1198 int maint_irq_mode; 1199 phys_addr_t vcpu_base; 1200 } acpi_data __initdata; 1201 1202 static void __init 1203 gic_acpi_register_redist(phys_addr_t phys_base, void __iomem *redist_base) 1204 { 1205 static int count = 0; 1206 1207 acpi_data.redist_regs[count].phys_base = phys_base; 1208 acpi_data.redist_regs[count].redist_base = redist_base; 1209 acpi_data.redist_regs[count].single_redist = acpi_data.single_redist; 1210 count++; 1211 } 1212 1213 static int __init 1214 gic_acpi_parse_madt_redist(struct acpi_subtable_header *header, 1215 const unsigned long end) 1216 { 1217 struct acpi_madt_generic_redistributor *redist = 1218 (struct acpi_madt_generic_redistributor *)header; 1219 void __iomem *redist_base; 1220 1221 redist_base = ioremap(redist->base_address, redist->length); 1222 if (!redist_base) { 1223 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); 1224 return -ENOMEM; 1225 } 1226 1227 gic_acpi_register_redist(redist->base_address, redist_base); 1228 return 0; 1229 } 1230 1231 static int __init 1232 gic_acpi_parse_madt_gicc(struct acpi_subtable_header *header, 1233 const unsigned long end) 1234 { 1235 struct acpi_madt_generic_interrupt *gicc = 1236 (struct acpi_madt_generic_interrupt *)header; 1237 u32 reg = readl_relaxed(acpi_data.dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 1238 u32 size = reg == GIC_PIDR2_ARCH_GICv4 ? SZ_64K * 4 : SZ_64K * 2; 1239 void __iomem *redist_base; 1240 1241 redist_base = ioremap(gicc->gicr_base_address, size); 1242 if (!redist_base) 1243 return -ENOMEM; 1244 1245 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); 1246 return 0; 1247 } 1248 1249 static int __init gic_acpi_collect_gicr_base(void) 1250 { 1251 acpi_tbl_entry_handler redist_parser; 1252 enum acpi_madt_type type; 1253 1254 if (acpi_data.single_redist) { 1255 type = ACPI_MADT_TYPE_GENERIC_INTERRUPT; 1256 redist_parser = gic_acpi_parse_madt_gicc; 1257 } else { 1258 type = ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR; 1259 redist_parser = gic_acpi_parse_madt_redist; 1260 } 1261 1262 /* Collect redistributor base addresses in GICR entries */ 1263 if (acpi_table_parse_madt(type, redist_parser, 0) > 0) 1264 return 0; 1265 1266 pr_info("No valid GICR entries exist\n"); 1267 return -ENODEV; 1268 } 1269 1270 static int __init gic_acpi_match_gicr(struct acpi_subtable_header *header, 1271 const unsigned long end) 1272 { 1273 /* Subtable presence means that redist exists, that's it */ 1274 return 0; 1275 } 1276 1277 static int __init gic_acpi_match_gicc(struct acpi_subtable_header *header, 1278 const unsigned long end) 1279 { 1280 struct acpi_madt_generic_interrupt *gicc = 1281 (struct acpi_madt_generic_interrupt *)header; 1282 1283 /* 1284 * If GICC is enabled and has valid gicr base address, then it means 1285 * GICR base is presented via GICC 1286 */ 1287 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) 1288 return 0; 1289 1290 return -ENODEV; 1291 } 1292 1293 static int __init gic_acpi_count_gicr_regions(void) 1294 { 1295 int count; 1296 1297 /* 1298 * Count how many redistributor regions we have. It is not allowed 1299 * to mix redistributor description, GICR and GICC subtables have to be 1300 * mutually exclusive. 1301 */ 1302 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_REDISTRIBUTOR, 1303 gic_acpi_match_gicr, 0); 1304 if (count > 0) { 1305 acpi_data.single_redist = false; 1306 return count; 1307 } 1308 1309 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1310 gic_acpi_match_gicc, 0); 1311 if (count > 0) 1312 acpi_data.single_redist = true; 1313 1314 return count; 1315 } 1316 1317 static bool __init acpi_validate_gic_table(struct acpi_subtable_header *header, 1318 struct acpi_probe_entry *ape) 1319 { 1320 struct acpi_madt_generic_distributor *dist; 1321 int count; 1322 1323 dist = (struct acpi_madt_generic_distributor *)header; 1324 if (dist->version != ape->driver_data) 1325 return false; 1326 1327 /* We need to do that exercise anyway, the sooner the better */ 1328 count = gic_acpi_count_gicr_regions(); 1329 if (count <= 0) 1330 return false; 1331 1332 acpi_data.nr_redist_regions = count; 1333 return true; 1334 } 1335 1336 static int __init gic_acpi_parse_virt_madt_gicc(struct acpi_subtable_header *header, 1337 const unsigned long end) 1338 { 1339 struct acpi_madt_generic_interrupt *gicc = 1340 (struct acpi_madt_generic_interrupt *)header; 1341 int maint_irq_mode; 1342 static int first_madt = true; 1343 1344 /* Skip unusable CPUs */ 1345 if (!(gicc->flags & ACPI_MADT_ENABLED)) 1346 return 0; 1347 1348 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? 1349 ACPI_EDGE_SENSITIVE : ACPI_LEVEL_SENSITIVE; 1350 1351 if (first_madt) { 1352 first_madt = false; 1353 1354 acpi_data.maint_irq = gicc->vgic_interrupt; 1355 acpi_data.maint_irq_mode = maint_irq_mode; 1356 acpi_data.vcpu_base = gicc->gicv_base_address; 1357 1358 return 0; 1359 } 1360 1361 /* 1362 * The maintenance interrupt and GICV should be the same for every CPU 1363 */ 1364 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || 1365 (acpi_data.maint_irq_mode != maint_irq_mode) || 1366 (acpi_data.vcpu_base != gicc->gicv_base_address)) 1367 return -EINVAL; 1368 1369 return 0; 1370 } 1371 1372 static bool __init gic_acpi_collect_virt_info(void) 1373 { 1374 int count; 1375 1376 count = acpi_table_parse_madt(ACPI_MADT_TYPE_GENERIC_INTERRUPT, 1377 gic_acpi_parse_virt_madt_gicc, 0); 1378 1379 return (count > 0); 1380 } 1381 1382 #define ACPI_GICV3_DIST_MEM_SIZE (SZ_64K) 1383 #define ACPI_GICV2_VCTRL_MEM_SIZE (SZ_4K) 1384 #define ACPI_GICV2_VCPU_MEM_SIZE (SZ_8K) 1385 1386 static void __init gic_acpi_setup_kvm_info(void) 1387 { 1388 int irq; 1389 1390 if (!gic_acpi_collect_virt_info()) { 1391 pr_warn("Unable to get hardware information used for virtualization\n"); 1392 return; 1393 } 1394 1395 gic_v3_kvm_info.type = GIC_V3; 1396 1397 irq = acpi_register_gsi(NULL, acpi_data.maint_irq, 1398 acpi_data.maint_irq_mode, 1399 ACPI_ACTIVE_HIGH); 1400 if (irq <= 0) 1401 return; 1402 1403 gic_v3_kvm_info.maint_irq = irq; 1404 1405 if (acpi_data.vcpu_base) { 1406 struct resource *vcpu = &gic_v3_kvm_info.vcpu; 1407 1408 vcpu->flags = IORESOURCE_MEM; 1409 vcpu->start = acpi_data.vcpu_base; 1410 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; 1411 } 1412 1413 gic_set_kvm_info(&gic_v3_kvm_info); 1414 } 1415 1416 static int __init 1417 gic_acpi_init(struct acpi_subtable_header *header, const unsigned long end) 1418 { 1419 struct acpi_madt_generic_distributor *dist; 1420 struct fwnode_handle *domain_handle; 1421 size_t size; 1422 int i, err; 1423 1424 /* Get distributor base address */ 1425 dist = (struct acpi_madt_generic_distributor *)header; 1426 acpi_data.dist_base = ioremap(dist->base_address, 1427 ACPI_GICV3_DIST_MEM_SIZE); 1428 if (!acpi_data.dist_base) { 1429 pr_err("Unable to map GICD registers\n"); 1430 return -ENOMEM; 1431 } 1432 1433 err = gic_validate_dist_version(acpi_data.dist_base); 1434 if (err) { 1435 pr_err("No distributor detected at @%p, giving up", 1436 acpi_data.dist_base); 1437 goto out_dist_unmap; 1438 } 1439 1440 size = sizeof(*acpi_data.redist_regs) * acpi_data.nr_redist_regions; 1441 acpi_data.redist_regs = kzalloc(size, GFP_KERNEL); 1442 if (!acpi_data.redist_regs) { 1443 err = -ENOMEM; 1444 goto out_dist_unmap; 1445 } 1446 1447 err = gic_acpi_collect_gicr_base(); 1448 if (err) 1449 goto out_redist_unmap; 1450 1451 domain_handle = irq_domain_alloc_fwnode(acpi_data.dist_base); 1452 if (!domain_handle) { 1453 err = -ENOMEM; 1454 goto out_redist_unmap; 1455 } 1456 1457 err = gic_init_bases(acpi_data.dist_base, acpi_data.redist_regs, 1458 acpi_data.nr_redist_regions, 0, domain_handle); 1459 if (err) 1460 goto out_fwhandle_free; 1461 1462 acpi_set_irq_model(ACPI_IRQ_MODEL_GIC, domain_handle); 1463 gic_acpi_setup_kvm_info(); 1464 1465 return 0; 1466 1467 out_fwhandle_free: 1468 irq_domain_free_fwnode(domain_handle); 1469 out_redist_unmap: 1470 for (i = 0; i < acpi_data.nr_redist_regions; i++) 1471 if (acpi_data.redist_regs[i].redist_base) 1472 iounmap(acpi_data.redist_regs[i].redist_base); 1473 kfree(acpi_data.redist_regs); 1474 out_dist_unmap: 1475 iounmap(acpi_data.dist_base); 1476 return err; 1477 } 1478 IRQCHIP_ACPI_DECLARE(gic_v3, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1479 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V3, 1480 gic_acpi_init); 1481 IRQCHIP_ACPI_DECLARE(gic_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1482 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_V4, 1483 gic_acpi_init); 1484 IRQCHIP_ACPI_DECLARE(gic_v3_or_v4, ACPI_MADT_TYPE_GENERIC_DISTRIBUTOR, 1485 acpi_validate_gic_table, ACPI_MADT_GIC_VERSION_NONE, 1486 gic_acpi_init); 1487 #endif 1488