1 /* 2 * Copyright (C) 2013, 2014 ARM Limited, All Rights Reserved. 3 * Author: Marc Zyngier <marc.zyngier@arm.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 * 14 * You should have received a copy of the GNU General Public License 15 * along with this program. If not, see <http://www.gnu.org/licenses/>. 16 */ 17 18 #include <linux/cpu.h> 19 #include <linux/cpu_pm.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/of.h> 23 #include <linux/of_address.h> 24 #include <linux/of_irq.h> 25 #include <linux/percpu.h> 26 #include <linux/slab.h> 27 28 #include <linux/irqchip.h> 29 #include <linux/irqchip/arm-gic-v3.h> 30 31 #include <asm/cputype.h> 32 #include <asm/exception.h> 33 #include <asm/smp_plat.h> 34 #include <asm/virt.h> 35 36 #include "irq-gic-common.h" 37 38 struct redist_region { 39 void __iomem *redist_base; 40 phys_addr_t phys_base; 41 }; 42 43 struct gic_chip_data { 44 void __iomem *dist_base; 45 struct redist_region *redist_regions; 46 struct rdists rdists; 47 struct irq_domain *domain; 48 u64 redist_stride; 49 u32 nr_redist_regions; 50 unsigned int irq_nr; 51 }; 52 53 static struct gic_chip_data gic_data __read_mostly; 54 static struct static_key supports_deactivate = STATIC_KEY_INIT_TRUE; 55 56 #define gic_data_rdist() (this_cpu_ptr(gic_data.rdists.rdist)) 57 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base) 58 #define gic_data_rdist_sgi_base() (gic_data_rdist_rd_base() + SZ_64K) 59 60 /* Our default, arbitrary priority value. Linux only uses one anyway. */ 61 #define DEFAULT_PMR_VALUE 0xf0 62 63 static inline unsigned int gic_irq(struct irq_data *d) 64 { 65 return d->hwirq; 66 } 67 68 static inline int gic_irq_in_rdist(struct irq_data *d) 69 { 70 return gic_irq(d) < 32; 71 } 72 73 static inline void __iomem *gic_dist_base(struct irq_data *d) 74 { 75 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ 76 return gic_data_rdist_sgi_base(); 77 78 if (d->hwirq <= 1023) /* SPI -> dist_base */ 79 return gic_data.dist_base; 80 81 return NULL; 82 } 83 84 static void gic_do_wait_for_rwp(void __iomem *base) 85 { 86 u32 count = 1000000; /* 1s! */ 87 88 while (readl_relaxed(base + GICD_CTLR) & GICD_CTLR_RWP) { 89 count--; 90 if (!count) { 91 pr_err_ratelimited("RWP timeout, gone fishing\n"); 92 return; 93 } 94 cpu_relax(); 95 udelay(1); 96 }; 97 } 98 99 /* Wait for completion of a distributor change */ 100 static void gic_dist_wait_for_rwp(void) 101 { 102 gic_do_wait_for_rwp(gic_data.dist_base); 103 } 104 105 /* Wait for completion of a redistributor change */ 106 static void gic_redist_wait_for_rwp(void) 107 { 108 gic_do_wait_for_rwp(gic_data_rdist_rd_base()); 109 } 110 111 #ifdef CONFIG_ARM64 112 static DEFINE_STATIC_KEY_FALSE(is_cavium_thunderx); 113 114 static u64 __maybe_unused gic_read_iar(void) 115 { 116 if (static_branch_unlikely(&is_cavium_thunderx)) 117 return gic_read_iar_cavium_thunderx(); 118 else 119 return gic_read_iar_common(); 120 } 121 #endif 122 123 static void gic_enable_redist(bool enable) 124 { 125 void __iomem *rbase; 126 u32 count = 1000000; /* 1s! */ 127 u32 val; 128 129 rbase = gic_data_rdist_rd_base(); 130 131 val = readl_relaxed(rbase + GICR_WAKER); 132 if (enable) 133 /* Wake up this CPU redistributor */ 134 val &= ~GICR_WAKER_ProcessorSleep; 135 else 136 val |= GICR_WAKER_ProcessorSleep; 137 writel_relaxed(val, rbase + GICR_WAKER); 138 139 if (!enable) { /* Check that GICR_WAKER is writeable */ 140 val = readl_relaxed(rbase + GICR_WAKER); 141 if (!(val & GICR_WAKER_ProcessorSleep)) 142 return; /* No PM support in this redistributor */ 143 } 144 145 while (count--) { 146 val = readl_relaxed(rbase + GICR_WAKER); 147 if (enable ^ (val & GICR_WAKER_ChildrenAsleep)) 148 break; 149 cpu_relax(); 150 udelay(1); 151 }; 152 if (!count) 153 pr_err_ratelimited("redistributor failed to %s...\n", 154 enable ? "wakeup" : "sleep"); 155 } 156 157 /* 158 * Routines to disable, enable, EOI and route interrupts 159 */ 160 static int gic_peek_irq(struct irq_data *d, u32 offset) 161 { 162 u32 mask = 1 << (gic_irq(d) % 32); 163 void __iomem *base; 164 165 if (gic_irq_in_rdist(d)) 166 base = gic_data_rdist_sgi_base(); 167 else 168 base = gic_data.dist_base; 169 170 return !!(readl_relaxed(base + offset + (gic_irq(d) / 32) * 4) & mask); 171 } 172 173 static void gic_poke_irq(struct irq_data *d, u32 offset) 174 { 175 u32 mask = 1 << (gic_irq(d) % 32); 176 void (*rwp_wait)(void); 177 void __iomem *base; 178 179 if (gic_irq_in_rdist(d)) { 180 base = gic_data_rdist_sgi_base(); 181 rwp_wait = gic_redist_wait_for_rwp; 182 } else { 183 base = gic_data.dist_base; 184 rwp_wait = gic_dist_wait_for_rwp; 185 } 186 187 writel_relaxed(mask, base + offset + (gic_irq(d) / 32) * 4); 188 rwp_wait(); 189 } 190 191 static void gic_mask_irq(struct irq_data *d) 192 { 193 gic_poke_irq(d, GICD_ICENABLER); 194 } 195 196 static void gic_eoimode1_mask_irq(struct irq_data *d) 197 { 198 gic_mask_irq(d); 199 /* 200 * When masking a forwarded interrupt, make sure it is 201 * deactivated as well. 202 * 203 * This ensures that an interrupt that is getting 204 * disabled/masked will not get "stuck", because there is 205 * noone to deactivate it (guest is being terminated). 206 */ 207 if (irqd_is_forwarded_to_vcpu(d)) 208 gic_poke_irq(d, GICD_ICACTIVER); 209 } 210 211 static void gic_unmask_irq(struct irq_data *d) 212 { 213 gic_poke_irq(d, GICD_ISENABLER); 214 } 215 216 static int gic_irq_set_irqchip_state(struct irq_data *d, 217 enum irqchip_irq_state which, bool val) 218 { 219 u32 reg; 220 221 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 222 return -EINVAL; 223 224 switch (which) { 225 case IRQCHIP_STATE_PENDING: 226 reg = val ? GICD_ISPENDR : GICD_ICPENDR; 227 break; 228 229 case IRQCHIP_STATE_ACTIVE: 230 reg = val ? GICD_ISACTIVER : GICD_ICACTIVER; 231 break; 232 233 case IRQCHIP_STATE_MASKED: 234 reg = val ? GICD_ICENABLER : GICD_ISENABLER; 235 break; 236 237 default: 238 return -EINVAL; 239 } 240 241 gic_poke_irq(d, reg); 242 return 0; 243 } 244 245 static int gic_irq_get_irqchip_state(struct irq_data *d, 246 enum irqchip_irq_state which, bool *val) 247 { 248 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ 249 return -EINVAL; 250 251 switch (which) { 252 case IRQCHIP_STATE_PENDING: 253 *val = gic_peek_irq(d, GICD_ISPENDR); 254 break; 255 256 case IRQCHIP_STATE_ACTIVE: 257 *val = gic_peek_irq(d, GICD_ISACTIVER); 258 break; 259 260 case IRQCHIP_STATE_MASKED: 261 *val = !gic_peek_irq(d, GICD_ISENABLER); 262 break; 263 264 default: 265 return -EINVAL; 266 } 267 268 return 0; 269 } 270 271 static void gic_eoi_irq(struct irq_data *d) 272 { 273 gic_write_eoir(gic_irq(d)); 274 } 275 276 static void gic_eoimode1_eoi_irq(struct irq_data *d) 277 { 278 /* 279 * No need to deactivate an LPI, or an interrupt that 280 * is is getting forwarded to a vcpu. 281 */ 282 if (gic_irq(d) >= 8192 || irqd_is_forwarded_to_vcpu(d)) 283 return; 284 gic_write_dir(gic_irq(d)); 285 } 286 287 static int gic_set_type(struct irq_data *d, unsigned int type) 288 { 289 unsigned int irq = gic_irq(d); 290 void (*rwp_wait)(void); 291 void __iomem *base; 292 293 /* Interrupt configuration for SGIs can't be changed */ 294 if (irq < 16) 295 return -EINVAL; 296 297 /* SPIs have restrictions on the supported types */ 298 if (irq >= 32 && type != IRQ_TYPE_LEVEL_HIGH && 299 type != IRQ_TYPE_EDGE_RISING) 300 return -EINVAL; 301 302 if (gic_irq_in_rdist(d)) { 303 base = gic_data_rdist_sgi_base(); 304 rwp_wait = gic_redist_wait_for_rwp; 305 } else { 306 base = gic_data.dist_base; 307 rwp_wait = gic_dist_wait_for_rwp; 308 } 309 310 return gic_configure_irq(irq, type, base, rwp_wait); 311 } 312 313 static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu) 314 { 315 if (vcpu) 316 irqd_set_forwarded_to_vcpu(d); 317 else 318 irqd_clr_forwarded_to_vcpu(d); 319 return 0; 320 } 321 322 static u64 gic_mpidr_to_affinity(unsigned long mpidr) 323 { 324 u64 aff; 325 326 aff = ((u64)MPIDR_AFFINITY_LEVEL(mpidr, 3) << 32 | 327 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 328 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 329 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 330 331 return aff; 332 } 333 334 static asmlinkage void __exception_irq_entry gic_handle_irq(struct pt_regs *regs) 335 { 336 u32 irqnr; 337 338 do { 339 irqnr = gic_read_iar(); 340 341 if (likely(irqnr > 15 && irqnr < 1020) || irqnr >= 8192) { 342 int err; 343 344 if (static_key_true(&supports_deactivate)) 345 gic_write_eoir(irqnr); 346 347 err = handle_domain_irq(gic_data.domain, irqnr, regs); 348 if (err) { 349 WARN_ONCE(true, "Unexpected interrupt received!\n"); 350 if (static_key_true(&supports_deactivate)) { 351 if (irqnr < 8192) 352 gic_write_dir(irqnr); 353 } else { 354 gic_write_eoir(irqnr); 355 } 356 } 357 continue; 358 } 359 if (irqnr < 16) { 360 gic_write_eoir(irqnr); 361 if (static_key_true(&supports_deactivate)) 362 gic_write_dir(irqnr); 363 #ifdef CONFIG_SMP 364 handle_IPI(irqnr, regs); 365 #else 366 WARN_ONCE(true, "Unexpected SGI received!\n"); 367 #endif 368 continue; 369 } 370 } while (irqnr != ICC_IAR1_EL1_SPURIOUS); 371 } 372 373 static void __init gic_dist_init(void) 374 { 375 unsigned int i; 376 u64 affinity; 377 void __iomem *base = gic_data.dist_base; 378 379 /* Disable the distributor */ 380 writel_relaxed(0, base + GICD_CTLR); 381 gic_dist_wait_for_rwp(); 382 383 gic_dist_config(base, gic_data.irq_nr, gic_dist_wait_for_rwp); 384 385 /* Enable distributor with ARE, Group1 */ 386 writel_relaxed(GICD_CTLR_ARE_NS | GICD_CTLR_ENABLE_G1A | GICD_CTLR_ENABLE_G1, 387 base + GICD_CTLR); 388 389 /* 390 * Set all global interrupts to the boot CPU only. ARE must be 391 * enabled. 392 */ 393 affinity = gic_mpidr_to_affinity(cpu_logical_map(smp_processor_id())); 394 for (i = 32; i < gic_data.irq_nr; i++) 395 gic_write_irouter(affinity, base + GICD_IROUTER + i * 8); 396 } 397 398 static int gic_populate_rdist(void) 399 { 400 unsigned long mpidr = cpu_logical_map(smp_processor_id()); 401 u64 typer; 402 u32 aff; 403 int i; 404 405 /* 406 * Convert affinity to a 32bit value that can be matched to 407 * GICR_TYPER bits [63:32]. 408 */ 409 aff = (MPIDR_AFFINITY_LEVEL(mpidr, 3) << 24 | 410 MPIDR_AFFINITY_LEVEL(mpidr, 2) << 16 | 411 MPIDR_AFFINITY_LEVEL(mpidr, 1) << 8 | 412 MPIDR_AFFINITY_LEVEL(mpidr, 0)); 413 414 for (i = 0; i < gic_data.nr_redist_regions; i++) { 415 void __iomem *ptr = gic_data.redist_regions[i].redist_base; 416 u32 reg; 417 418 reg = readl_relaxed(ptr + GICR_PIDR2) & GIC_PIDR2_ARCH_MASK; 419 if (reg != GIC_PIDR2_ARCH_GICv3 && 420 reg != GIC_PIDR2_ARCH_GICv4) { /* We're in trouble... */ 421 pr_warn("No redistributor present @%p\n", ptr); 422 break; 423 } 424 425 do { 426 typer = gic_read_typer(ptr + GICR_TYPER); 427 if ((typer >> 32) == aff) { 428 u64 offset = ptr - gic_data.redist_regions[i].redist_base; 429 gic_data_rdist_rd_base() = ptr; 430 gic_data_rdist()->phys_base = gic_data.redist_regions[i].phys_base + offset; 431 pr_info("CPU%d: found redistributor %lx region %d:%pa\n", 432 smp_processor_id(), mpidr, i, 433 &gic_data_rdist()->phys_base); 434 return 0; 435 } 436 437 if (gic_data.redist_stride) { 438 ptr += gic_data.redist_stride; 439 } else { 440 ptr += SZ_64K * 2; /* Skip RD_base + SGI_base */ 441 if (typer & GICR_TYPER_VLPIS) 442 ptr += SZ_64K * 2; /* Skip VLPI_base + reserved page */ 443 } 444 } while (!(typer & GICR_TYPER_LAST)); 445 } 446 447 /* We couldn't even deal with ourselves... */ 448 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", 449 smp_processor_id(), mpidr); 450 return -ENODEV; 451 } 452 453 static void gic_cpu_sys_reg_init(void) 454 { 455 /* 456 * Need to check that the SRE bit has actually been set. If 457 * not, it means that SRE is disabled at EL2. We're going to 458 * die painfully, and there is nothing we can do about it. 459 * 460 * Kindly inform the luser. 461 */ 462 if (!gic_enable_sre()) 463 pr_err("GIC: unable to set SRE (disabled at EL2), panic ahead\n"); 464 465 /* Set priority mask register */ 466 gic_write_pmr(DEFAULT_PMR_VALUE); 467 468 if (static_key_true(&supports_deactivate)) { 469 /* EOI drops priority only (mode 1) */ 470 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop); 471 } else { 472 /* EOI deactivates interrupt too (mode 0) */ 473 gic_write_ctlr(ICC_CTLR_EL1_EOImode_drop_dir); 474 } 475 476 /* ... and let's hit the road... */ 477 gic_write_grpen1(1); 478 } 479 480 static int gic_dist_supports_lpis(void) 481 { 482 return !!(readl_relaxed(gic_data.dist_base + GICD_TYPER) & GICD_TYPER_LPIS); 483 } 484 485 static void gic_cpu_init(void) 486 { 487 void __iomem *rbase; 488 489 /* Register ourselves with the rest of the world */ 490 if (gic_populate_rdist()) 491 return; 492 493 gic_enable_redist(true); 494 495 rbase = gic_data_rdist_sgi_base(); 496 497 gic_cpu_config(rbase, gic_redist_wait_for_rwp); 498 499 /* Give LPIs a spin */ 500 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 501 its_cpu_init(); 502 503 /* initialise system registers */ 504 gic_cpu_sys_reg_init(); 505 } 506 507 #ifdef CONFIG_SMP 508 static int gic_secondary_init(struct notifier_block *nfb, 509 unsigned long action, void *hcpu) 510 { 511 if (action == CPU_STARTING || action == CPU_STARTING_FROZEN) 512 gic_cpu_init(); 513 return NOTIFY_OK; 514 } 515 516 /* 517 * Notifier for enabling the GIC CPU interface. Set an arbitrarily high 518 * priority because the GIC needs to be up before the ARM generic timers. 519 */ 520 static struct notifier_block gic_cpu_notifier = { 521 .notifier_call = gic_secondary_init, 522 .priority = 100, 523 }; 524 525 static u16 gic_compute_target_list(int *base_cpu, const struct cpumask *mask, 526 unsigned long cluster_id) 527 { 528 int cpu = *base_cpu; 529 unsigned long mpidr = cpu_logical_map(cpu); 530 u16 tlist = 0; 531 532 while (cpu < nr_cpu_ids) { 533 /* 534 * If we ever get a cluster of more than 16 CPUs, just 535 * scream and skip that CPU. 536 */ 537 if (WARN_ON((mpidr & 0xff) >= 16)) 538 goto out; 539 540 tlist |= 1 << (mpidr & 0xf); 541 542 cpu = cpumask_next(cpu, mask); 543 if (cpu >= nr_cpu_ids) 544 goto out; 545 546 mpidr = cpu_logical_map(cpu); 547 548 if (cluster_id != (mpidr & ~0xffUL)) { 549 cpu--; 550 goto out; 551 } 552 } 553 out: 554 *base_cpu = cpu; 555 return tlist; 556 } 557 558 #define MPIDR_TO_SGI_AFFINITY(cluster_id, level) \ 559 (MPIDR_AFFINITY_LEVEL(cluster_id, level) \ 560 << ICC_SGI1R_AFFINITY_## level ##_SHIFT) 561 562 static void gic_send_sgi(u64 cluster_id, u16 tlist, unsigned int irq) 563 { 564 u64 val; 565 566 val = (MPIDR_TO_SGI_AFFINITY(cluster_id, 3) | 567 MPIDR_TO_SGI_AFFINITY(cluster_id, 2) | 568 irq << ICC_SGI1R_SGI_ID_SHIFT | 569 MPIDR_TO_SGI_AFFINITY(cluster_id, 1) | 570 tlist << ICC_SGI1R_TARGET_LIST_SHIFT); 571 572 pr_debug("CPU%d: ICC_SGI1R_EL1 %llx\n", smp_processor_id(), val); 573 gic_write_sgi1r(val); 574 } 575 576 static void gic_raise_softirq(const struct cpumask *mask, unsigned int irq) 577 { 578 int cpu; 579 580 if (WARN_ON(irq >= 16)) 581 return; 582 583 /* 584 * Ensure that stores to Normal memory are visible to the 585 * other CPUs before issuing the IPI. 586 */ 587 smp_wmb(); 588 589 for_each_cpu(cpu, mask) { 590 unsigned long cluster_id = cpu_logical_map(cpu) & ~0xffUL; 591 u16 tlist; 592 593 tlist = gic_compute_target_list(&cpu, mask, cluster_id); 594 gic_send_sgi(cluster_id, tlist, irq); 595 } 596 597 /* Force the above writes to ICC_SGI1R_EL1 to be executed */ 598 isb(); 599 } 600 601 static void gic_smp_init(void) 602 { 603 set_smp_cross_call(gic_raise_softirq); 604 register_cpu_notifier(&gic_cpu_notifier); 605 } 606 607 static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val, 608 bool force) 609 { 610 unsigned int cpu = cpumask_any_and(mask_val, cpu_online_mask); 611 void __iomem *reg; 612 int enabled; 613 u64 val; 614 615 if (gic_irq_in_rdist(d)) 616 return -EINVAL; 617 618 /* If interrupt was enabled, disable it first */ 619 enabled = gic_peek_irq(d, GICD_ISENABLER); 620 if (enabled) 621 gic_mask_irq(d); 622 623 reg = gic_dist_base(d) + GICD_IROUTER + (gic_irq(d) * 8); 624 val = gic_mpidr_to_affinity(cpu_logical_map(cpu)); 625 626 gic_write_irouter(val, reg); 627 628 /* 629 * If the interrupt was enabled, enabled it again. Otherwise, 630 * just wait for the distributor to have digested our changes. 631 */ 632 if (enabled) 633 gic_unmask_irq(d); 634 else 635 gic_dist_wait_for_rwp(); 636 637 return IRQ_SET_MASK_OK; 638 } 639 #else 640 #define gic_set_affinity NULL 641 #define gic_smp_init() do { } while(0) 642 #endif 643 644 #ifdef CONFIG_CPU_PM 645 static int gic_cpu_pm_notifier(struct notifier_block *self, 646 unsigned long cmd, void *v) 647 { 648 if (cmd == CPU_PM_EXIT) { 649 gic_enable_redist(true); 650 gic_cpu_sys_reg_init(); 651 } else if (cmd == CPU_PM_ENTER) { 652 gic_write_grpen1(0); 653 gic_enable_redist(false); 654 } 655 return NOTIFY_OK; 656 } 657 658 static struct notifier_block gic_cpu_pm_notifier_block = { 659 .notifier_call = gic_cpu_pm_notifier, 660 }; 661 662 static void gic_cpu_pm_init(void) 663 { 664 cpu_pm_register_notifier(&gic_cpu_pm_notifier_block); 665 } 666 667 #else 668 static inline void gic_cpu_pm_init(void) { } 669 #endif /* CONFIG_CPU_PM */ 670 671 static struct irq_chip gic_chip = { 672 .name = "GICv3", 673 .irq_mask = gic_mask_irq, 674 .irq_unmask = gic_unmask_irq, 675 .irq_eoi = gic_eoi_irq, 676 .irq_set_type = gic_set_type, 677 .irq_set_affinity = gic_set_affinity, 678 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 679 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 680 .flags = IRQCHIP_SET_TYPE_MASKED, 681 }; 682 683 static struct irq_chip gic_eoimode1_chip = { 684 .name = "GICv3", 685 .irq_mask = gic_eoimode1_mask_irq, 686 .irq_unmask = gic_unmask_irq, 687 .irq_eoi = gic_eoimode1_eoi_irq, 688 .irq_set_type = gic_set_type, 689 .irq_set_affinity = gic_set_affinity, 690 .irq_get_irqchip_state = gic_irq_get_irqchip_state, 691 .irq_set_irqchip_state = gic_irq_set_irqchip_state, 692 .irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity, 693 .flags = IRQCHIP_SET_TYPE_MASKED, 694 }; 695 696 #define GIC_ID_NR (1U << gic_data.rdists.id_bits) 697 698 static int gic_irq_domain_map(struct irq_domain *d, unsigned int irq, 699 irq_hw_number_t hw) 700 { 701 struct irq_chip *chip = &gic_chip; 702 703 if (static_key_true(&supports_deactivate)) 704 chip = &gic_eoimode1_chip; 705 706 /* SGIs are private to the core kernel */ 707 if (hw < 16) 708 return -EPERM; 709 /* Nothing here */ 710 if (hw >= gic_data.irq_nr && hw < 8192) 711 return -EPERM; 712 /* Off limits */ 713 if (hw >= GIC_ID_NR) 714 return -EPERM; 715 716 /* PPIs */ 717 if (hw < 32) { 718 irq_set_percpu_devid(irq); 719 irq_domain_set_info(d, irq, hw, chip, d->host_data, 720 handle_percpu_devid_irq, NULL, NULL); 721 irq_set_status_flags(irq, IRQ_NOAUTOEN); 722 } 723 /* SPIs */ 724 if (hw >= 32 && hw < gic_data.irq_nr) { 725 irq_domain_set_info(d, irq, hw, chip, d->host_data, 726 handle_fasteoi_irq, NULL, NULL); 727 irq_set_probe(irq); 728 } 729 /* LPIs */ 730 if (hw >= 8192 && hw < GIC_ID_NR) { 731 if (!gic_dist_supports_lpis()) 732 return -EPERM; 733 irq_domain_set_info(d, irq, hw, chip, d->host_data, 734 handle_fasteoi_irq, NULL, NULL); 735 } 736 737 return 0; 738 } 739 740 static int gic_irq_domain_translate(struct irq_domain *d, 741 struct irq_fwspec *fwspec, 742 unsigned long *hwirq, 743 unsigned int *type) 744 { 745 if (is_of_node(fwspec->fwnode)) { 746 if (fwspec->param_count < 3) 747 return -EINVAL; 748 749 switch (fwspec->param[0]) { 750 case 0: /* SPI */ 751 *hwirq = fwspec->param[1] + 32; 752 break; 753 case 1: /* PPI */ 754 *hwirq = fwspec->param[1] + 16; 755 break; 756 case GIC_IRQ_TYPE_LPI: /* LPI */ 757 *hwirq = fwspec->param[1]; 758 break; 759 default: 760 return -EINVAL; 761 } 762 763 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; 764 return 0; 765 } 766 767 return -EINVAL; 768 } 769 770 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, 771 unsigned int nr_irqs, void *arg) 772 { 773 int i, ret; 774 irq_hw_number_t hwirq; 775 unsigned int type = IRQ_TYPE_NONE; 776 struct irq_fwspec *fwspec = arg; 777 778 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); 779 if (ret) 780 return ret; 781 782 for (i = 0; i < nr_irqs; i++) 783 gic_irq_domain_map(domain, virq + i, hwirq + i); 784 785 return 0; 786 } 787 788 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, 789 unsigned int nr_irqs) 790 { 791 int i; 792 793 for (i = 0; i < nr_irqs; i++) { 794 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); 795 irq_set_handler(virq + i, NULL); 796 irq_domain_reset_irq_data(d); 797 } 798 } 799 800 static const struct irq_domain_ops gic_irq_domain_ops = { 801 .translate = gic_irq_domain_translate, 802 .alloc = gic_irq_domain_alloc, 803 .free = gic_irq_domain_free, 804 }; 805 806 static void gicv3_enable_quirks(void) 807 { 808 #ifdef CONFIG_ARM64 809 if (cpus_have_cap(ARM64_WORKAROUND_CAVIUM_23154)) 810 static_branch_enable(&is_cavium_thunderx); 811 #endif 812 } 813 814 static int __init gic_of_init(struct device_node *node, struct device_node *parent) 815 { 816 void __iomem *dist_base; 817 struct redist_region *rdist_regs; 818 u64 redist_stride; 819 u32 nr_redist_regions; 820 u32 typer; 821 u32 reg; 822 int gic_irqs; 823 int err; 824 int i; 825 826 dist_base = of_iomap(node, 0); 827 if (!dist_base) { 828 pr_err("%s: unable to map gic dist registers\n", 829 node->full_name); 830 return -ENXIO; 831 } 832 833 reg = readl_relaxed(dist_base + GICD_PIDR2) & GIC_PIDR2_ARCH_MASK; 834 if (reg != GIC_PIDR2_ARCH_GICv3 && reg != GIC_PIDR2_ARCH_GICv4) { 835 pr_err("%s: no distributor detected, giving up\n", 836 node->full_name); 837 err = -ENODEV; 838 goto out_unmap_dist; 839 } 840 841 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) 842 nr_redist_regions = 1; 843 844 rdist_regs = kzalloc(sizeof(*rdist_regs) * nr_redist_regions, GFP_KERNEL); 845 if (!rdist_regs) { 846 err = -ENOMEM; 847 goto out_unmap_dist; 848 } 849 850 for (i = 0; i < nr_redist_regions; i++) { 851 struct resource res; 852 int ret; 853 854 ret = of_address_to_resource(node, 1 + i, &res); 855 rdist_regs[i].redist_base = of_iomap(node, 1 + i); 856 if (ret || !rdist_regs[i].redist_base) { 857 pr_err("%s: couldn't map region %d\n", 858 node->full_name, i); 859 err = -ENODEV; 860 goto out_unmap_rdist; 861 } 862 rdist_regs[i].phys_base = res.start; 863 } 864 865 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) 866 redist_stride = 0; 867 868 if (!is_hyp_mode_available()) 869 static_key_slow_dec(&supports_deactivate); 870 871 if (static_key_true(&supports_deactivate)) 872 pr_info("GIC: Using split EOI/Deactivate mode\n"); 873 874 gic_data.dist_base = dist_base; 875 gic_data.redist_regions = rdist_regs; 876 gic_data.nr_redist_regions = nr_redist_regions; 877 gic_data.redist_stride = redist_stride; 878 879 gicv3_enable_quirks(); 880 881 /* 882 * Find out how many interrupts are supported. 883 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) 884 */ 885 typer = readl_relaxed(gic_data.dist_base + GICD_TYPER); 886 gic_data.rdists.id_bits = GICD_TYPER_ID_BITS(typer); 887 gic_irqs = GICD_TYPER_IRQS(typer); 888 if (gic_irqs > 1020) 889 gic_irqs = 1020; 890 gic_data.irq_nr = gic_irqs; 891 892 gic_data.domain = irq_domain_add_tree(node, &gic_irq_domain_ops, 893 &gic_data); 894 gic_data.rdists.rdist = alloc_percpu(typeof(*gic_data.rdists.rdist)); 895 896 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { 897 err = -ENOMEM; 898 goto out_free; 899 } 900 901 set_handle_irq(gic_handle_irq); 902 903 if (IS_ENABLED(CONFIG_ARM_GIC_V3_ITS) && gic_dist_supports_lpis()) 904 its_init(node, &gic_data.rdists, gic_data.domain); 905 906 gic_smp_init(); 907 gic_dist_init(); 908 gic_cpu_init(); 909 gic_cpu_pm_init(); 910 911 return 0; 912 913 out_free: 914 if (gic_data.domain) 915 irq_domain_remove(gic_data.domain); 916 free_percpu(gic_data.rdists.rdist); 917 out_unmap_rdist: 918 for (i = 0; i < nr_redist_regions; i++) 919 if (rdist_regs[i].redist_base) 920 iounmap(rdist_regs[i].redist_base); 921 kfree(rdist_regs); 922 out_unmap_dist: 923 iounmap(dist_base); 924 return err; 925 } 926 927 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init); 928